USO0RE42674E

(19) United States (12) Reissued Patent

(10) Patent Number:

Yang et a]. (54)

(45) Date of Reissued Patent:

CONTROL METHOD AND CIRCUIT WITH

(56)

'

U.S. PATENT DOCUMENTS

'

5,903,452 A

Inventors: Ta-Yung Yang, Milpitas, CA (US); Chien-Yuan Lin, Pan-Chiao (TW) -

.

-

-

6,836,415 B1 7,259,972 B2

(TW)

Appl. No.: 12/850,122

5/1999

Yang

12/2004 Yang et a1. 8/2007 Yang

7,362,592 B2

4/2008 Yang et a1.

7,362,593 B2

7,468,896 B2

4/2008

120008 Gong et a1‘

2008/0169802 A1

7/2008 Yang etal.

-

(73) Assignee. System General C0rp., Taipei Hsien (21)

Sep. 6, 2011

References Cited

INDIRECT INPUT VOLTAGE DETECTION BY SWITCHING CURRENT SLOPE DETECTION

(75)

US RE42,674 E

Yang et a1.

Primary Examiner * Jeffrey L Sterrett (74) Attorney, Agent, or Firm * Rosenberg, Klein & Lee

(22) Filed:

Aug. 4, 2010 Related US. Patent Documents

(57) ABSTRACT The present invention provides a method and a control circuit

Reissue of;

(64)

Patent No.1

7,616,461

to detect an input voltage for the control and protections of a

Issued:

Nov. 10, 2009

poWer converter. It includes a current sense circuit for gener

Appl. No.: Filed:

11/652,578 Jan. 12, 2007

ating a current signal in response to a switching current of a transformer. A detection circuit is coupled to sense the current

signal for generating a slope signal in response to a slope of (501mm ' '

' circuit "'fhd th e current s1'gnlAp a . rotection is urt er eve lpd o e to

H02H 7/122

(2006-01)

control the switching signal in accordance With the slope

(52)

US. Cl. ..................... .. 363/56.1; 363/21.01; 363/97

signal_ The level Of the Slope Signal is [Corrected] correlated

(58)

Field Of Classi?cation Search ............. .. 363/21.01,

t0 the input voltage of the power converter,

363/21.04, 21.05, 56.1, 56.11, 97, 131 See application ?le for complete search history.

36 Claims, 7 Drawing Sheets

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US. Patent

Sep. 6, 2011

Sheet 1 017

US RE42,674 E

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Sep. 6, 2011

Sheet 2 of7

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110

Sep. 6, 2011

Sheet 3 of7

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US. Patent

Sep. 6, 2011

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US RE42,674 E

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FIG. 9

US. Patent

Sep. 6, 2011

85

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US RE42,674 E

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US RE42,674 E 1

2

CONTROL METHOD AND CIRCUIT WITH INDIRECT INPUT VOLTAGE DETECTION BY SWITCHING CURRENT SLOPE DETECTION

After that, sampling the current signal during a second period will generate a second signal. The slope of the current signal is determined in accordance with the ?rst signal and the second signal. A protection circuit is further utilized to con

trol the switching signal in accordance with the slope signal. The level of the slope signal is [corrected] correlated to the input voltage of the power converter.

Matter enclosed in heavy brackets [ ] appears in the original patent but forms no part of this reissue speci?ca tion; matter printed in italics indicates the additions made by reissue.

BRIEF DESCRIPTION OF THE DRAWINGS

BACKGROUND OF THE INVENTION

The accompanying drawings are included to provide fur ther understanding of the invention, and are incorporated into and constitute a part of this speci?cation. The drawings illus trate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

1. Field of the Invention The present invention relates to power converters, and more speci?cally relates to the control of switching power converters.

FIG. 1 shows a circuit diagram of a traditional power

2. Description of Related Art Switching power converters have been widely used to pro vide regulated voltage and current. A transformer (an induc tive device) is used in the power converter for energy store and

converter having a resistor coupled to detect the input voltage 20

power transfer. FIG. 1 shows a circuit schematic of a tradi

FIG. 3 shows switching current waveforms according to the present invention.

tional power converter. A controller 15 generates a switching

signal S Wat an output terminal OUT to regulate the output of the power converter in response to a feedback signal VFB. In

general, the feedback signal VFB is obtained at a feedback terminal FB of the controller 15 by detecting the output volt age VO of the power converter through an optical-coupler or a feedback circuit including an auxiliary winding (Figure not

25

shown). The switching signal SW drives a power transistor 12 for

30

switching a transformer 10. The transformer 10 is connected to an input voltage VIN of the power converter. The energy of

the transformer 10 is transferred to the output voltage V0 of the power converter through a recti?er 17 and a capacitor 18.

A resistor RS is connected serially with the power transistor

35

12 to generate a current signal V, in response to a switching current IP of the transformer 10. The current signal V, is coupled to a current-sense terminal VS of the controller 15 for the control and protections of the power converter. A resistor

19 is further connected from the input voltage VIN to an input terminal IN of the controller 15 for over-voltage and under

of the power converter. FIG. 2 shows a circuit diagram of a preferred control circuit of a power converter according to the present invention.

FIG. 4 shows a circuit diagram of a preferred embodiment of a switching controller according to the present invention. FIG. 5 shows a circuit diagram of a preferred embodiment of an oscillation circuit according to the present invention. FIG. 6 shows a circuit diagram of a preferred embodiment of a VIN-circuit according to the present invention. FIG. 7 shows a circuit diagram of a preferred embodiment of a detection circuit according to the present invention. FIG. 8 shows a circuit schematic of a preferred embodi ment of a pulse generator according to the present invention. FIG. 9 shows signal-waveforms of the switching controller according to the present invention. FIG. 10 shows the circuit diagram of a preferred embodi ment of a VIN signal generator and a protection signal gen erator according to the present invention. FIG. 11 shows a circuit schematic of a preferred embodi

40

ment of a blanking circuit according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS

voltage protections, etc. Furthermore, the over-power protection of power converter

requires sensing the input voltage VIN to control the maxi mum output power as a constant. The approach was disclosed 45

FIG. 2 shows a circuit diagram of a preferred control circuit

as “PWM controller for controlling output power limit of a

of a power converter. The power converter includes a power

power supply” by Yang et al., US. Pat. No. 6,611,439. The

transistor 20, a transformer 30, a recti?er 40, a capacitor 45, a switching controller 50 and a resistor RS. The transformer 30

drawback of this prior art is the power loss caused by the

serves as an inductance device coupled to receive an input

resistor 19 especially when the input voltage VIN is high. The object of the present invention is to sense the input voltage VIN for the control and protections without the need of the

50

voltage VIN. The power transistor 20 is connected serially with the transformer 30 to switch the transformer 30. The

resistor 19 for saving power. Moreover, reducing input termi

resistor RS serves as a current sense circuit connected to the

nals of the controller 15 is another object of the present invention.

power transistor 20 to develop a current signal V, in response to a switching current IP of the transformer 30. The current signal V, represents the switching current IP. The current signal V, is coupled to a current-sense terminal VS of the

55

SUMMARY OF THE INVENTION

switching controller 50 for the control and protections of the power converter. An output terminal OUT of the switching

The present invention provides a method and a control

controller 50 generates a switching signal SWto control the

circuit to detect an input voltage for the control and protec

tions of a power converter. It includes a current sense circuit 60 power transistor 20 for regulating the output of the power

converter in response to the current signal VI and a feedback

to generate a current signal in response to a switching current of a transformer. The transformer is operated as an inductive device. A detection circuit is coupled to sense the current

signal VFB. The feedback signal VFB is generated at a feed

signal for generating a slope signal in response to a slope of the current signal. When a power transistor of the power converter is turned on, the detection circuit will sample the

current signal during a ?rst period to generate a ?rst signal.

65

back terminal FB of the switching circuit 50 for the feedback regulation in response to the output of the power converter. The energy of the transformer 30 is transferred to the output voltage V0 of the power converter through the recti?er 40 and

the capacitor 45.

US RE42,674 E 3

4

The switching controller 50 detects the input voltage VIN for the protections of the poWer converter. The input voltage

the current-limit signal VM. The negative input terminal of the comparator 62 and the negative input terminal of the com parator 63 are coupled to receive the current signal VI. The positive input terminal of the comparator 63 is coupled to receive the feedback signal VFB for the feedback loop control. FIG. 5 shoWs the circuit diagram of the oscillation circuit 100. A charge current 110 is coupled to a supply voltage VCC. The charge current 110 is serially connected With a sWitch 115 for charging a capacitor 130. A discharge current 120 is coupled to the ground. The discharge current 120 is serially connected With a sWitch 125 for discharging the capacitor 130. A ramp signal RAMP is therefore produced on the

VINis detected by sensing a slope of the switching current IP. FIG. 3 shoWs sWitching current Waveforms. The slope of the sWitching current IP is produced in response to the level of the

input voltage VIN. For example, the slopes 31, 32 and 33 are generated in response to the input voltages VIM, VIN2 and VIN3 respectively. The level of the input voltage is V, V,N2>V,N3. Once the sWitching signal SWis turned on, the sWitching current IP is generated accordantly,

(1)

capacitor 130. Comparators 150, 151, NAND gates 155, 156 and an inverter 158 are used to generate the oscillation signal IPS to control the sWitch 115. The oscillation signal IPS is further utiliZed to control the sWitch 125 through an inverter 159. The oscillation signal IPS is further transmitted to the 20

Where LP is the inductance of the primary Winding of the

transformer 30; TON is on time of the sWitching signal SW. FIG. 4 shoWs a circuit diagram of the sWitching controller 50. It includes a sWitching circuit 60 to generate the sWitching signal SWin response to an oscillation signal IPS. An oscil lation circuit 100 is developed to generate the oscillation

25

signal IPS and the timing signals S1, S2. Timing signals S l and S2 serve as sample signals outputted to aVIN-circuit 200. The VIN-circuit 200 is coupled to receive the current signal V, for

30

producing an input-voltage signal VV (shoWn in FIG. 10) in accordance With the slope of the current signal VI. Mean While, the VIN-circuit 200 generates a control signal ENB, a

current-limit signal VM and a blanking adjustment signal VB in response to the input-voltage signal VVfor poWer converter

35

protections. The sWitching circuit 60 includes a ?ip-?op 70 to generate

the sWitching signal SWthrough an AND gate 75. The input terminal of the AND gate 75 is connected to the output ter minal Q of the ?ip-?op 70 . Another input terminal of the AND gate 75 is connected to the oscillation circuit 100 to receive the oscillation signal IPS to limit the maximum on time of the

40

Vmfcircuit 200 and the sWitching circuit 60 respectively (shoWn in FIG. 4). The ramp signal RAMP is coupled to the negative input terminal of the comparator 150 and the positive input terminal of the comparator 151 respectively. Trip -point voltages VH and VL are connected to the positive input termi nal of the comparators 150 and the negative input terminal of the comparator 151 respectively. The ramp signal RAMP is thus sWing in betWeen the trip-point voltages VH and VL. The input terminal of the NAND gate 155 is coupled to the output terminal of the comparator 150. The input terminal of the NAND gate 156 is coupled to the output terminal of the comparator 151. Another input terminal of the NAND gate 156 is coupled to the output terminal of the NAND gate 155. The output terminal of the NAND gate 156 is coupled to another input terminal of the NAND gate 155. The output terminal of the NAND gate 155 is coupled to the input termi nal of the inverter 158. The oscillation signal IPS is generated by the output terminal of the inverter 158. The output terminal of the inverter 158 is further coupled to the input terminal of the inverter 159 to receive the oscillation signal IPS. The inverter 159 inverts the oscillation signal IPS to control the sWitch 125.

The negative input terminals of the comparators 160 and 170 are coupled to receive the ramp signal RAMP for gener

sWitching signal SW. The input terminal D of the ?ip-?op 70

ating the timing signals S 1 and S2. Threshold voltages V1 and

is coupled to the VIN-circuit 200 to receive the control signal ENB. The ?ip-?op 70 is enabled in response to the oscillation signal IPS coupled to the clock input terminal CK of the ?ip-?op 70 if the control signal ENB is enabled. The sWitching signal SWis coupled to a blanking circuit 80

V2 are connected to the positive input terminals of the com 45

connected to the input terminal of an AND gate 165 to gen

erate the ?rst timing signal S1. The output of the comparator 170 is connected to the input terminal of an AND gate 175 to

to generate a blanking signal SK in response to the sWitching signal S W. The blanking signal SK ensures a minimum on time

50

of the sWitching signal SWWhen the sWitching signal SW is enabled. The blanking adjustment signal VB is coupled to the

generate the second timing signal S2. The input terminals of the comparators 165 and 175 are further connected to receive

the oscillation signal IPS and the sWitching signal SW. Since the oscillation signal IPS is coupled to enable the sWitching

blanking circuit 80 to adjust the blanking time of the blanking signal SK. Therefore, the blanking time of the blanking signal SK Will be increased in response to the decrease of the input

parators 160 and 170 respectively. The level of the voltage is VH>V2>VI>VL. The output terminal of the comparator 160 is

signal S W and turn on the poWer transistor 20 (shoWn in FIG. 55

2) , the ?rst timing signal S1 is generated during a ?rst period

voltage VIN.

T 1 (shown in FIG. 9) When the poWer transistor 20 is turned

The blanking signal SK is connected to the input terminal of an NAND gate 66. The output terminal of the NAND gate 66 is coupled to the reset terminal R of the ?ip-?op 70 to reset the ?ip-?op 70. Another input terminal of the NAND gate 66 is connected to the output terminal of an NAND gate 65. The input terminal of the NAND gate 65 is connected to the output terminal of a comparator 62. Another input terminal of the

on. The second timing signal S2 is produced during a second period T2 (shoWn in FIG. 9) When the poWer transistor 20 is turned on. The ?rst timing signal S 1 and the second timing 60

includes a detection circuit 210 and a signal generation circuit

250. The detection circuit 210 generates a slope signal VSD by detecting the slope of the current signal VI. The slope of the

NAND gate 65 is connected to the output terminal of a com

parator 63. The comparator 62 is utiliZed to limit the maxi mum sWitching current IP. The positive input terminal of the comparator 62 is connected to the Vmfcircuit 200 to receive

signal S2 are synchronized With the oscillation signal IPS. FIG. 6 shoWs the circuit diagram of the VIN-circuit 200. It

65

current signal V, is measured in response to the oscillation

signal IPS and the timing signals S 1, S2. The signal generation circuit 250 further receives the slope signal VSD to generate

US RE42,674 E 5

6

the input-voltage signal VV (shown in FIG. 10), the control signal ENB, the current-limit signal VM and the blanking

Sampling the current signal V, during the second period T2 generates the second signal. The slope signal VSD is deter

adjustment signal VB.

mined in accordance With differential voltage of the ?rst

FIG. 210. A receive second ground

signal and the second signal. FIG. 10 shoWs the circuit diagram of the signal generation

7 is a preferred embodiment of the detection circuit ?rst terminal of a ?rst capacitor 223 is coupled to the current signal V, though a ?rst sWitch 215. A terminal of the capacitor 223 is connected to the via a third sWitch 216. A ?rst terminal of a second

circuit 250. It includes a V,N signal generator 300 and a

protection signal generator 350. The V,N signal generator 3 00 has an operational ampli?er 310 coupled to amplify the slope

capacitor 220 is coupled to receive the current signal V, as

signal VSD for generating the input-voltage signal VV. The

Well through a second sWitch 211. A second terminal of the

positive input terminal of the operational ampli?er 310 is coupled to receive the slope signal VSD. A resistor 315 is coupled betWeen the negative input terminal of the opera

second capacitor 220 is connected to the ground. The ?rst terminal of the second capacitor 220 is further connected to the ?rst terminal of the ?rst capacitor 223 through a fourth sWitch 212. The second sWitch 211 is controlled by the sec

tional ampli?er 310 and the ground. A resistor 316 is coupled

from the negative input terminal of the operational ampli?er

ond timing signal S2. The fourth sWitch 212 is controlled by the second timing signal S2 through an inverter 214. Both

310 to the output terminal of the operational ampli?er 310. Resistors 315 and 316 determine the gain of the ampli?cation.

sWitches 215 and 216 are controlled by the ?rst timing signal 8,. A ?rst terminal of a third capacitor 225 is coupled to the

The protection signal generator 350 serves as a protection circuit to control the sWitching signal SW in response to the

second terminal of the ?rst capacitor 223 via a ?fth sWitch 219. A second terminal of the third capacitor 225 is coupled to the ground. The ?fth sWitch 219 is controlled by a pulse signal SP. The pulse signal SP is produced in response to the oscil

lation signal IPS through a pulse generator 230. The slope signal VSD is generated on the third capacitor 225. The ?rst capacitor 223 is therefore coupled to sample-and

input-voltage signal VV. The protection signal generator 350 20

includes comparators 320, 325 and operational ampli?ers 330, 340 coupled to receive the input-voltage signal VV. A resistor 335 is coupled betWeen the negative input terminal of the operational ampli?er 330 and the input-voltage signal VV. A resistor 336 is coupled from the negative input terminal of

25

the operational ampli?er 330 to the output terminal of the operational ampli?er 330. Resistors 335 and 336 determine the gain for operational ampli?er 330. A resistor 345 is coupled betWeen the negative input terminal of the opera

hold the current signal V,through the sWitches 215 and 216 to generate a ?rst signal during the ?rst period T 1 (shoWn in FIG. 9) after the poWer transistor 20 (shoWn in FIG. 2) is turned on.

The second capacitor 220 is coupled to sample-and-hold the current signal V, through the second sWitch 211 to generate a

30

second signal during the second period T2 (shoWn in FIG. 9)

tional ampli?er 340 and the input-voltage signal VV. A resis tor 346 is coupled from the negative input terminal of the

after the poWer transistor 20 is turned on. The third capacitor

operational ampli?er 340 to the output terminal of the opera tional ampli?er 340. Resistors 345 and 346 determine the

225 is coupled to sample-and-hold the differential voltage of the ?rst signal and the second signal to generate the slope

gain for operational ampli?er 340. A reference voltage VR connects the positive input terminals of the operational ampli

signal VSD. The slope signal VSD is thus correlated to the slope of the current signal V,. The level of the slope signal VSD is [corrected] correlated to the input voltage V,N of the poWer converter. The slope signal VSD is increased in response to the increase of the input voltage V,N. FIG. 8 shoWs the schematic circuit diagram of the pulse

35

Threshold voltages VTH and VT, are coupled to compara tors 320 and 325 respectively. The over-voltage threshold VTH is coupled to the positive input terminal of the over 40

generator 230. The pulse generator 230 comprises a constant current-source 232, a transistor 231, a capacitor 235 and an

NOR gate 236 to produces the pulse signal SP in response to

the falling edge of the oscillation signal IPS. The gate of the transistor 231 is coupled to receive the oscillation signal IPS.

45

The oscillation signal IPS is used to control the transistor 231. The source of the transistor 231 is coupled to the ground. The constant current-source 232 is coupled betWeen the drain of

the transistor 231 and the supply voltage VCC. The capacitor 235 is coupled from the drain of the transistor 231 to the

50

ground. The input terminals of the NOR gate 236 are coupled to the capacitor 235 and the oscillation signal IPS respec tively. The pulse signal SP is generated at the output terminal of the NOR gate 236. The constant current-source 232 is used

to charge the capacitor 235 When the transistor 231 is turned off in response to the falling edge of the oscillation signal IPS.

55

235. The current of the constant current-source 232 and the

capacitance of the capacitor 235 determine the pulse Width of

threshold voltages V1 and V2 respectively (shoWn in the FIG. 5). The ?rst timing signal Sl includes the ?rst period T1. The timing signal S2 has the second period T2. The detection circuit 210 samples the current signal V, during the ?rst period Tl generates the ?rst signal (shoWn in the FIG. 7).

voltage comparator 320. The negative input terminal of the over-voltage comparator 320 is coupled to receive the input voltage signal VV. The over-voltage comparator 320 is used to detect the over-voltage of the input-voltage signal VV. The over-voltage comparator 320 generates an over-voltage sig nal When the input-voltage signal VV is higher than the over voltage threshold VTH. The under-voltage threshold VT, is coupled to the negative input terminal of the under-voltage comparator 325. The positive input terminal of the under voltage comparator 325 is coupled to receive the input-volt age signal VV. The under-voltage comparator 325 is used to detect the under-voltage of the input-voltage signal VV. The under-voltage comparator 325 generates an under-voltage signal When the input-voltage signal VV is loWer than the under-voltage threshold VTL. Input terminals of an AND gate 360 are connected to the output terminals of the comparators 320 and 325. The output terminal of the AND gate 360 gen

erates the control signal ENB through a delay circuit 370. The delay circuit 370 provides a time delay for the disable of the control signal ENB When the over-voltage or the under-volt

The pulse signal SP is enabled during charging the capacitor the pulse signal SP. FIG. 9 shoWs signal-Waveforms. The oscillation circuit 100 generates the timing signals S 1 and S2 in accordance With

?ers 330 and 340.

age of the input-voltage signal VVis occurred. 60

The operational ampli?er 330 serves as a current-limit

adjustment circuit for adjusting a current limit of the trans

65

former 30 (shoWn in the FIG. 2) in response to the input voltage signal VV. It is also adjusting the current limit of the poWer transistor 20 (shoWn in the FIG. 2). The operational ampli?er 330 produces the current-limit signal VM to disable

the sWitching signal SWfor limiting the sWitching current 1,, (shoWn in the FIG. 2) The operational ampli?er 340 serves as

US RE42,674 E 7

8

a signal adjustment circuit and generates the blanking adjust ment signal VB for adjusting the blanking time of the sWitch ing signal SWin response to the input-voltage signal VV. The

increase of the input-voltage signal VV. The blanking adjust

rent signal during a ?rst period When the poWer transistor is turned on, a second signal is generated by the detection circuit sampling the current signal during a second period When the poWer transistor is turned on, the slope of the current signal is determined in accordance With the ?rst signal and the second

ment signal VB is increased in response to the decrease of the

signal.

current-limit signal VM is decreased in response to the

input-voltage signal VV.

4. The control circuit as claimed in claim 1, Wherein the

FIG. 11 shoWs a circuit schematic of the blanking circuit 80. The blanking circuit 80 comprises a constant current source 85, a transistor 82, a capacitor 83, a comparator 87, an inverter 81 and an NAND gate 89 to produce the blanking

detection circuit comprises: a ?rst capacitor coupled to sample-and-hold the current signal through a ?rst sWitch during a ?rst period after the poWer transistor is turned on;

signal SK in response to the rising edge of the sWitching signal SW. The constant current-source 85 is coupled from the sup ply voltage VCC to the drain of the transistor 82. The gate and

a second capacitor coupled to sample-and-hold the current signal through a second sWitch during a second period after the poWer transistor is turned on; and

the source of the transistor 82 are coupled to the output

a third capacitor coupled to sample-and-hold the differen tial voltage of the ?rst capacitor and the second capacitor

terminal of the inverter 81 and the ground respectively. The capacitor 83 is coupled betWeen the drain of the transistor 82

for generating the slope signal.

and the ground. The sWitching signal SW is coupled to the input terminal of the inverter 81 to control the transistor 82 through the inverter 81. Therefore the constant current source 85 Will start to charge the capacitor 83 once the sWitching

signal SWis turned on. The capacitor 83 is connected to the negative input termi nal of the comparator 87 to compare With the blanking adjust ment signal VB coupled to the positive input terminal of the comparator 87. The output terminal of the comparator 87 is

5. The control circuit as claimed in claim 4, Wherein the 20

sample signal and the second sample signal are generated by an oscillation circuit of the poWer converter. 25

lation signal. 7. The control circuit as claimed in claim 1, Wherein the 30

8. The control circuit as claimed in claim 1, Wherein the

protection circuit comprises:

time of the blanking signal SK is therefore increased in 35

It Will be apparent to those skilled in the art that various modi?cations and variations can be made to the structure of

the present invention Without departing from the scope or spirit of the invention. In vieW of the foregoing, it is intended that the present invention covers modi?cations and variations of this invention provided they fall Within the scope of the

higher than the over-voltage threshold; 40

protection circuit comprises: 45

a poWer transistor coupled to a transformer for sWitching

the transformer;

10. The control circuit as claimed in claim 1, Wherein the 50

protection circuit comprises: a current-limit adjustment circuit coupled to receive the input-voltage signal to generate a current limit signal to

controlling the poWer transistor and regulating the out put of the poWer converter;

disable the sWitching signal for limiting the sWitching

a detection circuit coupled to sense the current signal for 55

current of the poWer converter; Wherein the current limit signal is decreased in response to

the increase of the input voltage of the poWer converter. 11. The control circuit as claimed in claim 1, Wherein the

protection circuit comprises: a signal adjustment circuit coupled to receive the input 60

Wherein the input-voltage signal is [corrected] correlated to the input voltage of the poWer converter. 2. the control circuit as claimed in claim 1, Wherein the slope of the current signal is detected When the poWer tran sistor is turned on. 65 3. The control circuit as claimed in claim 1, Wherein a ?rst

signal is generated by the detection circuit sampling the cur

an under-voltage comparator coupled to receive the input voltage signal and an under-voltage threshold to gener ate an under-voltage signal When the input-voltage sig nal is loWer than the under-voltage threshold; Wherein the under-voltage signal is coupled to disable the

sWitching signal.

a current sense circuit generating a current signal in

generating a slope signal in accordance With a slope of the current signal; a signal generator generating an input-voltage signal in accordance With the slope signal; and a protection circuit coupled to control the sWitching signal in response to the input-voltage signal;

sWitching signal. 9. The control circuit as claimed in claim 1, Wherein the

What is claimed is: 1. A control circuit of a poWer converter including an input

response to a sWitching current of the transformer; a sWitching circuit coupled to receive the current signal and a feedback signal to generate a sWitching signal for

an over-voltage comparator coupled to receive the input voltage signal and an over-voltage threshold to generate an over-voltage signal When the input-voltage signal is

Wherein the over-voltage signal is coupled to disable the

folloWing claims and their equivalents.

voltage detection, comprising:

signal generator comprises: an operational ampli?er coupled to amplify the slope sig nal for generating the input-voltage signal.

83 and level of the blanking adjustment signal VB determine the blanking time of the blanking signal SK. The blanking response to the decrease of the input voltage VIN.

6. The control circuit as claimed in claim 5, Wherein the oscillation circuit further generates an oscillation signal

coupled to enable the poWer transistor, the ?rst sample signal and the second sample signal are synchroniZed With the oscil

connected to the input terminal of the NAND gate 89 . Another

input terminal of the NAND gate 89 is connected to the sWitching signal S W. The blanking signal SK is thus generated at the output terminal of the NAND gate 89. The current of the constant current-source 85, the capacitance of the capacitor

?rst sWitch is controlled by a ?rst sample signal, the second sWitch is controlled by a second sample signal, the ?rst

voltage signal to generate a blanking adjustment signal for adjusting a blanking time of the sWitching signal; Wherein the blanking time is increased in response to the decrease of the input voltage of the poWer converter. 12. A control circuit of a poWer converter including an

input voltage detection, comprising: a poWer transistor coupled to a transformer for sWitching

the transformer;

US RE42,674 E 9

10 20. A control circuit of a poWer converter, comprising: a sWitching circuit generating a sWitching signal for con

a current sense circuit generating a current signal in

response to a sWitching current of the transformer; a sWitching circuit coupled to receive the current signal and a feedback signal to generate a sWitching signal for controlling the poWer transistor and regulating the out put of the poWer converter;

trolling a poWer transistor and regulating the output of the poWer converter in response to a sWitching current

and a feedback signal; a detection circuit coupled to sense the sWitching current

for generating a slope signal; and a protection circuit coupled to control the sWitching signal in response to the slope signal; Wherein the slope signal is [corrected] correlated to an input voltage of the poWer converter.

a detection circuit coupled to sense the current signal for

generating a slope signal; and a protection circuit coupled to control the sWitching signal in response to the slope signal; Wherein the level of the slope signal is [corrected] corre lated to the input voltage of the poWer converter.

21. The control circuit as claimed in claim 20, Wherein the

slope signal is correlated to a slope of the sWitching current.

13. The control circuit as claimed in claim 12, Wherein the

22. The control circuit as claimed in claim 20, Wherein a

slope signal is correlated to a slope of the sWitching current.

?rst signal is generated by the detection circuit sampling the

14. The control circuit as claimed in claim 12, Wherein a

sWitching current during a ?rst period When the poWer tran sistor is turned on, a second signal is generated by the detec tion circuit sampling the sWitching current during a second period When the poWer transistor is turned on, the slope signal is generated in accordance With the ?rst signal and the second

?rst signal is generated by the detection circuit sampling the current signal during a ?rst period When the poWer transistor is turned on, a second signal is generated by the detection circuit sampling the current signal during a second period When the poWer transistor is turned on, the slope signal is generated in accordance With the ?rst signal and the second

20

signal. 23. The control circuit as claimed in claim 20, Wherein the

signal.

detection circuit comprises: a ?rst capacitor coupled to sample-and-hold the sWitching

15. The control circuit as claimed in claim 12, Wherein the

detection circuit comprises:

25

a ?rst capacitor coupled to sample-and-hold the current signal through a ?rst sWitch during a ?rst period after the poWer transistor is turned on;

a second capacitor coupled to sample-and-hold the current signal through a second sWitch during a second period

30

after the poWer transistor is turned on; and

Wherein the slope signal is correlated to a slope of the sWitching current.

for generating the slope signal; 35

16. The control circuit as claimed in claim 12, Wherein the

a current-limit adjustment circuit adjusting a current limit

of the poWer transistor in response to the slope signal. 25. The control circuit as claimed in claim 24, Wherein the 40

voltage threshold; Wherein the over-voltage signal is coupled to disable the

sWitching signal. 17. The control circuit as claimed in claim 12, Wherein the

45

protection circuit comprises:

50

sWitching signal.

sWitching signal. 27. The control circuit as claimed in claim 20, Wherein the

protection circuit comprises:

protection circuit comprises: 55

signal to disable the sWitching signal for limiting the sWitching current of the poWer converter in response to

the slope signal;

under-voltage threshold; 60

sWitching signal. 28. The control circuit as claimed in claim 20, Wherein the

protection circuit comprises:

a signal adjustment circuit generating a blanking adjust

a signal adjustment circuit generating a blanking adjust

ment signal for adjusting a blanking time of the sWitch Wherein the blanking time is increased in response to the decrease of the input voltage of the poWer converter.

an under-voltage comparator generating an under-voltage signal in response to the slope signal and an under voltage threshold When the slope signal is loWer than the

Wherein the under-voltage signal is coupled to disable the

protection circuit comprises: ing signal in response to the slope signal;

voltage threshold; Wherein the over-voltage signal is coupled to disable the

18. The control circuit as claimed in claim 12, Wherein the

Wherein the current limit signal is decreased in response to the increase of the input voltage of the poWer converter. 19. The control circuit as claimed in claim 12, Wherein the

the poWer converter. 26. The control circuit as claimed in claim 20, Wherein the

an over-voltage comparator generating an over-voltage signal in response to the slope signal and an over-voltage threshold When the slope signal is higher than the over

Wherein the under-voltage signal is coupled to disable the

a current-limit adjustment circuit generating a current limit

current-limit adjustment circuit generates a current limit sig nal to disable the sWitching signal for the current limit in response to the slope signal, the current limit signal is decreased in response to the increase of the input voltage of

protection circuit comprises:

an under-voltage comparator generating an under-voltage signal in response to the slope signal and an under voltage threshold When the slope signal is loWer than the

under-voltage threshold;

24. The control circuit as claimed in claim 20, Wherein the

protection circuit comprises:

protection circuit comprises: an over-voltage comparator generating an over-voltage signal in response to the slope signal and an over-voltage threshold When the slope signal is higher than the over

a second capacitor coupled to sample-and-hold the sWitch ing current through a second sWitch during a second period after the poWer transistor is turned on; and a third capacitor coupled to sample-and-hold the differen tial voltage of the ?rst capacitor and the second capacitor

for generating the slope signal;

a third capacitor coupled to sample-and-hold the differen tial voltage of the ?rst capacitor and the second capacitor Wherein the slope signal is correlated to a slope of the current signal.

current through a ?rst sWitch during a ?rst period after the poWer transistor is turned on;

ment signal for adjusting a blanking time of the sWitch 65

ing signal in response to the slope signal; Wherein the blanking time is increased in response to the decrease of the input voltage of the poWer converter.

US RE42,674 E 11

12 generating an over-voltage signal to disable the sWitching signal in response to the slope signal and an over-voltage threshold When the slope signal is higher than the over

29. A control method of a power converter, comprising: generating a switching signal for controlling a poWer tran sistor in response to a sWitching current; sensing a slope of the sWitching current for generating a

slope signal [corrected] correlated to an input voltage of

voltage threshold. 5

the poWer converter; and

step of controlling the sWitching signal comprises:

controlling the sWitching signal in response to the slope

generating an under-voltage signal to disable the sWitching signal in response to the slope signal and an under voltage threshold When the slope signal is loWer than the

signal. 30. The control method as claimed in claim 29, Wherein

generating a sWitching signal further comprises for regulating

under-voltage threshold.

the output of the poWer converter in response to a feedback

34. The control method as claimed in claim 29, Wherein the

signal.

step of controlling the sWitching signal comprises:

31. The control method as claimed in claim 29, Wherein the

generating a blanking adjustment signal for adjusting a blanking time of the sWitching signal in response to the

step of sensing a slope of the sWitching current for generating

a slope signal comprises:

slope signal.

generating a ?rst signal in response to the sWitching current during a ?rst period When the poWer transistor is turned

35. The control method as claimed in claim 34, Wherein the blanking time is increased in response to the decrease of the

on;

input voltage of the poWer converter.

generating a second signal in response to the sWitching current during a second period When the poWer transistor is turned on; and

generating the slope signal correlated to the slope of the sWitching current in accordance With the ?rst signal and the second signal. 32. The control method as claimed in claim 29, Wherein the

step of controlling the sWitching signal comprises:

33. The control method as claimed in claim 29, Wherein the

36. The control method as claimed in claim 29, Wherein the 20

step of controlling the sWitching signal comprises: adjusting a current limit of the poWer transistor in response

to the slope signal.

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