Yield Monitor for Embedded-SiGe Process Optimization Xu Ouyang, Shwu-Jen Jeng, Ishtiaq Ahsan, Andrew Waite*, Karl Barth, Hasan M. Nayfeh, Yunyu Wang IBM Semiconductor Research and Development Center, Hopewell Junction, NY 12533, USA *Advanced Micro Devices, Inc., Hopewell Junction, NY 12533, USA Phone: (845) 892 8366 Email: [email protected]

Abstract If not yield optimized, embedded SiGe (eSiGe) processes with aggressive transistor performance enhancements could induce high SRAM standby current and single cell failures in SRAM. In order to optimize the yield of eSiGe process, a SRAM-layout-based test structure was identified. It has the advantage of being able to be tested after silicidation or first metal level, therefore can be used as an early monitor of yield degradation due to eSiGe and therefore an effective vehicle for optimization between yield and performance. Using this monitoring structure, an eSiGe process optimized for yield was developed which does not show additional yield loss due to eSiGe while retaining comparable performance enhancements.

2. Optimization of eSiGe performance and yield

process

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Obviously there are many factors in the eSiGe process that can be tuned to improve transistor performance. For example, if the eSiGe is located closer to the pFET channel by tuning the disposable spacer thickness or cavity-etch recipe, improved performance is expected because of the increased stress level due to close proximity of eSiGe. Table 1 lists some examples of the various such experiments that are expected to improve the performance. On the other hand, the impact of such process factors on circuit yield is less clear, however their yield impact should certainly be taken into consideration during eSiGe process development so that these process factors can be carefully optimized for both performance and yield.

1. Instruction As CMOS technology continues to scale, various mobility enhancement techniques are needed in order to meet the performance requirements at advanced technology node. Embedded-SiGe (eSiGe, Fig. 1) in the source/drain areas creates longitudinal compressive stress and improves hole mobility, thus has been reported as a key enablement technology at high performance 65nm node and 45nm node [1-2]. However, previous papers predominantly discussed the performance aspect of the eSiGe process. This paper will try to address the yield issues of eSiGe process by discussing the trade-off between performance and yield and present a yield monitoring structure that successfully tracks with SRAM yield.

Figure 1. Illustration of embedded-SiGe process

Table 1. eSiGe process experiments designed for optimization of performance and yield

Fig. 2 shows an example of how such the eSiGe processes affect SRAM yield and standby current. In this study, several experiments were designed to have different degrees of performance improvements, with 2 wafers per experiment. Note that the 5 experiments are ordered by their performance enhancements. It was found that wafers with smallest performance enhancement (process 1) have comparable yield and SRAM standby current when compared to the reference wafers, while wafers with more performance enhancements have incrementally lower yield and higher SRAM standby current. The increased failures in these wafers show up as single cell failures in SRAM fail bit maps, confirming that the failures are related to pFETs in

the SRAM cells. This example illustrates how important it is to take yield loss into consideration during eSiGe process development and optimization. However there are significant challenges in carrying out all these possible experiments listed in table 1: assuming only 3 conditions to explore for each of the 4 process factors listed, the number of possible combinations of experiments is 34=81. In reality, there are even more process factors and conditions that need to be considered.

Example of eSiGe process impact on SRAM

Figure 3. SRAM-layout based eSiGe monitor to detect yield loss due to eSiGe

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1.2 SRAM standby current

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Figure 2. Example of an experiment showing eSiGe process has significant impact on SRAM standby current and yield. Process 1-5 are ordered in their performance enhancements.

The structure shown is based on actual SRAM layout in both poly and active levels to mimic actual SRAM impact, and is designed to measure poly-poly leakage current. The test structure has different variants with different gate oxide thicknesses. The leakage current of the structure with thicker gate oxide is found to correlate well with final SRAM yield in multiple lots and experiments (Fig. 4-5), and therefore can be used as the early yield monitor for eSiGe optimization. This has the significant advantage of not only shortening learning cycle, but also saving expensive wafer and processing resources so that more eSiGe optimization experiments can be performed.

Split response of eSiGe monitor

3. Yield Monitoring Structures

eSiGe monitor w afer yield 1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 1.00E-11 Process5

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eSiGe monitor leakage (A)

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eSiGe monitor leakage (w afer median)

As there are many possible experiments that can be performed, it is important to have effective monitoring structures early in the process flow to detect the yield loss due to the eSiGe process instead of waiting for the wafers to travel through all the process steps to reach SRAM test. Fig. 3 depicts the layout of such an in-line monitoring structure.

eSiGe experiment

Figure 4. Split response of eSiGe monitor is very similar to split response of SRAM (shown in Fig. 2)

Figure 5. Strong correlation between SRAM yield and eSiGe monitor leakage current across all lots.

To further understand the failing mechanism, a failed eSiGe monitor was electrically probed in our failure analysis laboratory and non-linear “tunnel-like” IV

Figure 7. TIVA Image using 1340 nm laser showing thermal mapping of fail region in failed eSiGe monitor.

characteristics was observed, indicating non-ohmic shorts (Fig. 6).

Figure 6. Bench probing of failed eSiGe monitor shows non-linear “tunnel-like” IV characteristics. To localize the exact failing location within the monitor, laser stimulation techniques including TIVA and LIVA analyses were performed, and it shows that the failure/leakage is confined to a local region within the test structure (Fig. 7-8).

Figure 8. LIVA Image using 1064 nm laser showing fail region where electron-hole pairs leaking through gate oxide. Further cross-sectional TEM analysis within the failing region found that the leakage was caused by aggressive eSiGe undercut under poly (Fig. 9). Such leakage could not be detected by regular transistor gate leakage measurements because of the typical thin gate oxide used and the very few transistors measured, nor can it be detected by regular inline top-down inspections.

Figure 9: Cross-section TEM of the eSiGe monitor shows eSiGe is closer to gate in the failed site compared to the passing site.

Using this eSiGe monitor, a lot more eSiGe optimization experiments were able to be carried out in a timely manner, and eventually a yield-optimized eSiGe process was developed which does not show any additional yield loss due to eSiGe while retaining comparable performance enhancements.

4. Conclusions This paper shows that it is very important to optimize the eSiGe process with consideration of both performance and yield. An early yield monitoring structure based on actual SRAM layout was presented. It was shown that the leakage current measured with the monitoring structure correlates very well with final SRAM yield. The use of such structures significantly shortened the learning cycle and helped eSiGe process optimization. Acknowledgments This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities. References [1] W-H Lee et al., International Electron Devices Meeting, p. 4 (2005). [2] S. Narasimha et al., International Electron Devices Meeting, p. 1 (2006).