VIT UNIVERSITY SCHOOL OF ELECTRONICS ENGINEERING EEE588 DIGITAL IC DESIGN Home work Assignment- 1 Faculty In-charge: Prof.Sivanantham.S Assignment Date: 09.08.2011

Due Date: 16.08.2011

Note: If any parameter is not given in the problem, you can take the values from the model file given in the Appendix-I MOS Transistor 1. The figures below represent a side-view of a MOSFET with its channel under different operating conditions. Use the figures for the following questions. The transistors are `typical’ digital MOS transistors.

a. Which of the figures above is the best representation of the channel in the schematic on the right (Choose one of (a) – (e)). Justify

b. Which of the figures above is the best representation of the channel in the schematic on the right (Choose one of (a) – (e)).Justify

c. Which of the figures above is the best representation of the channel of an NMOS transistor with VGS=2.5V, VDS=2.3V, VT = 0.7V and VSB=0V (Choose one of (a) – (e)). Justify. 2. The following figure shows NMOS and PMOS devices with drains, source, and gate

ports annotated. Determine the mode of operation (saturation, linear, or cutoff) and drain 1   

current ID for each of the biasing configurations given below. Verify with SPICE. Use the following transistor data: NMOS: k'n = 115µA/V2, VT0 = 0.43 V, λ = 0.06 V–1, PMOS: k'p = 30 µA/V2, VT0 = –0.4 V, λ = -0.1 V–1. Assume (W/L) = 1. a. NMOS: VGS = 2.5 V, VDS = 2.5 V. PMOS: VGS = –0.5 V, VDS = –1.25 V. b. NMOS: VGS = 3.3 V, VDS = 2.2 V. PMOS: VGS = –2.5 V, VDS = –1.8 V. c. NMOS: VGS = 0.6 V, VDS = 0.1 V. PMOS: VGS = –2.5 V, VDS = –0.7 V.

Fig. NMOS and PMOS device 3. (a) Consider NMOS transistor. The device is biased with VGS = 2.2V, VDS = 4 V, and VSB = 2V. Compute the value of the aspect ratio (W/L) needed to obtain current flow of ID = 100uA. Use simplified device equation set and the parameters given below. (b) Suppose that the minimum line width in the given technology is 2.5um. Calculate the approximate gate capacitance Cg for the device designed in part (a) The parameters are: VTO = =0.8V, γ = 0.4 V1/2 , 2| φF | = 0.58 V , KP = 20 uA/V2, COX = 3.4x10 – 3pF/ (um)2

4. For the circuit given below, determine the final value of VA, VB, VC, assuming the initial condition at each of the nodes is 3V and VTP = −0.5V (ignore the body effect).

5. For VIH = 4 V, VOH = 4.5 V, VIL = 1 V, VOL = 0.3 V, and VDD = 5 V, calculate the noise margins NMH and NML. 6. Consider an NMOS transistor with the following parameters: tox = 6 nm, L = 0.24 µm, W = 0.36 µm, LD = LS = 0.625 µm, CO = 3 x 10–10 F/m2, Cjo = 2 x 10–3 F/m2, Cjswo = 2.75 x 10–10 F/m. Determine the zero-bias value of all relevant capacitances. 2   

7. Sometimes the substrate is connected to a voltage called the substrate bias to alter the threshold of the nMOS transistors. If the threshold of an nMOS is to be raised, should a positive or negative bias be used? Why?

8. A static CMOS inverter is driving a load capacitance of CL=500fF as shown in the circuit diagram below. If an ideal 5V pulse is applied at the input, determine the rise and fall times of the inverter. Assume the transistor M1 has width of 20µ and length of 1µ and transistor M2 has a length of 2µ and a width of 5µ. The supply voltage is VDD = 5V.

9. The characteristic for an n- and p-channel transistor, with the minimum dimensions W/L=0.5/0.35 and VTn = 0.4 and |VTp| = 0.5 is shown in Figure 3.1.

Fig.3.1 Characteristics of an nMOS and pMOS transistors We want to create a simple RC-model, as shown in Figure 3, were CL=50fF.

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Fig.3.2 RC model of a CMOS inverter Design the inverter with Wn=0.5 and Wp chosen to so that the inverter is balanced and calculate Ron-n and Ron-p.

10. Consider the CMOS Inverter shown in figure: (a) Calculate VOH, VOL, VM of the above inveter (b) Find VIH, VIL, NML and NMH for inverter. How can you increase the noise margins and reduce the undefined region? (c) Comment on the differences in the VTCs, robustness and regeneration of given inverter. Does the VTC tell you anything about the timing of the circuit?

11. Determine the trip-point, VIH, and VIL of the inverter under the following scenarios and comment on how device dimensions affect these key points. a) W1=0.6u, W2=1.8u. L1=0.6u, L2=0.6u b) W1=3u, W2=9u. L1=3u, L2=3u c) W1=0.6u, W2=0.6u. L1=0.6u, L2=0.6u d) W1=0.6u, W2=0.6u. L1=0.6u, L2=6u Assume µnCOX=100uA/V2, VTn=1V, VTp=-1V, µn/µp=3, γ=0 and λ=0. Note: Compute te actual value only for case (a), and show your analysis for the other three cases (i.e no need to compute the actual values). 4   

Appendix- I MOS Model Parameters

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