9th International Symposium on Quality Electronic Design

Variation Aware Spline Center and Range Modeling for Analog Circuit Performance ∗ Shubhankar Basu, Balaji Kommineni and Ranga Vemuri Department of ECE, University of Cincinnati Cincinnati, OH 45221, USA basusr,komminb,[email protected]

Abstract

promising, the choice of an appropriate rank can determine the accuracy of the models across different technologies. Also the choice of the rank can determine the run-time complexity of the modeling process. Therefore these techniques are not perfectly scalable with similar accuracy and run-time across different technologies. Noisy data may be represented as intervals [9] as long as they are continuous in the bounds. The use of interval data types for computation however exhibits limitations like width expansion in the results due to dependent variables. This makes them unsuitable for precision applications like analog performance macromodeling. Neto et al. proposed an alternate technique (CRM [6]) to perform regression modeling on interval valued data using the center and the range information of intervals. Use of higher dimension polynomial in non-linear multi-variate regression modeling often suffers from Runge’s Phenomenon [2]. In this work we propose a Spline Center and Range Method based regression technique to capture the non-linearity of the multi-variate design space. SCRM employs Duchon pseudo-cubic spline interpolation technique to find exact solutions between non-linear points while preserving the center and range transformation of interval valued data as presented in [6]. Unlike the existing techniques, our Variation Aware Performance Macromodeling of Analog Circuits (VAPMAC) technique models the variation in performance of circuits with respect to the design variables in the presence of process varying device parameters. Also the impact of process parameters are captured accurately without any approximations. Experiments performed on the operational amplifier class of circuits demonstrate the accuracy of our proposed technique when compared with HSpice based performance measurements. The remainder of the paper is organized as follows. Section 2 illustrate the motivation behind our work. In Section 3 we present the theory and algorithm used in VAPMAC. Section 4 describes the experiments performed and results obtained. Finally, Section 5 presents the conclusions and future work.

With scaling technologies, process variations have increased significantly. This has led to deviations in analog performance from their expected values. Performance macromodeling aids in reduction of synthesis time by removing the simulation overhead. In this work, we develop a novel Spline based Center and Range Method (SCRM) for process Variation Aware Performance MACromodeling (VAPMAC) which works on interval valued data. Experiments demonstrate around 200K times computational time advantage using VAPMAC generated macromodels over SPICE montecarlo simulation. The results also demonstrate less than 10% loss in accuracy in computing the performance bounds using the macromodels compared to the spice simulations.

1. Introduction Analog design traditionally relied on designer’s knowledge and expertise. The introduction of high complexity SOC designs with aggressive time-to-market requirements made analog design automation an attractive alternative. However, conventional analog circuit synthesis requires expensive simulation-in-the-loop iterations to evaluate circuit performance. This becomes prohibitively expensive when montecarlo simulations have to be performed to capture the effects of random process variations on the device parameters such as Tox , Lef f , Wef f and Vt0 of MOS transistors. Process variations induce impedance mismatch in devices making analog circuit performances unreliable. Performance macromodels have found widespread applicability as an alternative to simulation during synthesis. Several authors [1, 4, 8] have presented techniques to generate accurate performance macromodels. The use of macromodel significantly reduces the synthesis time complexity. The above works in performance macromodeling however do not consider the impact of process variation on circuit performance. This make the models insufficient for use in variation tolerant synthesis. Therefore there is a need to develop macromodels to predict performance in the presence of process variations. In [11, 12], the authors present several variation aware performance modeling techniques. These works employ a low rank projection methodology to reduce the parameter space. This reduces the complexity of generating a model as a function of the process parameters. While these techniques are

2. Motivation To illustrate the impact of process variation on circuit performance, we use a sized SEO circuit in 180nm and subject it to variation in the device parameters as presented in [10] for 500 sample cases. Due to the impedence mismatch occuring out of such random variation in device parameters (Tox , Lef f , Wef f , Vt0 ), the performance of the opamp shows significant deviation from normal. The experiment shows that for open loop gain, around 11% of the single ended opamps fall below the specifications. Ta-

∗ This research is supported in part by the National Science Foundation under grant numbers CNS-0421092 and CCF-0429717

0-7695-3117-2/08 $25.00 © 2008 IEEE DOI 10.1109/ISQED.2008.118

162

Algorithm 1: VAPMAC procedure VAPMAC (Range for the independent widths, Process variations, Circuit topology, Modeling control file) Input: Range for the independent widths (W), Process variations file (prvar), Circuit topology (ckt), Modeling control file (cfg) Output: Final performance macromodel X0 = null, Y0 = null Ext Samp(Nos. of External quasi-random samples) Int Samp(Nos. of Internal pseudo-random samples) /* EDGE: Experimental data generation */ for i ← 0 to ExtSamp do wi = Halton(w) [params] = [wi ], [Vth ], [tox ], [lef f ] for i ← 0 to IntSamp do paramj = uniform(wij , vthj , toxj , lef fj ) spicefile = ckt top + paramj endfor /* SPA: Simplified Performance Analysis */ sim data = HSPICE(spicefile) pr metrics = f(sim data, cfg) Xi = Xi−1 ∪ Wij Yi = Yi−1 ∪ pr metrics endfor X = Xi , Y = Yi /* PMG: Performance model generation */ [Y ] = Interval transform (y) [Yc , Yr ] = CR transform ([Y ]) /* SCRM: Spline based Center and Range Method */ βc = Duchon spline(X, Yc ) βr = Duchon spline(X, Yr ) Macromodel = {βc , βr } [a] = (al , au )

Table 1. SEO Performance in 180nm Parameter Synth. Variation Gain 50.55db [40.78, 57.95] BW 6.29e5 Hz [2.25e5, 23.2e5] UGF 2.0e8 Hz [1.27e8, 8.3e8] PM 67.98 Deg [19.15, 74.31]

Table 2. SEO Performance in 65nm Parameter Nominal Variation Gain 52.06db [-7.63, 63.6] BW 2.22e7 Hz [5.11e6,4.76e9] UGF 6.94e9 Hz [1.24e8, 1.18e10] PM 55.69 Deg [-2.15, 100.396] ble.1 presents the variation in the different performance parameters (open-loop gain (Gain), 3dB bandwidth (BW), phase margin (PM) and unity-gain frequency (UGF)) for the synthesized SEO due to process variations. In Table. 2, the results demonstrate how the performance degrades even further (around 70%) due to process variation on the SEO circuit’s nominal performance due to the scaling of technologies to 65nm. The above situation prompts the need for the development of accurate macromodels that computes the bounds on performance parameters under the effect of such variations. The modeling technique should also be scalable across different technologies. In the next section we present our automated methodology which can generate accurate mismatch aware performance macromodels.

3. VAPMAC Variation Aware Performance Macromodeling for Analog Circuits (VAPMAC), proposed in this work, employs a novel Spline based Center and Range regression Method (SCRM) which works on interval-valued data. This automated methodology generates the performance of the circuit as an interval value with lower and upper bounds representing the worst case and best case performance measures. The automated SCRM based macromodeling technique can be classified into three major steps: Training Data Generation, macromodel Generation and Model Verification. Fig. 1 presents the block diagrams, highlighting the major steps in the flow. In Algorithm.1, we present the pseudo-code developed for VAPMAC. The following sub-sections would elaborate on the essential steps presented in this work.

3.1

Training Data Generation

The accuracy of any statistical modeling process is dependent on the training data. However, high dimensionality of modeling problems make the choice of sampling technique and optimum number of samples, difficult to estimate. In high dimensional design space, the problem of sparse data samples is an active area of research [7].

3.1.1 Sampling Since spline is used as a regression technique in our work, the essence of sampling can be well described in the context of a spline

163

model. It is well established that a spline model for a system is accurate, if the removal or addition of a single design point does not significantly alter the model. This therefore emphasizes the coverage of the entire design space during sampling. Pseudo-random samples are produced using a random number generator which are based on an initial seed. With no-prior assumption on the nature of the function, pseudo-random number sequences are capable of filling up the entire design space. While this is an effective technique, they come at the cost of relative non-uniformity in the sampled points. Pseudo-random sampling has the inherent weakness of clustered data points, leaving intermediate gaps in the sample space. Regression techniques often require the computation of matrix inversion which can lead to errors due to extremely close sample values for the model variables. Quasi-random sampling produces a more uniform distribution over the entire design space. Quasi-random number generators do not make use of a seed unlike pseudo-random generators. With sufficiently high sequence for sampling, they cover the design space uniformly. In this work we use a combination of quasi-random sampling and pseudo-random sampling. The quasi-random sampling technique is used for the design variables, which form the independent model variables. The pseudo-random sampling is used to capture the variation in transistor model parameters, which lead to varying performance values.

Figure 1. a) Training Data Generation b) Macromodel Generation c) Verification

3.1.2 EDGE and SPA

the random values of the widths based on the nominal width selected is sampled using upto IntSamp iterations of pseudo-random generator. In this work we use 400 samples points through a montecarlo simulation. The culmination of the EDGE process is the generation of the experimental data which is required by SPA to evaluate the performance functions using HSPICE simulation. Simplified Performance Analyzer (SPA), is the next stage in the model data generation process. SPA is a parameterized program, which contain the definition of the performance functions to be evaluated. The input and output of the SPA can be classified as follows:

Fig. 1(a) shows the flow to generate the scalar data for samples and performance measurements. The entire method is implemented in C++ and uses HSP ICE ! in the loop. The main parts in the flow are classified as Experimental Data Generation (EDGE), Simplified Performance Analyzer (SPA) and Model Data Preparation Process. The function (EDGE) is to sample the design space based on user defined parameters. The inputs and output from EDGE can be classified as follows: • Input:

• Input: – Design Variables (Nominal Widths of Transistors) – Variable Range

– Circuit topology (Spice Netlist)

– Technology Parameter Correlation Model

– Design and process parameter samples

– Process Variation (Distributions)

• Output:

• Output:

– Performance data

– Sampled Design and Process Parameter space

HSP ICE ! is used to perform DC and AC analysis on the circuits to evaluate the performance parameters which are the dependent variables for our regression modeling problem. The last step in the training data generation process is the model data preparation. This is a raw data preparation process which creates a matrix with the values of the design variables (nominal values of widths, X) together with the corresponding performance metric (Y). The output from the training data generation process is the Scalar Valued Data, which forms the input to the macromodel generation process.

In our work, we consider the transistor parameters as Lef f , Tox , Wef f and Vt0 . For this work the nominal channel length for each transistor is kept at the minimum value and is not considered as an external design variable. The tolerance bounds are represented as, for example [toxl , toxu ] with percentage variation from the nominal values chosen from the literature [10] for 0.18µ technology. The sampling process comprises of two loops. The outer loop, is the process to generate the independent set of widths of the transistors within the range (design constraints) for upto ExtSamp number of samples. This is generated using Halton quasi-random sequence generator, which samples the design space uniformly. Thus each such set of nominal widths is a point in the Euclidian space Rd , where ’d’ implies the dimension of the modeling problem. It is often observed that the worst cases under process varying conditions are a combination of intermediate points. This motivates our choice of quasi-random sampling over other techniques such as Latin Hypercubes. It has been experimentally observed that 2000 data samples provide desired accuracy in modeling for the size of circuits involving upto 33 transistors. In the inner loop, the set of random values of the process parameters, together with

3.2

Macromodel Generation

In this work, we present a novel spline based Center and Range regression Method (SCRM) which is used to generate variation aware performance macromodels for analog circuits. SCRM works on center and range transformed data from an initially interval data set. The main advantage of the use of interval data type is to group the scalar data into meaningful 3σ ’min’/’max’ data which are continuous in the interval. If the intervals faithfully describe the behavior of a system, then it can provide a multi-fold advantage in computation time over a numerical system operating on scalar

164

valued data. This specific advantage is exploited in this work with an objective to substitute for the costly montecarlo simulation-inthe-loop evaluation during circuit synthesis. Fig. 1(b), presents the flow to transform the scalar data and perform the regression modeling.

them as: Zi φ

[Xl , Xu ]

Y Output : Xc Xr Yc Yr

= = = = =

[Yl , Yu ] (Xl + Xu )/2 (Xu − Xl ) (Yl + Yu )/2 (Yu − Yl )

(1) (2) (3) (4) (5) (6)

zic zir

λa |t − a|

+ p(t)

(9)

=

k X

Wjc φ(xci − xcj ) + P m (xci )

(10)

=

k X

Wjr φ(xri − xrj ) + P m (xri )

(11)

where the model coefficients (for basis function and polynomials) are obtained by using Duchon pseudo-cubic spline regression [5].

3.3

The design space for analog performance function is highly non-linear and unstructured. This makes common techniques like linear regression with one or higher order polynomials an inaccurate technique. Spline is found to be the best method in fitting extremely non-linear data, which solves a set of linear equations generating perfect models. However due to the limitations of generating gridded samples, tensor product splines cannot be used for modeling multi-dimensional performance functions [3, 4]. Duchon [5] developed a few alternatives to tensor product splines that work well on unstructured data. Pseudo-polynomial splines are one such class and can work effectively for high dimensional regression modeling on unstructured data. As described by Duchon, for a n-dimensional space, considering a finite space A ⊂ Rn containing Pm−1 unisolvent subsets, there exists one function of the form: σ(t) =

= 'x'32

j=1

3.2.2 Duchon pseudo-cubic spline regression

2m−1

(8)

j=1

With the CR transformed data sets, the task is to find the model coefficients that leads to the least error measured as the root mean squared error (RMSE) or the highest square of the correlation coefficient (r 2 ) between the modeled and actual performance values.

X

Wj φ(xi − xj ) + P m (xi )

The height (zi ) of the N-dimensional point to interpolate (xi ) is a weighted (Wj ) summation of basis functions (φ) applied to the difference between the unknown point and all ’k’ number of sampled nearest neighbor points (xj ) currently defining the spline, plus a polynomial of degree m = 1. The basis function is the Euclidean norm cubed, i.e. the cubed distance between the points xi and xj . Given a set of sample points, it is possible to uniquely solve for the basis function coefficients and the first order polynomial coefficients by solving a set of linear equations. This is well supported by M AT LAB ! and is solved within a much reduced time. The coefficients together with the location of the sampled data points completely define the spline interpolate. Duchon Spline is called as a function within MATLAB as a part of model generation using SCRM. Mathematically, the two SCRM regression models are expressed by Equation. (10) and Equation. (11).

Having obtained the scalar valued raw data set from the training data generation step, the first task is to transform the data into the corresponding interval valued data. This is done by clustering the data set obtained for each ExtSamp sample (combination of design variables) into one experiment and observing the ’minimum’ and ’maximum’ value obtained for the performance variable due to the varying process parameter values as supplied during IntSamp. The interval valued data is transformed into their corresponding ’center’ and ’range’ values as a secondary step to prepare data for spline center and range regression. The transformation is obtained using the upper and lower bound of the intervals, as follows:

=

k X j=1

3.2.1 Interval Data and Center and Range Transformation

Input : X

=

(7)

a∈A

Model Verification

Spice has been the defacto standard to measure accuracy of circuit function evaluation. In our work we therefore measure the accuracy of the SCRM based performance macromodels with the corresponding evaluation by HSPICE circuit simulator. Figure 1(c) shows our verification strategy for the performance macromodels. We employ a randomly generated test data set (set of nominal transistor widths) to compare the resulting performance results. The random test data set is generated using a pseudorandom generator. The montecarlo simulation based results are evaluated using C++ and HSPICE simulator. The lower and upper bounds of the performance function ’Y’ (Ylower , Yupper ) are found by a ’min’/’max’ sampling of the function. While the SCRM based results are evaluated using the macromodels. It may be noted that the models cr values from which the lower and upper generate the Ybc and Y bounds of the performance function are computed as: Yblower Ybupper

cr /2 = Ybc − Y b cr /2 = Yc + Y

(12) (13)

The goodness-of-fit is evaluated as an average percentage error for the lower and upper bounds computed for SCRM and montecarlo simulation for ’n’ validation test cases, i.e.

where p ∈ Pm−1 and λa q(a) = 0, ∀q ∈ Pm−1 When m=2, we obtain the pseudo-cubic spline, and we express

165

1 r2l

Erru

= =

Pn

− Ybloweri )/Yloweri ) ∗ 100) n Pn b (((Y − Y upperi upperi )/Yupperi ) ∗ 100) i=1 n (14) i=1 (((Yloweri

0.9 0.85 Correlation Coefficient

Errl

r2u

0.95

0.8 0.75 0.7 0.65 0.6

4. Experimental Results

0.55 0.5 500

With the objective to measure the accuracy of the performance macromodeling technique using VAPMAC, we select benchmark circuits as presented in [1] with the same performance specifications. We select the operational amplifier class of circuits, which is one of the most common building blocks in analog systems, for our experiments and measure a set of their performance parameters. Simulations are performed using Synopsys HSP ICE for Windows as the circuit simulator. For this work, all transistors are considered to be MOS transistors using 0.18µ TSMC and 65nm PTM device models. For the purpose of the experiments, the authors consider the process parameters (Tox , Lef f , Wef f and Vt0 ) to be perfectly random and distributed normally. This is done to consider an extreme range of variation in the performance. The 3-sigma variation of the process parameters are chosen from [10] for 0.18µ technology. Simulations are run on Windows PC with Intel! CORE T M 2 Duo processor. Alike any other regression modeling techniques, the accuracy of the macromodels improve with the increase in the number of samples. However the number of samples also increase the time complexity of the modeling process. While, we do not intend to minimze the simulation time, we try to improve the modeling time and accuracy of the macromodels. Fig. 2 plots the modeling time required by SCRR based on the number of samples. Fig. 3 compares the accuracy of the macromodel generation using the statistical correlation coefficient metric for different number of samples.

2000 Number of Samples

3000

(a) Accuracy Figure 3. Accuracy Comparison We present the comparison of VAPMAC generated performance macromodels and HSP ICE ! and montecarlo based evaluation of the performance metrics of two operational amplifier circuits: • Two-Stage Opamp • Single-Ended Opamp Figure 4 plots the MM estimated and MC actual values of the four performance parameters for the single-ended opamp circuit using the 50 candidate width combination from the validation data set. Owing to space limitations, we present the results for the 0.18µ in this work.Table 3. presents the comparison result of the performance macromodels generated using VAPMAC ([M Ml , M Mu ]) with the bounds on the performance functions obtained using montecarlo simulation, ([M Cl M Cu ]) for the two benchmark circuits for 0.18µ technology. Results show that for the 50 independent validation data set as an input to the two systems, the macromodels provide a reliable bound within less than 10% average error of the results generated using montecarlo using HSP ICE ! . In terms of a statistical goodness-of-fit measure, we observe that all model generated results are above 90% correlated (r 2 ≥ 0.90) with the spice results. The results also show around 200K times improvement in run time due to computation of the macromodels over the expensive montecarlo simulation in the repeated synthesis loop. However, it is also observed that a one-time model generation time is approximately 5 hours using our technique to obtain the desired accuracy.

70

60 Macromodel Generation Time (Seconds)

1000

50

40

30

20

10

0 0

200

400

600

800 1000 1200 Number of Samples

1400

1600

1800

2000

5. Conclusion

Figure 2. SCRR Modeling Time Comparison In this paper we present a variation aware analog performance macromodeling (VAPMAC) technique. VAPMAC employs a novel Spline based Center and Range regression Method which works on interval valued data. These macromodels would find wide use in fast and variation-tolerant synthesis of analog circuits with minimal loss in accuracy as compared to the expensive montecarlo simulation-in-the-loop measurements. For future work, the authors intend to improve the accuracy of VAPMAC by considering adaptive sampling techniques.

The performance metrics for the experiments are generic to the class and are independent of the specific op-amp circuit topology. Some of the performance metrics measured for this work are: • Open Loop Gain (Gain) • 3dB Bandwidth (Bandwidth/BW) • Unity Gain Frequency (UGF)

6. References

• Phase Margin (PM)

166

Figure 4. Comparing the MC and MM computation of a) Gain b) BW c) UGF d) PM for single-ended opamp

Ckt.

Perf.

TSOP

Gain 3dB UGF PM Gain 3dB UGF PM

SEO

Table 3. Comparison of VAPMAC macromodel and Monte Carlo MC MM Errl Erru T imeM C [M Cl , M Cu ] [M Ml , M Mu ] [-17.5 , 10.6] [-18.0 , 11.0] 3.1% 2.0% 74min [2.28e8 , 5.7e9] [2.16e8 , 6.02e9] 4.2% 4.7% [2.23e9 , 1.18e10] [2.15e9 , 1.24e10] 5.4% 9.2% [19.2 , 84.9] [17.4 , 91] 9.5% 7.18% [-14.6 , 67.5] [-16.3 ,71.1] 6.5% 5.2% 41min [5.78e4 , 1.59e10] [5.194e4 , 1.689e10] 7.9% 8.1% [3.71e6 , 1.39e11] [3.36e6 , 1.52e11] 8.1% 9.2% [-40.3, 131.8] [-43.1, 140.2] 6.95% 6.3%

T imeM M 0.021sec

0.016sec

Symposium on Neural Networks, 2006. [7] Ping Li et al. A sketch-based sampling algorithm on sparse data. Technical report, Stanford University, Microsoft Research. [8] R. Harjani and J. Shao. Feasibility and performance region modeling of analog and digital circuits. Analog Integrated Circuits and Signal Processing, 10(1-2):23–43, December 1996. [9] Ramon E. Moore. Interval Analysis. Prentice-Hall, 1966. [10] X. Li et al. Asymptotic probability extraction for non-normal distribution of circuit. In IEEE ICCAD, 2004. [11] Xin Li; Gopalakrishnan, P.; Yang Xu; Pileggi, L.T. Robust analog/rf circuit design with projection-based posynomial modeling. In ICCAD, pages 855–862, 2004. [12] Z.Feng, G.Yu and P.Li. Reducing the complexity of vlsi performance variation modeling via parameter dimension reduction. In ISQED, pages 737–742, 2007.

[1] A. Agarwal et al. Hierarchical Performance Macromodels of Feasible Regions for Synthesis of Analog and RF Circuits. In IEEE ICCAD: 430-436, 2005. [2] B.Fornberg and J. Zuev. The runge phenomenon and spatially variable shape parameters in rbf interpolation. Technical report, University of Colorado, Dept. of Applied Mathematics. [3] C.W. Scherer et al. Robust performance analysis for parameter dependent systems using tensor product splines. In IEEE Conference on Decision & Control, 1998. [4] G. Wolfe et al. Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. In IEEE ICCAD: 931-938, 2004. [5] J. Duchon. Constructive Theory of Functions of Several Variables, Lecture Notes in Mathematics. Springer-Verlag, 1977. [6] L. Neto, F. Carvalho et al. Linear regression methods to predict interval-valued data. In IEEE Nith Brazilian

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Variation Aware Spline Center and Range Modeling for ...

Neto et al. proposed an alternate technique (CRM [6]) to per- form regression ... The automated SCRM based macromodeling technique can be classified into ...

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