Printed Pages-7

EECsOl

ollowing Paper ID and Roll No. to be filled in yourAnswer Book Roll No. B.Tech. (SEM. V) ODD SEMESIERT}IEORY EXAMINANON 2012-13

INTEGRATED CIRCUITS Time : 3 Hours

Tbtal Marks : 100 Note : Attempt all questions. All questions carry equal marks. Assume missing data suitably if any.

1.

Attempt any two parts ofthe following:

(a)

Tvyo circuits for generating constant current

Qxt0-10)

of I 0 pA from l0 V p.ower supply. Assuming all matched transistors, determine the value of resietances. T[ke V", : 0.7 v ;i 1 mA (Neglect effect of finite B).

V""=l0V

=l0pA

I.=l0pA

q (u)

Fieure l Name the two circuitiand compare their features in Figure l.

EEC50I/DLT-44160

I

as showh

{Turn Over

(b)

Draw the circuit diagram of a Wilson current source and find the expression for current transfer ratio. For the circuit shown in Figure 2 below, find current transfer ratio. I..t

Figure 2 (c)

Second stage of afypicalOP-AMP is shown in following

Figure 3, find input resistance (\r),output resistance and transconductance

ofthe stage (G*").

f.re

R12 I

EEC501/DLT44l60

(\r)

Figure 3

:

r"r?

= 2.63 K

P" = 200,

9*:

Vo:

V

125

so

2.

(2x10=20)

Attempt any two pans of the following:

(a)

For the circuit shown in Figure 4 show that common mode

gain is minimum when R, =

q

and

& = \.

Figure 4

(b)

Find differential gain of the circuit shown in Figure 5' R(i vvv

R, Rr

___N t_\ ^)

t\ l\

)-/

+

R1

l*,/

Vo

1) v,

vl

t

Figure 5 EEC50l/DLt44l60

fTurn Over

I

(c)

Compare and contrast active filters and passive filters. Draw the circuit of IId order low pass filters and find the expression for its cut-off frequency. Design a second order low pass Butterworth filter

to have cut-offfrequency I kHz.

3.

Attempt any two parts of the following

(2x10=20)

:

(a) Discuss the features of cMoS circuit. Discuss the effect of Fan-in and Fan-out on propagation delay in CMOS digital logic circuit. Find the expression of y in terms of A and B and hence the truth table for the circuit shown in Figure 6.

T:

oa I

Figure 6 (b)

Design CMOS logic circuit to realize the Boolean function

given by

:

Y=ABC+a Be EEC50l/DLr44l60

(c)

Implement,rhe following digital CMOS logic circuits

(i) (ii) 4.

S-R

flip-flop

D Latch.

Attempt any two parts of the following

(a)

:

:

(2x10=20)

Draw the circuit diagram of full wave precision rectifier and find expression for output voltage for both positive and negative half cycle of input sinusoidal waveform.

(b)

For monostable rnultivibrator circuit shown in Figure

7

the gircuit can be triggered by applying a positive input pulse of amplitude greater than Find the expression

\.

for T quasi-stable time period.

_it Trigger

Vo

(q\

<
Figure 7

I t

EEC50l/DL[44160

fTurn

Awr

i

(c) . For the circuit shgwn in Figure 8, show that outPut voltage is ProPortional to /n v' (Assuming matched transistors).

Figure 8 5.

Attempt any two parts of the following

(a)

:

(2x10=20)

What are different mode of operation of IC 555 ? Draw the circuit diagram of a delay circuit using 555' What is maximum delay that can be provided with 555 capacitor of 1000 PF ?

EECsOI/DLT44I60

*itlr,u

' (b)

PLL IC. Explain its working and deduce the expression for maximum Draw the functional block diagram of

frequency range ofsignal that can be locked.

(c)

Draw

tle circuit

diagram of weighted resistor digital to

analog converter and find the expression

of its output

analog voltage.

I I

EEC50I/DLT-44160

7

8925

t

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