TEST SCHEDULING FOR MEMORY CORES

. (DEPARTMENT OF ELECTRONICS AND ELECTRICAL COMMUNICATION ENGINEERING)

By KUNDAN KUMAR Roll Number: 05EC1019

Under the Guidance of Prof. S. Chattopadhyay

INDIAN INSTITUTE OF TECHNOLOGY

Department of Electronics and Electrical Communication Engineering Indian Institute of Technology Kharagpur, India

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Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur-721302

Certificate This is to certify that the project titled “Test Scheduling for Memory Cores” is a bonafide record of the work carried out by Kundan Kumar, Roll No. 05EC1019, under my supervision and guidance during the period Jan 2008 to April 2008 as a mini project in the Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur.

Date:

Prof. S. Chattopadhyay

Place: IIT Kharagpur

Department of Electronics and Electrical Communication Engineering

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Contents: 1. Introduction 2. March Algorithm Based test Scheduling 2.1 Memory Testing Power Dissipation 2.2 Optimal Way to Test memory Cores in Parallel 2.3 Memory Testing Timing Criteria 2.4 Results and Discussion

3. Stage-Based Test Scheduling With BISR Scheme 3.1 Theory 3.2 Scheduling Algorithm 3.3 Results and Discussion

4. Future Directions 5. Acknowledgement 5. References

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1. Introduction With the rapid progress in the VLSI fabrication process, a complex system can now be integrated into a System-on-Chip (SOC). Furthermore, with the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of memories with different sizes and frequencies. Both the number of embedded memory cores and and area occupied by memories are rapidly increasing on SOCs. The yield of on-chip memories thus determines the chip yield. Testing and diagnosis of embedded memories brings new challenges to the SOC development. Test Time and Test Power Constraint have always been major concerns for the testing of memory cores. Usually, the embedded memory cores occupy the most chip area of the SOC. Therefore, the testing of the memory cores is more complicated than the testing of the logical cores. Also, due to the limitation of the I/O pins, it is difficult to test embedded memory cores externally. The Built-In Self-Test (BIST) schemes and Built-In Self-Repair (BISR) schemes have been widely used to solve this problem. The test power constraint becomes a major concern because the power consumption of memories under test is higher than their power in normal operation mode due to the high switching activities during the testing. To reduce the switching activity, sequential testing of memories can be done, which results in a high testing time, thus increasing the test cost. Testing memory cores in parallel is essential to reduce the testing time. When a large number of memories are tested simultaneously, the total test power dissipation can exceed power constraints, thus generating excessive heat and potentially causing device damage. A straightforward solution to the power problem is to reduce the number of memories tested in parallel so that the power constraints are respected. Therefore, efficient test scheduling of memory cores plays an important role on the minimization of the overall test time under the test power limitation. It has been shown that the march algorithms are the most effective methods to detect the various memory faults. Several BIST schemes using the march algorithms have been proposed to test the memory cores. Employing BISR schemes for memory cores is also a promising way of increasing the yield of embedded chips. In this report, the following two types of scheduling have been discussed. 1. March Algorithm Based test scheduling. 2. Stage-based test scheduling with BISR scheme under power constraint.

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2. MARCH ALGORITHM BASED TEST SCHEDULING 2.1 Memory Testing Power Dissipation In memory testing, power is dissipated mainly in 1. Memory array 2. The decoders (row and column) and 3. Peripheral circuits (sense amplifiers and write drivers) Among the three, power dissipation in the memory array is the most significant due to its large capacitance and high signal activities. Power Consumption Analysis of memory Array R/W operation :

An addressable memory cell as shown in figure 1 uses both n-channel (NMOS) and p-channel (PMOS) transistors. A total of six transistors are used in the cell. These memory cells share a pair of differential bit lines (BL and BLb). A pair of bit lines carries true and complement data. A word line connected to the gates of pass transistors couples the bit lines to gates of storage transistors. Both the read write operations start with pre charged BL and BLb lines.

FIGURE 1: A typical memory cell

•

Read Operation :

WL line selects the particular row of memory cells to be selected. Once a specific memory cell is selected by the row and column decoder, the pass transistors allow the charge at the gates of the storage transistors to get discharged through the BL and BLb line consequently allowing the data to be read. Charge remains dynamically stored on the gates of the storage transistors when the pass transistors are turned off. NOTE: In order to speed up read operation and to reduce power on the bit lines, the duration of WL = 1 is often fairly small, during which the bit line discharges due to read is often less than 10% of Vdd.

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The current drawn during a read cycle is:

where m represents the number of cells on the same WL; Idc(r) is the DC current on the bit lines during read, Dt is the duration of WL=1; Cd the capacitance of a bit line, BL or BLb; DV(r) denotes the bit line voltage swing during a read; and f is an operating frequency or 1/Tc with Tc being system clock cycle time.

The first term in the above equation represents DC current drawn when WL = 1 and the second term is the current draw from Vdd for pre charging the bit lines after a read is performed. •

Write Operation :

Similarly to a read operation, once a row is selected, all the memory cells on the row are activated. However, except for the memory cells to write, all the other cells selected are essentially performing pseudo read operations, whereby data read from these cells are ignored. To write 0(1) into a cell BL line is pulled low (high) while to BLb line is set floating high (low). WL line is set high momentarily during which the data gets transmitted to the gates of the storage transistors. Now after the pass transistors are switched off, the feedback mechanism inside the transistor circuit allows the data to get sustained. During write operations both the storage transistors corresponding to BL and BLb store complementary data. This mechanism of having two bit lines provides us the necessary feedback to sustain the stored data in the circuit. NOTE: In order to reliably write memory cells at high speed, the voltage swing of the bit is usually Vdd. The current drawn on the bit lines during a write is:

Where, p is the no of cells in that particular row involved in write operations.

Since the power consumed is directly proportional to the voltage swing we observe that write operation uses 10 times more power compared to read operation for processing a word of fixed length ‘p’.

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2.2 Optimal Way to Test memory Cores in Parallel In a SoC, where there are many memories to test, multiple memories are often tested in parallel in order to minimize test time. Here, we discuss the case of memory testing using March C Algorithm which employs three different types of March elements. The type 1 March element is M0, which conducts consecutive write operations for memory initialization; the type 2 March elements consists of M1-M4, which can be described as (rd, wdb) with d being any binary number and db being its complementary; the type 3 March element is M5, which performs consecutive read operations over the entire memory space.

FIGURE 2: March Element M1 on two memories

Figure 2 illustrates the application of type 2 march element M1 of a March C algorithm used for testing two memories in parallel, where (r0, w1)i represents the test (r0, w1) is applied to address i. As shown, the read operations applied to both RAM 1 and RAM 2 are aligned in time and so are the write operations. As shown, all the memories tested in parallel always perform write operations simultaneously. Consequently, when one memory is in its peak power dissipation state, all other memories being tested are also in their peak power dissipation states. So this particular scenario may cause memory testing to fail if the combined peak powers consumed for both the memories, during write operations exceed the power budget. Power Constrained Test Scheduling So the very basic idea proposed for low power design of memory testing via BIST is to arrange read and write operations of the march elements amongst multiple memories tested in parallel such that the total peak power is less than the sum of peak powers. We must skew the application of the read and write operations to both memories so that no simultaneous write occurs. Figure 3 illustrates the skew of the read and write operations when applying M1 to the two memories.

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FIGURE 3: Low Power March Element M1 on two memories

Total peak power dissipation now reduces to P(w) +P(r) from 2*P(w). Note: implementing this methodology an additional overhead of one clock cycle will be required.

Similarly when dealing with the type 1 March element M0, there exist at least two ways to apply it to both memories. The first is to apply M0 to one memory at a time. In other words, apply M0 to memory 1 while placing memory 2 in idle. Once the first memory is initialized, M0 is then applied to memory 2 while placing memory 1 in idle. The test time overhead in this case will be n cycles. No modifications are required for type 3 march element M5 and hence no additional clock cycles. To summarize the two memory scenarios, in case of March C algorithm based memory testing for 2 cores in parallel we are able to reduce test peak power from 2*P(w) down to P(w) + P(r) at the cost of additional n+1 clock cycles.

2.3 Memory Testing Time Criterion

  The testing time of the multiple memory cores under the power constraint of SOC also is another important issue which should be highlighted.

Alternative use of the above proposed algorithm in reducing testing time for memory testing: For example, if there are 800 memories embedded in a SoC and 200 of them can be tested in parallel due to power constraint. If each memory has P(w) = 100 mW and P(r) = 60 mW, [P(w)+P(r)] /[2*P(w)] = 20% peak power reduction can be achieved for each memory, which allows another 20% or 40 more memories to be tested in parallel under the same power constraint. In this case, shorter test time for the entire SoC become possible with the low power BIST.

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March Algorithm Techniques to Reduce Memory Testing Time under Power Constraint It is now known to us that the march algorithms can obtain higher fault coverage than the non-march algorithms in the embedded memories. A march algorithm is composed of several march elements which are used to generate addresses, data, and read/write signals to test a particular memory core. Based on the march elements of the march algorithms, an effective method for the embedded memory core test scheduling has been discussed below. Without losing the memory testing functionality, the march elements of a march algorithm can be performed consecutively by distinct test resources. But here in the proposed march element based test scheduling, two phenomena should be noticed: • •

March elements of march algorithm can be performed consecutively by distinct test resources, & The march elements of distinct march algorithms can be performed by a single test resource.

In the conventional march algorithm based test scheduling, for any test resource, all the march elements of a march algorithm must be performed before executing the next march algorithm. Therefore, the march algorithm based test scheduling is a special case of the march element based test scheduling. It will be shown later that the march element based test scheduling has a great possibility to obtain a shorter testing time of the multiple memory cores. To reduce the total testing cost, appropriate test resources should be considered in the test scheduling. March Element Based Algorithm Without loss of generality, assume K memory cores, C1, C2, .., and CK, are used in a SOC. For testing the pth memory core (p= 1, 2, .., K), the march algorithm, Ap, with m-march element ( m1 ) is expressed as follows: Ap : {Mp1, Mp2, Mp3, .., Mpm} Where the ith march element Mpi (i = 1, 2, .., m) with at most r read/write operations is expressed as:

Mpi =

(opi1, opi2, .., opij) j = 1, 2, .., r

= (up) or (down) or (either up or down) = r0 or r1 or w0 or w1 or del Where the notation r (w) is the read (write) operation and notation 0 (1) is the noninverted (inverted) data backgrounds, respectively.

A simple example depicting the sequence wise allocation of different march elements of a particular algorithm to test the given memory core is shown in figure 4.

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FIGURE 4: Testing for the ith memory core with an m-element algorithm

The march elements of the march algorithms for testing the memory cores are stored in the Core Table as in Figure 5. The jth march element used to test the ith core, Mij, is filled in the blank at the position of the ith row and jth column.

FIGURE 5: The generalized Core Table

Under the power constraint and precedence constraint, the march elements in the Core Table can be mapped onto a Resource Table by using a mapping relationship explained below.

FIGURE 6: The generalized Resource Table

The Resource Table is a result of the march element based test scheduling. As tabulated in Figure 6, a Resource Table with a size of t-row by u-column (where t is the number of test resources, b≤ u ≤a, a is the number of total march elements, and b = a/t). For each row of the Resource Tale, the march elements may be subject to distinct march algorithms. Any march element of the Resource Table has its unique corresponding march element in the Core Tale. Therefore, the mapping relationship between the Core Table and Resource Table is one-to-one. Now let us define few terminologies to help us formulate the entire problem: An untested time array (UTA) for the p core is expressed as: UTA = {T1, T2, .., Tp} 10

Initially, the Ti is the total testing time of the i-th memory core. Let the testing time of the u march elements which are mapped from the Core Table onto the Resource Table be t1, t2, …, and tu, then the busy time (BT) of resources (it implies that none of resources is idle at that time) is: BT = min {t1, t2, …, tu} (4) These u march elements are called the active march elements. If the testing time of any active march element t > BT, then its corresponding test resource is still busy at the next time. The corresponding testing time of the corresponding memory core is excluded temporarily from the sorting of UTA.

Resource Table Formulation Algorithm Step (1): Establish the initial Core Table and Resource Table as tabulated in Tables 2 and 3, respectively. Step (2): Find the initial untested time array UTA and the number of idle resources u. Step (3): Sort the UTA in a decreasing order. Step (4): Under the power constraint, for the memory cores with the first u longest testing length, remove the leftmost march elements of the Core Table and fill in the Resource Table. Step (5): Find the resource busy time, BT. Step (6): If the testing time of the active march elements t >BT, then their corresponding test resources are set to be busy. The corresponding testing time of the corresponding core is excluded temporarily from the sorting of UTA. Step (7): Update the number of idle resources u and replace the value of UTA by {T1-BT,Tp-BT}. Step (8): If the Core Table is non-empty, then repeat from Step (3); else exit the procedure.

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2.4 RESULTS AND DISCUSSION: C1: P1 (power) = 3, T1 = 6, {t11, t12, t13} = {1, 2, 3} C2: P2 (power) = 5, T2 = 13, {t21, t22, t23, t24} = {2, 4, 5, 2} C3: P3 (power) = 4, T3 = 8, {t31, t32, t33} = {1, 5, 2} C4: P4 = 2, T4 = 9, {t41, t42, t43} = {1, 2, 6} C5: P5 = 3, T5 = 15, {t51, t52, t53, t54, t55} = {1, 3, 2, 4, 5} No of Resources available: 3 {R1,R2,R3} Power Constraint: 10

FIGURE 7: The Initial Core Table for the given example

FIGURE 8: The Resource Table for the given example

NOTE: Under the power constraint of 10, the overall testing time is 19.

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If we would have done it by conventional march algorithm way instead of considering all the march elements as separate entity we would have landed up with the result as shown in figure 9:

FIGURE 9: The test scheduling of five memory cores using three resources

Note: Under the power constraint of 10, the overall testing time in this case is 21 This justifies the superiority of March Element based algorithm over conventional March Algorithm based techniques in testing time minimization.

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3. STAGE-BASED TEST SCHEDULING WITH BISR SCHEME 3.1 Theory The testing of memory core with BISR scheme consists of the following three stages: 1. Test with BIST circuitry 2. Diagnosis/repair with built-in repair analyzer 3. Re-test with BIST circuitry

The first stage consists of testing of the memory cores using BIST circuitry. If no fault is detected in this stage, the core is evaluated as pass and the testing is finished. If any fault is detected, it is analyzed whether it can be repaired in the 2nd stage. If the faults are not repairable, it is evaluated as fail and the testing is finished. If the faults are repairable, the repair information is transferred and the memory core is reconfigured to avoid the faulty cells. After that, it is tested by using BIST circuitry again. Finally, the memory core is evaluated as pass or fail depending on the result in the 3rd stage. The test flow is shown in Figure10.

FIGURE 10: BISR test flow for memory core

In test scheduling for memory cores with BISR scheme, all stages are not always executed. For example, if no fault is detected in first test in stage 1, then, it is not necessary to execute the next two stages. This is called abort-on-pass approach. In abort-on-fail approach, the testing is terminated as soon as a fault is detected. An example is shown in figure 11(a). Tf/Tp is the possible set of times when the testing can be terminated due to failure/pass. The test time for the sequential corebased test schedule shown is t6. When the abort-on-fail approach is applied, there is a possibility that the testing can be terminated at the end time of every stage except 1st stages (even if faults are detected at 1st stage in a core, there is a chance that it can be repaired correctly in the following stages). An example is shown in Figure 11(b), where the testing can be terminated at time t2, t3, t5 and t6 depending on the 14

pass probabilities. In addition to abort-on-fail approach, in stage-based test scheduling for memory cores with BISR scheme, we can consider the abort-on-pass approach where the testing is terminated as soon as all cores are evaluated as pass. In Figure 11(b), the testing can be also terminated at time t4 and t6 depending on the pass probabilities. The optimal test sequence based on abort on pass/fail approach is shown in Figure 11(c), which gives the minimum test time.

FIGURE 11: Test time in abort-on pass/fail environment

3.2 Scheduling Algorithm For the test scheduling of memory cores with BISR scheme, the total power consumption during test is of major concern and should be considered not to exceed a certain limit. Therefore, the objective is to minimize the expected test time under the given power constraints. In this report, an efficient and effective stage-based test scheduling algorithm for memory cores with BISR scheme has been described to minimize the overall expected test time. First of all, the algorithm performs stage clustering based on its pass probability so that the stages in each cluster have similar pass probability. Then, it repeatedly selects an unselected cluster with lowest pass probability, and decides test schedule for each stage in the selected cluster. In this step, we select an un-scheduled stage with longest execution time (not lowest pass probability) such that the preceding stages are already scheduled. Then, we schedule it to the earliest time slot such that the power and precedence constraints are satisfied. This process is repeated until all stages in the cluster are scheduled. An overview of the scheduling algorithm is shown in the Figure12.

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FIGURE12: Overview of the scheduling algorithm

Let, Ci represents the ith memory core and its BISR consists of three stages. 1. Si,1 : test 2. Si,2 : diagnosis/repair 3. Si,3 : Re-test For each stage Si,j , the following informations are given. • • •

timei,j : execution time required to complete Si,j poweri,j : power consumption during Si,j ppi,j : pass probability for Si,j

First of all, the fail probability fpi,j for each stage si, j of core ci is calculated.

f pi ,1 = 0

f pi ,2 = (1 − ppi ,1 ).(1 − ppi ,2 ) f pi ,3 = (1 − ppi ,1 ). ppi ,2 .(1 − ppi ,3 ) Now, all the stages are sorted in descending order based on their fail probability. Let S be the set of all the stages except the first stages. The variance Vs of fail probability in S and the threshold variance Vth are calculated as follows.

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VS

∑( f =

pi , j

S

)2

−(

∑f S

Vth = a.Vs

pi , j

)2 Where, α is a constant.

After that, a group G1 is created which consists of the stage with highest fail probability, and the stage with next highest fail probability is added to G1 if the variance VG1, after adding it, does not exceed Vth. This process is repeated until VG1 exceeds Vth. When VG1 exceeds Vth, we create a new group G2 and repeat the same procedure. Whenever the variance VGi of group Gi exceeds Vth, we create a new group and repeat the same procedure until all stages in S are clustered. Finally, 1st stage Si,1 of each core Ci is added to the group where 2nd stage Si,2 of the core belongs in order to satisfy the precedence constraints.

3.3 Results and Discussion An example of clustering is shown in the Table1. Vth is assumed to be 0.001 in this example. There are two clusters G1 and G2 having 5 and 4 stages in them respectively. The stages with zero fail probability (all the first stages) have been added according to the precedence constraint. G1 : VG1 = 0.000867

G1

S1,2 : fp1,2 = 0.20

S1,2 : fp1,2 = 0.20

S1,2 : fp1,2 = 0.20

S2,2 : fp1,2 = 0.15

S2,2 : fp1,2 = 0.15

S2,2 : fp1,2 = 0.15

S1,3 : fp1,2 = 0.13

S1,3 : fp1,2 = 0.13

S1,3 : fp1,2 = 0.13

S3,2 : fp1,2 = 0.10

G2 : VG2 = 0.000289

S1,1 : fp1,2 =

0

S2,3 : fp1,2 = 0.07

S3,2 : fp1,2 = 0.10

S2,1 : fp1,2 =

0

S3,3 : fp1,2 = 0.06

S2,3 : fp1,2 = 0.07

G2

S3,3 : fp1,2 = 0.06

S3,2 : fp1,2 = 0.10

S1,1 : fp1,2 =

0

S2,1 : fp1,2 =

0

S1,1 : fp1,2 =

0

S2,3 : fp1,2 = 0.07

S3,1 : fp1,2 =

0

S2,1 : fp1,2 =

0

S3,3 : fp1,2 = 0.06

S3,1 : fp1,2 =

0

S3,1 : fp1,2 =

0

Table1. An example of the clustering procedure

In the algorithm discussed here, the size of the clusters can be adjusted according to the requirement by using the parameter α. If the execution time is to be given more priority, the size of clusters should be increased. For this, the number of the cluster should be decreased by increasing the value of α and also scheduling should be done in the descending order based on the execution time in this case. On the other hand, if the size of clusters to be decreased to minimize the power, scheduling should be done on the basis of the fail probability of the stages. 17

4. FUTURE DIRECTIONS The March element based scheduling method discussed in this report gives more efficient schedule than the existing March algorithm based scheduling. In future, we intend to make a mathematical model of the scheduling problem and solve it by some linear or Non-linear programming method, which takes care of all the power and precedence constraints. Some heuristical methods like Genetic Algorithm can also be used to solve this problem by making an objective function and optimizing it with the given constraints.

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4. ACKNOWLEDGEMENT I hereby express my indebtedness and heartiest gratitude to my guide Professor S Chattopadhyay, Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, for his valuable suggestions and inspiring guidance in bringing out this project successfully and preparing this report. Prof. S Chattopadhyay supervised and guided me with vital information and motivating discussions throughout the project which were very much fruitful. I am thankful to Ritej Bachhawat, 3rd year undergraduate, Department of Electronics and Electrical Communication Engineering, for all his support during the project work.

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5. REFERENCES: 1. Ivanov A and Wu Y, “Low Power SoC Memory BIST”, Defect and Fault Tolerance in VLSI Systems, 2006, DFT’06, 21st IEEE Symposium , on page(s): 197-205 2. Fujiwara H, Fukuda Y. and Yoneda T, “Test Scheduling for Memory Cores with Built-In Self-Repair”, Proceedings of the 16th Asian Test Symposium, Pages 199-206 3. Wang W L, “March Based Memory Core Test Scheduling for SOC” test Symposium 2004, 13th Asian, on page(s): 248- 253 4. Wu C W, “VLSI Test Principles and Architectures”

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