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Topology and Control Innovation for Auxiliary Power Supply in Dimmable LED Drivers Liang Jia, Member, IEEE and Yan-Fei Liu, Fellow, IEEE [email protected], [email protected]

Abstract- In this paper, a cost effective architecture based on Flyback topology is proposed for both constant current (CC) output for LED drive and constant voltage (CV) output for AUX supply. A novel nonlinear ramp based control scheme is proposed to decouple the main CC power train from the CV AUX supply and avoid LED output flickering. Small signal modeling is presented to highlight the advantages of this control scheme over conventional peak current mode control. This scheme has been implemented successfully for a 40W dimmable LED driver with a 12V 3W AUX supply.

Keywords: Dimmable LED Drivers, Active Cooling Power Supply, Flyback Converter Modeling, Nonlinear Ramp Control, Small Signal Model

Related work: This paper is an improved version of the work presented in ECCE 2014, entitled “Control Scheme for Decoupling Auxiliary Power Supply in Dimmable LED Drivers”.

Liang Jia is with Consumer Hardware Engineering, Google Inc, Mountain View, CA 94043, USA (e-mail: [email protected]). Yan-Fei Liu is with the Department of Electrical and Computer Engineering, Queen’s University, Kingston, ON K7L 3Y4, Canada (e-mail: [email protected]).

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I.

INTRODUCTION Due to the rapid transformation of lighting technology, light-emitting diode (LED) becomes

the promising light source for the future world and provides: longer lifetime, higher energy efficiency, eco-friendly, better light quality, easier dimming and color control, etc to the consumers. Unlike incandescent light source, LED requires a control gear (usually called LED driver) to provide a constant current (CC) driving current preferably for the best light output performance. As the Internet of Things (IoT) continues to proliferate, connected and smart solutions are influencing more and more areas of our lives, as well as lighting sector. From system point of view, the additional smart features will require separate power and voltage domains from LED load, therefore, integrating an auxiliary (AUX) power supply into LED drivers is an ideal option to facilitate LED luminaire system design and reduce system cost and complexity. This section comprises of a comprehensive overview of the latest trends for indoor dimmable LED drivers, including voltage window, 0-10V dimming controls, and requirements for auxiliary power supplies. A.

Wide Operation Window and Dimming One major challenge of designing LED driver (often being ignored in academic research) is

the need of supporting a wide range of output voltage window [1]. The advantage of a wide voltage window driver is very obvious: 1) reduction of cost, number of stock keeping units (SKUs) and logistic complication; 2) reliability enhancement of LED load variation; 3) system design flexibility, etc. An LED driver operation window can be defined using a V-I mapping [2]. In Figure 1, two types of windows are illustrated, A type (red) and B type (blue) [3][4]. In this example, the two types of operation windows have the same VLEDmin and ILEDmin. In both cases, the maximum LED voltage (VLEDmax), minimum LED voltage (VLEDmin), maximum LED current (ILEDmax), minimum LED current (ILEDmin) are defined. In the LED lighting industry, for a high performance LED driver, it often has a 2:1 window of VLEDmax:VLEDmin [3][4]. The LED driver should provide protection for LED over voltage and over current and the levels are called VLEDOVP and ILEDOCP. Usually, the VLEDOVP is 5-10% higher than VLEDmax (only Type B VLEDOVP is shown) and ILEDOCP is defined based on the LED specifications. Also, driver may offer under voltage protection to prevent LED or driver damage during this abnormal condition and the VLEDUVP level is usually 10% lower than the nominal VLEDmin.

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In both windows, the LED practical operating window is drawn in solid-line boxes. The slope of

Δ𝑉𝑉𝐹𝐹 Δ𝐼𝐼𝐹𝐹

in the LED practical operating window is determined by the LED dynamic resistance

[6][7][8][9]. In type A window, it is worth noticing that due to the LED dynamic resistance, a portion of the driver operation window cannot be practically used (for example, the red * operating point in the window). For a reliable design, the driver should be able to operate properly and meet all the design specifications at the corner of VLEDmax*ILEDmax, i. e. Pmax. In order to extent the window for a same power capability, type B is introduced for alternative. The constant power line is defined for a power of VLED*ILED=Pmax. In this way both the VLEDmax (B) and ILEDmax (B) can be extended from the A type window. And the practical LED load operation window is thus extended significantly. B type window utilizes the power capability of the LED driver more efficiently.

VLEDOVP (B)

VLED 5~10% of nominal VLEDmax

VLEDmax (B) VLEDmax (A)

B Constant Power Line

Pmax A

VLEDmin

*

Slope

10% of nominal VLEDmin

VLEDUVP

ILED ILEDmin

ILEDmax (A)

ILEDmax (B)

Figure 1 LED driver operation window: A and B types Dimming control becomes very common for LED lighting application due to the simplicity of controlling light output by driving current [10]-[12]. A commonly used low voltage dimming interface for indoor lighting is 0-10V dimming interface. There are many different names of this interface, for example, Mark 7 dimming (first introduced by Philips in North America), 1-10V dimming (in Europe), etc. And it was firstly introduced for dimmable fluorescent lighting system and adapted later into HID and LED-based lighting (both indoor and outdoor applications). The 010V dimmer can be simply designed as a variable resistor and the ballast/driver has to provide a

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power source to generate a voltage potential between the two dimming leads (usually violet as positive, and grey as negative). To sum up, for industrial LED applications, the LED driver has to support a wide range of LED load voltage and current, especially in dimmable applications. B.

Auxiliary Power Supply Even though high-brightness LEDs (HBLEDs) are rapidly advancing in terms of energy

efficiency, heat remains the nemesis of most HBLED illumination systems as shown in Table 1 generated by non-radiated recombination of electrons and holes in the HBLED semiconductor material. Although LEDs have the advantage of producing light in a narrow, well-defined wavelength, this also limits the devices’ ability to radiate excess heat in the form of infrared energy [13][14], therefore, still around 60-75% of the LED power remains as heat [2][15]. Table 1 Heat and energy distribution of various white light sources Fluorescent

HID (Metal Halide)

60W Incandescent

25-40%

21%

27%

8%

Infrared

~0%

37%

17%

73%

UV

0%

~0%

19%

0%

Total Radiant Energy

25-40%

58%

63%

81%

Remaining Heat

60-75%

42%

37%

19%

White HB LED Visible Light

Other than increase the heat sinking capacity in the LED luminaire, a growing number of indoor LED lighting applications will require forced-air convection because of the high intensity of light needed such as recessed light, spot light and track light. Regular fans, however, introduce life time and reliability concern and for indoor application the undesirable motor noise is also a disadvantage. A novel cooling solution is called SynJet cooler [14][16]. These small coolers use an electromagnetically-coupled diaphragm to pulse high-velocity jets of air through nozzles. As the air is forced out of the nozzle, a vortex is created. Once the vortex flow propagates downstream from the nozzle, it entrains the surrounding air [16]. The cooler requires 12V DC power supply to provide DC+AC current. Also, due to the downward-trending prices and limited price competition opportunities in “conventional” LED lighting, the ability to provide new value-added features, such as connectivity,

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enables additional growth potentials. Therefore, a deeper transition towards smart solutions becomes a natural direction for the entire LED lighting industry [5]. The idea that lighting can now communicate (via wireless network) and interact with the environment (via various sensors) and the people or things around it, is opening up a new requirement for power delivery in the system to supply the added features. 12V DC is a general voltage level to support multiple digital and analog voltage domains (5V, 3.3V, etc) just like in computing application. So from system point of view, a preferred low-medium power indoor LED driver architecture should offer a built-in auxiliary power supply for cooling or digital control/communication devices. A lot of research has been conducted for single stage Flyback LED driver with PFC for low power application, however, the high output ripple at low frequency is not favorable for high performance dimmable indoor application [17]-[23]. In [24]-[27], several methods have been discussed to reduce or cancel the low frequency ripple. Boost PFC+Flyback topology is a low cost and good candidate for low-medium power LED application (25W2W) directly from conventional Flyback topology for dimmable LED lighting application. So, in this paper, a novel power architecture and control scheme is proposed to offer a decoupled CV power supply for the purposes of active cooling, lighting control, sensing, etc from the same power converter, which outputs CC to the LEDs. In section II, existing techniques and issues are introduced for research background. In section III, the control scheme is outlined and the proposed scheme generates a nonlinear ramp to decouple the CV output from CC output and prevents from light flickering during fan operations in LED dimming condition. In section IV, the operation and implementation of the proposed control scheme is explained in details. The implementation of the controller can be based on commonly used peak current mode (PCM) controller and no additional silicon development is required. In section V, small signal model is built to analyze the advantages of the propose controller. Experimental results verify the benefits of this proposed LED driver architecture and control scheme in a 40W 700mA 0-10V dimmable LED driver in section VI. Finally, conclusion is drawn in the end of the paper. Appendix is also provided for detailed derivation for some of the critical design equations in the paper. A version of this paper was presented at the ECCE 2014 conference [1]. The paper has been extended and improved, and derivation of critical design equations has been added.

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II.

EXISTING TECHNIQUES AND ISSUES In order to better illustrate the significance of the proposed technology, a detailed review of the existing techniques to create CV auxiliary supply is provided in this section. There is a possibility of using auxiliary winding in the Boost PFC inductor to create an auxiliary power supply, however, 1) with peak detector output (diode rectifier and output capacitor) from either a flyback or forward winding, the rectified AC line voltage will be reflected to the auxiliary output, resulting in large voltage variation; and 2) with charge pump supply, the variation may also occur at line voltage zero crossing moment, due to higher current draw to support the constant auxiliary power. And overdesigned charge pump supply will require output voltage clamp to prevent from over voltage event at no load and very light load condition at the auxiliary output, resulting in unnecessary power losses. More importantly, in both cases, the commonly used peak current mode controlled Boost PFC performance will be degraded, especially at line voltage zero crossing, when higher auxiliary current is reflected and added on top of the sensed Boost inductor current. Therefore, in this paper, the input AC rectifier and Boost PFC stage is ignored for simplicity and the input to the Flyback converter will be a well-regulated DC bus voltage. The first solution is shown in Figure 2, and a multi-output Flyback converter is used to generate the auxiliary supply. The flyback voltage Vfb is roughly proportional to the output voltage Vout. However, as outlined in section I, for a wide window LED driver (for example, VLEDmax:VLEDmin=3:1), the variation of flyback voltage Vfb (the input of the auxiliary power supply) is 3:1 roughly. If non-ideal transformer coupling is considered for different LED driving current scenarios, the voltage variation from the flyback winding will be much larger. Therefore, flyback winding is not suitable to provide a constant input level Vfb for the AUX supply. Otherwise, it requires a Buck-Boost stage to deal with the wide input range of Vfb. For example, if the designer selects Vfbmin>12V at minimum number of LEDs to design the 12V AUX supply using Buck converter, then at maximum number of LEDs, the Vfbmax will be larger than 36V, efficiency will be compromised and power component cost will be increased to handle higher voltage stress.

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T1 AC Input Rectifier+ Boost PFC

+ Vout

D1 W1

Vbus

LEDs W2

Vfb

D2 Q1

AUX supply (for example, Buck Converter)

To Fan Cooling/ Controller, etc

Figure 2 AUX supply from a Flyback winding The second method is shown in Figure 3. An additional Buck converter stage is powered directly from the LED main output. Other than the aforementioned range of Vout for AUX supply input, the operation of AUX supply will interrupt the main power train, resulting in LED output flickering or other light quality degradations. Expensive switcher IC/bulky configuration will be required for designing the Buck stage with >60Vmax input. T1 AC Input Rectifier+ Boost PFC

+ D1

Vout

W1

Vbus

LEDs -

Q1

AUX supply (for example, Buck converter)

To Fan Cooling/ Controller, etc

Figure 3 AUX supply from main LED output The third method as shown in Figure 4 is to use a separate Flyback converter powered from the high voltage DC bus for CV AUX supply. This configuration is used in some design that requires isolated standby power supply. During the standby mode, the main power train MOSFET Q1 will be off all the time, as well as the PFC stage. The Vbus will be the rectified line voltage filtered by

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Vbus capacitor and FET Q2 is controlled to regulate the AUX output voltage. However, in LED lighting application for thermal management purposes, the fan will only need to be operated when the LED light output power is high and additional heat dissipation is required. So for the auxiliary supply, the standby mode is not applicable. Although using this option, the AUX supply load is also completely independent from the main LED power train, the design will be bulky and more expensive, because of the extra high voltage switch/switcher IC [28], isolation transformer, etc. AC Input Rectifier+ Boost PFC

T1

D1

+

Vout W1

Vbus LEDs -

Q1 T2

D2 W2

Q2 AUX supply (for example, Buck Converter)

To Fan Cooling/ Controller, etc

Figure 4 AUX supply from a dedicated Flyback converter Another option is shown in Figure 5, where a forward winding is used to provide a relatively constant DC voltage Vfw (about 20V) from the DC bus and a Buck converter to step down this DC voltage for 12V AUX supply. A cost effective and commonly available switcher IC can be used for this AUX supply [31]. However, using conventional peak current mode control (PCMC), when the LED string is dimmed by dimmer, the AUX load starts affecting the main power train more severely and causing visible flicker at the LED output. This issue will be analyzed in more details in the next section.

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T1 AC Input Rectifier+ Boost PFC

+ D1

Vout

W1

Vbus

LEDs W2 D2

Vfw

Q1 AUX supply

To Fan Cooling/ Controller, etc

Figure 5 AUX supply from a forward winding This section provides a detailed review of the existing technology for generating a CV auxiliary power supply, including flyback winding supply, main output converter, dedicated Flyback converter and a forward winding supply. The issue of each of the methods is also outlined.

III.

PROPOSED DECOUPLING METHODS To resolve the issues discussed in the previous section, a new control scheme is presented in this section to decouple the AUX supply from the main LED driving power train. The forward winding offers a relatively constant output voltage with fixed ratio to the DC bus voltage. This makes forward winding a promising option for this CV AUX application with lower cost and system complexity. At 40W power level, where conduction loss is not yet dominant, BCM Flyback offers such benefits as smaller size of the magnetics (lower inductance) [29], higher efficiency (lower switching loss on the main FET with nearly voltage valley switching and zero current switching; lower output rectifier reverse recovery loss), etc, compared with CCM mode or fixed frequency Flyback with conventional voltage mode duty cycle control. Also, loop compensation will be more complicated due to the relatively lower frequency RHP zero in CCM Flyback converter [30]. So in this paper, the conventional peak current mode control (PCMC) is selected and used for Flyback converter control as illustrated in Figure 6. In the case shown in Figure 6 (A), Flyback stage is operating without the AUX supply in BCM. Ve signal is the output from the error amplifier (EA). And the main FET Q1 sensing signal is IQ1*Rsense and as soon as the equation (1) is satisfied, Q1 will be turned off. Q1 turns back on again when the magnetizing current of T1 goes to zero.

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V= I Q1 ⋅ Rsense e

(1)

However, once the forward winding is employed for the CV AUX, it is noted that the current reflected from forward winding IFW will be also added to the main FET drain current IQ1 during tON. IFW is varying with the AUX load demanding, Vbus low frequency ripple, Vo, etc. The triangular shape of the sensing signal IQ1*Rsense is thus distorted. At full power or heavy LED load condition when Pout>>Paux, flyback winding current IFB is still dominant as shown in Figure 6. (B). But at LED dimming condition, the variant reflected forward winding current IFW will start to dominate the IQ1peak shown in Figure 6. (C) and the on time tON will vary a lot cycle by cycle, resulting in system instability and LED output random flickering. Heavy LED load without AUX load Ve

IQ1*Rs1

PWM tO N

tO FF

A Heavy LED load with AUX load Ve IQ1*Rs1 IFB*Rs1

IFW

PWM tO N

tO FF

B

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Light LED load during dimming with AUX load

Ve IFW IFB*Rs1 IQ1*Rs1

PWM tO N

tO FF

C Figure 6 Conventional peak current mode control L

N

+

D1

ZCD

Rs2

Control Logic

-

Na S

FB + _

Ve

LEDs Voltage Regulation

Np

ZCD Circuitry

+ _ Vref

Io

Wp

-

EA

+ Vo

W1 Ns

Vin=Vbus

FB

Id

T1

AC Input Rectifier+ Boost PFC

VPWM Q

R

PWM

D2

+ Iref

Ia

DOCP

CS

R2

Vcc

Current Regulation

Ip

(optional)

AUX supply Buck Converter

Rsense

+

0-10V Dimming Interface

R1

DR2

_

Vfw

Lka

Q1

Iout_sen

Ca

W2

Gate Drive

0-10V Dimmer -

To Fan Cooling/ Controller, etc

Rs1 Q Dz1

+

Rd1

Vramp

Cs1 Rd2

Nonlinear Ramp Generator

D4 FB

-

To Fan Cooling/ Controller, etc

D3

Opto

D5

PE

Temp. Regulation

NTC/PTC

Driver Housing

Figure 7 Proposed system, functional blocks and LED driver connection Therefore, in order to take full advantage of the power architecture shown in Figure 5, a novel control scheme is proposed to offer a decoupled CV auxiliary power supply for the purposes of active cooling, lighting control, sensing, etc from the same power converter, which delivers CC to the LEDs. Proposed system and functional blocks are shown in Figure 7. The 0-10V dimmer is connected to the LED driver using the violet (positive) and grey (negative) wires and the dimmer circuit is shown in Figure 23. The LED driver internal 0-10V diming interface block will 1) provide bias current to the 0-10V dimmer (150µA for example) and create a DC voltage (0-10V in this

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case, according to the dimmer position) between violet and grey wires; and 2) read this DC voltage and translate it into Iref for setting the output current reference in the current regulation loop. Different from the linear ramp signal from the sensed IQ1, the control scheme generates a nonlinear ramp (highlighted in red in Figure 7) to 1) decouple the CV output from CC output and prevents from light flickering during fan or other auxiliary load operations; 2) improve noise immunity of the controller at dimming condition; 3) reduce the variation of the system loop response at different operating conditions for easier compensation design and 4) offer optional redundant over current and over power protection. The ramp signal Vramp is generated (from the PWM gate signal of the main FET Q1) to substitute the current sensing signal IQ1*Rsense in the control scheme, as shown in Figure 8 (A), (B) and (C). This Vramp signal will then compare with Ve to turn off the FET in each switching cycle. The function of Vramp is predefined to modulate tON based only on LED output regulation feedback loop (i. e. Ve signal), so Vramp is not influenced by IFW anymore. Detailed design guidelines will be provided in the next sections. For example, in Figure 7, when higher LED output current is desired, the current reference signal Iref will be increased on the secondary side. And the secondary side error amplifier will compensate the LED output current. Through the closed feedback loop control, Ve will be increased to Ve’. Vramp’ thus follows to reach Ve’ and finally extends tON’ for larger LED output current in Figure 8 (A) (in dashed green). In another case, when LED current is under steady state, if AUX load is increased, tON will not be changed because of the unchanged Iref and Ve, but IFW’ will be higher during tON’ to provide more power for AUX load in Figure 8 (B) (in dashed red). Besides the coupling impact, the instability at full dimming condition can be also caused by the very low sensing signal (IQ1*Rsense) level (at around 10mV using conventional current mode control scheme), which is very sensitive to board noise (caused by

𝑑𝑑𝑑𝑑 𝑑𝑑𝑑𝑑

and

𝑑𝑑𝑑𝑑

𝑑𝑑𝑑𝑑

). So a nonlinear type of ramp

signal is proposed and shown in Figure 9, which has higher slew rate at the beginning of the charging process and then slows down until it reaches the Ve level.

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Duty cycle change with increased LED output demand Ve Vramp

Ve’

Vramp’

IFB*Rs1

PWM tON

tOFF

A Heavy LED load condition with increased AUX demand Ve Vr amp

IFB*Rs1

IFW

IFW ’

PWM tO N

tO FF

B Light LED load during dimming with AUX load

Ve IFW

Vr amp

IFB*Rs1

PWM tO N

tO FF

C Figure 8 Proposed nonlinear ramp control scheme

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For a typical application at this power level, the FET turn-on time tON is usually around hundreds of nano-seconds (tONmin) to several micro-seconds (tONmax). A proper time constant of τ=Rs1 Cs1 is selected accordingly, where tONmin<τ
Figure 9 Simulated nonlinear ramp signal (Green: ramp level at tONmax; Blue: ramp level at tONmin)

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IV.

BASIC OPERATIONS AND SYSTEM IMPLEMENTATION The system implementation diagram is shown previously in Figure 7. The AUX supply is

powered from forward winding W2 and D2. AUX supply block is typically a step down DC-DC switcher (for example, ST 5970D [31]) to create 12Vdc, 250mAmax supply. The input of the ramp generator is the gate signal from the gate control logic IC. The output of the ramp generator is called Vramp, which simulates the signal of IQ1*Rsense. The real current sensing signal (=IQ1*Rsense) is used for redundant OCP and OPP only. The gate control logic will compensate the loop according to the FB signal from secondary side (using built-in EA, the output of EA is called Ve) and turn off Q1 as soon as the Vramp>Ve. On the secondary side, the current regulation loop passes the feedback signal FB to the primary side across the isolation barrier through the optocoupler. R2

Vcc

R1 VPWM

DR2

Rs1

Q Dz1 Rd1

Vramp

Cs1 Rd2

Figure 10

Analog ramp generator

In Figure 10, an analog circuit implementation of the ramp generator is shown. VPWM is the gate signal from the gate control logic IC. R1 and Dz1 clamp the signal to a square waveform (Vhigh=Vgd). RS1 and CS1 form a RC time constant τ and the square waveform will be filtered to generate the ramp signal. When the gate signal VPWM is at about 0V, R2 and DR2 will help to quickly discharge CS1 to about 0.6V. In order to compensate the diode forward voltage drop of DR2 and increase loading capability, a bipolar emitter follower Q stage is used to condition the signal. Rd1 and Rd2 form a voltage divider for proper Vramp signal level. To properly design the nonlinear ramp generator circuit, the design rules are provided in equations (2)-(5). Based on the Flyback converter principles, the maximum turn-on time tONmax can be calculated using equation (2). Please refer to Appendix A for more details for derivation.

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tON max

− β + β 2 − 4αγ = 2α

(2)

And the parameter α, β and γ can be calculated in equations (3)-(5). Vinmin is the minimum input DC voltage (425V in this case) to the Flyback stage, in this case is the DC bus voltage. Lm is the primary magnetizing inductance of the transformer. Ctot is the total equivalent output capacitance of the MOSFET. Vomax is the maximum output voltage of the Flyback converter. Pomax is the maximum output power. VF is the forward voltage of the output rectifier diode. η is the efficiency of Flyback power stage. Please refer to Appendix A for more details for derivation.

α=

1 Vin min 2 2 Lm

(3)

 P  Vin min β= − o max  + 1 η  n (Vo max + VF ) 

γ= −

Po max

η



LmCtot

)

(4)

(5)

Based on the calculation, the maximum tON at different operating points is shown in Figure 11. At maximum power (700mA and 60V), tON is about 4.5µs and at minimum power (70mA and 20V), tON is about 500ns. And the results match the simulation closely shown in Figure 9. In the experimental results section, it will demonstrate that the calculated results also match the experiments very well.

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Figure 11

Maximum tON time at different operating conditions at Vinmin=425V

Finally, we need to make sure the voltage Vramp in equation (6) to the gate control logic is less than the over current protection threshold level. In this way, we can tune the RS1 and CS1 to achieve maximum output power. In Figure 12, the equivalent circuit of the ramp generator is shown. When the gate is off, the voltage of Cs1 is clamped to the diode voltage VF_DR2 after the discharging of Cs1 through R2. And the ramp voltage Vramp at this moment will be roughly 0V, due to the compensation between Vbe of Q and VF_DR2. When the gate drive voltage is high, the capacitor Cs1 voltage will be charged up and the voltage of the ramp can be calculated in equation (6). Vbe is the base-emitter voltage of Q and VF_DR2 is the forward voltage drop of DR2 in Figure 10. Vgd is the clamping voltage of Dz1. It is noted that in equation (6), there are actually two design parameters: 1) the time constant τ=Rs1 Cs1 and 2) the divider ratio

𝑅𝑅𝑑𝑑2

𝑅𝑅𝑑𝑑1 +𝑅𝑅𝑑𝑑2

. So based on the desired peak ramp voltage levels for

tonmin and tonmax, the designer can solve these two parameters simply and flexibly.

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R2 _ VF_DR2 Rs1

+ + Rd1

Vbe

Rs1

Vbe

_

+

Vgd Vramp

Rd1

Cs1

Cs1

_

Vramp

VIC=VF_DR2

Rd2

Rd2

ON

OFF

Figure 12 Equivalent circuit for the ramp generator during ON and OFF modes − tON max   Vramp= VF _ DR 2 + Vgd 1 − e Rs1 ⋅Cs1   

 R   d2  − Vbe       Rd 1 + Rd 2  

(6)

The relationship between control signal Vramp and LED current Io is plotted in Figure 13. For example, when the LED load voltage is 60V and current is 700mA, the Vramp peak value is about 1.3V. While the LED load voltage is 20V and current is 70mA, the Vramp peak level is around 200mV. This result matches the simulation in Figure 9 also very well.

Figure 13 LED current Io VS control signal Vramp at Vinmin=425V

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V.

SMALL SIGNAL MODELING In this section, the small signal model is derived to provide the insight of the coupling issue

between CC and CV outputs using PCM control and the benefits of the proposed method. Flyback converter can be analyzed with a Buck Boost equivalent model shown in Figure 14 (left side). In the practical implementation, the leakage inductance of the Flyback transformer can be controlled lower than 1% of the magnetizing inductance, therefore, in the model, the leakage inductance is ignored. And the average large-signal model of a peak current controlled Flyback converter (in BCM) can be obtained by replacing the semiconductors Q1 and D1 in Figure 14 (left side) with dependent current sources Iac and Ipc [33]-[40]. Iac is the average current of the MOSFET Q1 and Ipc is the average current of the diode D1 over a switching cycle.

c

a p

rC

_ Rdyn

Vo _

+

+ VL

c

p

+

L/N2

Co

Ipc

+

a

VIN/N

Iac

ipc

+

VIN/N

L/N2

_

Co Rdyn

VL _

iac

rC

Vo +

_

_

Figure 14 Equivalent Buck Boost Model for Flyback converter and average large signal model When the AUX supply is loaded and Q1 is on (shown in Figure 7), the current flows through the diode D2 is near-constant and continuous due to winding leakage inductor Lka and output filter capacitor Ca. It is assumed that the average AUX load current is Ia. The average output diode current Id can be calculated in equation (7), where VF is the forward voltage of D1, Vo is the output voltage, Vin is the bus voltage, 𝑛𝑛 =

𝑁𝑁𝑝𝑝 𝑁𝑁𝑠𝑠

, and 𝑛𝑛𝑎𝑎 =

𝑁𝑁𝑝𝑝

𝑁𝑁𝑎𝑎

. Please refer to Appendix B for more details for

derivation of equation (7), using PCM control.

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 n ⋅ Ve I a ⋅ Vin + n (Vo + VF )   Vin I d (Vin , Vo ,= Ve , I a )  −   2 Rsense  Vin + n (Vo + VF ) 2na ⋅ (Vo + VF )   ^

Id

(7)

Z ^

Io ^

^

^

K in Vin

K e Ve

Ka Ia

^

K o Vo

Co

+

^

^

I ac

Rdyn

Vo

rC

Figure 15

-

Small Signal Model

The small signal model can be obtained by setting all DC source values to zero (in Figure 15). Then Id is linearized around its steady state operating point in (2), where 𝐾𝐾𝑒𝑒 =

𝐾𝐾𝑜𝑜 =

𝜕𝜕𝐼𝐼𝑑𝑑

𝜕𝜕𝑉𝑉𝑜𝑜

and 𝐾𝐾𝑎𝑎 =

𝜕𝜕𝐼𝐼𝑑𝑑 𝜕𝜕𝐼𝐼𝑎𝑎

𝜕𝜕𝐼𝐼𝑑𝑑

𝜕𝜕𝑉𝑉𝑒𝑒

, 𝐾𝐾𝑖𝑖𝑖𝑖 =

𝜕𝜕𝐼𝐼𝑑𝑑

𝜕𝜕𝑉𝑉𝑖𝑖𝑖𝑖

,

. The equations of Ke, Kin, and Ko for a Flyback converter without AUX

load (i.e. Ia=0) are presented in (9)-(11). It is noticed that in the small signal model in equation (8),

there is a coupling gain -Ka path from 𝐼𝐼�𝑎𝑎 to 𝐼𝐼�𝑑𝑑 , where Ka can be calculated in equation (12), resulting in LED output flickering, while auxiliary loading is varying. ^

^

^

^

^

I d = K e Ve + K in Vin + K o Vo − K a I a nVin 1 Vin + n (Vo + VF ) 2 Rsense

(9)

n (Vo + VF ) nVe 2 Rsense Vin + n (Vo + VF )  2  

(10)

n 2Ve Vin 2 Rsense Vin + n (Vo + VF )  2  

(11)

Vin 2 ⋅ na (Vo + VF )

(12)

Ke =

K in =

(8)

Ko = −

Ka =

The transfer function from error voltage 𝑉𝑉�𝑒𝑒 to output current 𝐼𝐼�𝑜𝑜 is obtained in equation (13),

where Z is the output impedance in equation (14) and Rdyn is the LED dynamic resistance [8].

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^

Io Z ⋅ Ke = Gie = ^ Ve V^ =0 Rdyn ⋅ (1 − Z ⋅ K o )

(13)

in

Z=

Rdyn (1 + s ⋅ Co ⋅ rC )

1 + s ⋅ Co ⋅ ( rC + Rdyn )

(14)

Bode plot of Gie for conventional peak current mode control is shown in Figure 16. When the Flyback stage is operating at VLEDmin=20V, the DC gain is higher and zero location is at higher frequency, compared with VLEDmax=60V (shown in Figure 16) for the same output current. This explains that using the same compensator, Flyback LED driver stage is less stable when powering less number of LEDs.

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Figure 16

Bode plot of Gie for conventional peak current mode control

Using the same modeling principles, the average diode current Id of Flyback stage controlled by the proposed nonlinear ramp control scheme can be calculated as equation (15), where tON can be obtained in equation (16). Please refer to Appendix C for more details for derivation.

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= I d (Vin , Vo , Ve )

nVin 2

TR ⋅ n (Vo + VF )   2 Lm ⋅ Vin + n (Vo + VF ) +  tON  

⋅ tON

(15)

 V R + Rd 2  tON = − Rs1Cs1 ln 1 − e d 1   V R gd d 2  

𝜕𝜕𝐼𝐼𝑑𝑑

𝜕𝜕𝑉𝑉𝑖𝑖𝑖𝑖

(16)

The small signal model can be derived using the equation in (17), where 𝐾𝐾𝑒𝑒 ′ =

, and 𝐾𝐾𝑜𝑜 ′ =

𝜕𝜕𝐼𝐼𝑑𝑑

𝜕𝜕𝑉𝑉𝑜𝑜

. The equations of Ke’, Kin’, and Ko' are represented in (18)-(20). ^

^

^

, 𝐾𝐾𝑖𝑖𝑖𝑖 ′ =

^

I d =K e 'Ve + K in 'Vin + K o 'Vo

 nVin 2   2 L ⋅ V + n (V + V ) + TR ⋅ n (Vo + VF )  m  in o F  tON   ∂I d  K = = e ' n 2Vin 2 (Vo + VF ) ⋅ TR ∂Ve  + 2  2 L ⋅ V + n V + V + TR ⋅ n (Vo + VF )  ⋅ t ( o F) m  in  ON  tON   

(17)

  Rd 1 + Rd 2    Rs1Cs1 V R gd d 2  V R   1 − e d 1 + Rd 2  V Rd 2 gd   

 TR  −n 2Vin 2 1 +  tON  ∂I d  = = K t o' 2 ON ∂Vo TR ⋅ n (Vo + VF )   2 Lm Vin + n (Vo + VF ) +  tON  

K = in '

𝜕𝜕𝐼𝐼𝑑𝑑

𝜕𝜕𝑉𝑉𝑒𝑒

∂I d = ∂Vin

nVin 2 + 2n 2VinVo +

2n 2VinVo ⋅ TR tON

TR ⋅ n (Vo + VF )   2 Lm Vin + n (Vo + VF ) +  tON  

t

2 ON

    (18)  

(19)

(20)

� � It shows that the current 𝐼𝐼�𝑑𝑑 is not related to 𝐼𝐼�𝑎𝑎 , but a function of 𝑉𝑉�𝑜𝑜 , 𝑉𝑉 𝚤𝚤𝚤𝚤 and 𝑉𝑉𝑒𝑒 in equation

(17). So the output current is completely decoupled from the auxiliary load and also has the capability against Vo and Vin transients.

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Similarly, the transfer function from error voltage 𝑉𝑉�𝑒𝑒 to output current 𝐼𝐼�𝑜𝑜 is obtained in

equation (21).

^

Io Z ⋅ Ke ' Gie = = ^ Ve V^ =0 Rdyn ⋅ (1 − Z ⋅ K o ')

(21)

in

It is noticed that by using the proposed control scheme, when the Flyback stage is operating at VLEDmin=20V, the DC gain is reduced and getting closer to the case of VLEDmax=60V (shown in Figure 17). At minimum current condition, the DC gain is also reduced to make the system easier to control for system stability.

Figure 17

Bode plot of Gie for proposed control scheme

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VI.

EXPERIMENTAL VERIFICATION The design parameters of the prototype used in the experiments are shown in Table 2.

Table 2 Design Parameters in the experimental prototype Design Parameter

Design Value or Description

Vin

425Vdc (min)

Vomin

20Vdc

Vomax

60Vdc

Iomin

70mA

Iomax

700mA

Lm

3.0mH EE 25/16/9 core

Lk

Leakage inductance, 25µH (max)

n

122:30

na

122:6

Q1

STF5N95K3 FET N 950V 3.5 Ohm TO-220FP

D1

2x ES2G in parallel Diode, 400V, 2A, SMB

Rs1

5.1kΩ

Cs1

470pF

Rd1

10kΩ

Rd2

1.5kΩ

Rsense

2.7Ω//2.7Ω

LED Load

LUMILEDS LUXEON Rebel ES

Auxiliary Load

1.8W Fan Load+1.2W Resistive Load

In Figure 18, at full output power, the Vramp signal peak shown in CH2 (green) is close to 1.3V and the maximum tON is about 4.5µs and the maximum power 40W can be achieved. This is very similar to the simulation in Figure 9 and calculated results in Figure 11 and Figure 13. Compared

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with the real current sensing signal in CH3 (pink), Vramp clearly shows a saturated nonlinear top. In the experiment, a fan load (1.8W output power) is used as a worst case load with DC+AC current demand. The fan’s vibrator is working during the higher half of the cycle, resulting in noisy current waveform in Figure 18 CH1 (Yellow).

Figure 18

Experimental results at full load (CH1-Yellow: Fan current; CH2-Green: Vramp; CH3-Pink: IQ1; CH4-Blue: Vds of Q1)

In Figure 19, LED output power Pout=1.4W (3.5% of Pmax), the Vramp signal peak is close to 200mV and the minimum tON is about 500ns. This is very similar to the simulation in Figure 9 and calculated results in Figure 11 and Figure 13. The minimum power can be reached with the same fan load running at the same time. From the zoom-in figure on the bottom, a stable switching is observed; even the FET current sensing signal (CH3: Pink) is distorted by the fan load.

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Figure 19

Experimental results at light load (CH1-Yellow: Fan current; CH2-Green: Vramp; CH3-Pink: IQ1; CH4-Blue: Vds of Q1)

A MOSFET is used to switch the auxiliary load on and off with gate control signal in the following auxiliary load transient tests. The load consists of a resistive load and a cooling fan load. The additional resistive load is to increase the loading transient step and the slew rate, due to the slow ramping up of the fan load. In Figure 20, AUX load transient test is conducted at 0.1Hz switching. The CH1 (Yellow) signal is the load control switch voltage (drain to source), so during loading on the auxiliary supply, the switch is closed and zero voltage is across drain to source. While during the unloading step, the switch is off and about 12Vdc is across the drain to source. From the zoom-in figure, it demonstrates a flat and non-interrupted output current in CH2 (Green) at 20V minimum LED voltage and 70mA driving current (10% dimming).

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Figure 20 Transient performance during AUX load changes at 0.1Hz (CH1-Yellow: Control switch voltage of the auxiliary load, CH2-Green: Load current at 70mA, CH3-Pink: Auxiliary load current, 1.2W resistive load+1.8W fan load) In Figure 21, 1kHz AUX load transient test is conducted and in this case, the fan load is inactive. The CH1 (Yellow) signal is again the load control switch voltage (drain to source), so during loading step, the switch is closed and zero voltage is across drain to source. While during the unloading step, the switch is off and about 12Vdc is across the drain to source. From the zoomin figure, it demonstrates a flat and non-interrupted output current in CH2 (Green) at 20V minimum LED voltage and 70mA driving current (10% dimming).

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Figure 21 Transient performance during AUX load changes at 1kHz (CH1-Yellow: Control switch voltage of the auxiliary load, CH2-Green: Load current at 70mA, CH3-Pink: Auxiliary load current, 1.2W resistive load+1.8W fan load) The comparative Bode plots of Gie are shown in Figure 22 for the proposed scheme using mathematical model and experimental measurements. It demonstrates that the presented small signal model is very accurate up to several kHz, where the system cross over frequency will locate. And beyond 10kHz, the small signal model based on the average value of each switching cycle starts to deviate from the measurement [45]. The system can be designed to be less sensitive for Vo change and the system DC gain is reduced at lower Vo. (VLEDmax=60V, ILEDmax=700mA, VLEDmin=20V, ILEDmin=70mA).

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10 Gain (dB)

0 -10

Model-VLEDmax Gain

-20

Model-VLEDmin Gain Measured-VLEDmax Gain

-30

Measured-VLEDmin Gain

-40 0 Phase (deg)

Model-VLEDmax Phase Model-VLEDmin Phase

-30

Measured-VLEDmax Phase Measured VLEDmin Phase

-60 -90 10

Figure 22

100 Frequency (Hz)1000

10000

Bode plot of Gie for proposed control scheme, mathematical model VS measurements

A typical 0-10V dimmer circuit is shown in Figure 23. VRmk7, Rmk72, Cmk7 and Qmk7 form an adjustable voltage source. The voltage between base and emitter, Vbe is used in this case as the reference voltage at about 0.6V and the voltage between violet and grey leads can be calculated in (22). Zmk7 is for over voltage protection when the user misconnects the dimmer to high voltages, such as AC mains. Violet + VRmk7

Rmk71

Qmk7

Zmk7 Rmk72

Cmk7 -

Figure 23

Grey

A Simple 0-10V/Mark 7 dimmer

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Vdim ≈

Vbe _ Qmk 7 Rmk 7 2

⋅ (VRmk 7 + Rmk 7 2 )

(22)

The ballast/driver will read the voltage different between violet and grey leads Vdim and control the light output. In Figure 24, the dimming curves are measured with the prototype at different case temperatures of -20, 25 and 70 °C and AUX fan loading. A standardized 0-10V dimming controller is used in the experiment and the driver outputs 100% when the diming voltage is larger than 8V and 10% when the dimming voltage is lower than 1V [3]. It demonstrates that the proposed topology and control scheme provide very stable and accurate output driving current with wide dimming range and temperature variations.

Figure 24

Experimental dimming performance with AUX loading at different operating temperatures

The measured efficiency of the Flyback stage with and without auxiliary loading is shown in Figure 25. 1.8W fan is used for the loading during efficiency measurement. For more than 15W output LED load power, the driver output current is 700mA with different number of LEDs. And for below 15W output power, the driver efficiency is measured with output current dimming.

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Without the auxiliary loading, the peak efficiency of the LED driver is ~92.1%, and with the 1.8W auxiliary loading, the peak LED power efficiency is about 4.9% lower at ~87.2%. It is worth noting that the 1.8W auxiliary loading (real power to the fan) is not included in the LED output power in the plot. So the efficiency drop, especially at low LED load power, is mainly due to this reason,

Efficiency (%)

and the actual total loss in the LED driver is not that much.

700mA with Different Number of LEDs

14 LEDs with Dimming

LED Output Power (W)

Figure 25 Measured efficiency output LED load power VS the overall input power with and without auxiliary loading (with 1.8W fan load)

VII.

CONCLUSION In this paper, a novel control scheme is introduced to regulate CC LED output and CV AUX

output at the same time for a Flyback based LED driver architecture. Using a nonlinear ramp signal, the main CC output is decoupled from the CV auxiliary output, so that LED flickering issue at dimming condition is completely resolved. Advantages of the proposed method are explained by building the small signal model. Based on the provided design guidelines, simulations and experimental results are presented to verify the proposed control scheme. Finally, experiments under steady state and auxiliary load transient confirm the effectiveness of the control scheme in the 40W dimmable LED driver with a 12V 3W AUX supply.

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APPENDIX The derivation of critical equations in this paper will be shown in more details in this section. A.

Derivation of tON in Equation (2) Equation (2) is derived from the power delivery from the inductance Lm in the Flyback

converter, where Ipk is the peak current of Lm and fsw is the switching frequency. 2

V  Po 1 1 1 = ⋅ Lm I pk 2 f sw = ⋅ Lm  in ⋅ tON  Pin = 2 η 2  Lm  tON + tdis + TR

(23)

tdis is the discharging time of the magnetizing current, which can be calculated in (24). And TR is the quasi-resonant duration, which can be found in (25).

tdis =

Vin tON n (Vo + VF )

(24)

TR = π LmCtot

(25)

Substitute (24) and (25) into (23), we can then obtain

 P  Vin P 1 Vin 2 ⋅ ⋅ tON 2 − o  + 1 ⋅ tON − o π LmCtot = 0 η  n (Vo + VF )  η 2 Lm

(

)

(26)

And the tON can be solved using equation (2) finally and only the positive solution will be taken. B.

Derivation of Id in Equation (7) Firstly, the current of the auxiliary load Ia is reflected to primary side when the main FET turns

on and the average value of this current Iap during on time can be found in (27) and geometry of the waveform is shown in Figure 26.

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= Ia

I ap ⋅ tON ⋅ na tON + tOFF

= ⇔ I ap

I a ( tON + tOFF ) tON ⋅ na

(27)

Ve IFB*Rsense Ip*Rsense

Iap*Rsense

Ia*Rsense

Id

PWM tON

tOFF

Figure 26 Waveform for derivation of (7) To calculate the average current Id, we can use (28) to obtain the peak of the IFB, IFB_pk in Figure 26 and then reflect this value to secondary side and average it over the switching period in (29).

I FB _ pk=

I (t + t ) Ve Ve − I ap= − a ON OFF Rsense Rsense tON ⋅ na

 Ve  − I ap  ⋅ n ⋅ tOFF  I FB _ pk ⋅ n ⋅ tOFF R  = I d =  sense 2 ( tON + tOFF ) 2 ( tON + tOFF )

(28)

(29)

Finally, we can substitute (27) into (29) and in order to simplify the equation in an explicit form without losing the insight of the coupling between Ia and Id, we assume in the (29), tOFF=tdis. However, in the Figure 16, we still consider the time duration TR, which is the difference between tOFF and tdis. C.

Derivation of Id in Equation (16) Using the nonlinear ramp proposed in this paper, the tON can be derived from (30).

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t − ON Rd 2 = Ve Vgd 1 − e Rs1Cs1    Rd 1 + Rd 2

(30)

Similar to the derivation of equation (7), we can obtain the peak of the IFB, IFB_pk on the primary side and calculate the average value of Id over a switching cycle on the secondary side as in (31).

 Vin  ⋅ tON  ⋅ n ⋅ tdis  I FB _ pk ⋅ n ⋅ tdis L  = Id =  m 2 ( tON + tOFF ) 2 ( tON + tdis + TR )

(31)

Substitute (24) and (25) into (31), we can obtain the equation (16).

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