2

3 FB15

16 19

CC CC

29

3

22 R49

100pF

160pF

1

B84

2

51

3

2

6

4

SDIO SCLK SEN*

IOUT_G+ IOUT_N+

PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]

IOUT_NIOUT_G-

49

DB2

JNO J4

2

2

46

3

3

45

RX+

38 B68

L7

240nH

270nH

270nH

B82

B69

0.1uF

B70

0.1uF

5

2

2

3

3

+

1

2

2

2

3

3

3

T1

4

0.1uF

0.1uF B91 RF2

10 R57

1

14 R60

T2

4

1

TXPAn

R58 10 TXSWbar

2

14 R61

3 1:1 Z

U10 B92

DB4

B89

R55 10

7

0.1uF

6 5 4

1 0

TXSW

U8B

PE4259

1 2 3

0.1uF

0.1uF B93

B

Vop

C45 10pF

1

0

1 2 3

10 R59

Vop/2

0.1uF

37

22 R50

0.1uF

4 DB3

RXCLK CLKOUT1

L5

1

50

J5 JNO

L3

3

-

1

TXSW

4

4 IOUT_P-

52

6 5 4

PE4259

R53 330

0.1uF

C43

0.1uF U8A

4

-

B88

R54 10

1

330 R52

75 R51

1K

150pF

1

C42

0.1uF

R44

B78

1K

10uF C28

C41

0.1uF B67

0.1uF

B90

OPA2677

+

A

U9

2

0.1uF

V-

IOUT_P+

RX-

330nH

C47 DNI 330nH

B85

0.1uF

2

B86

0.1uF

B87

0.1uF 1

3

PATRRX

TXTAP

3

RF1

Instrument RX

L8 C44

L9 C46

C48

100pF

180pF

100pF

5

1

TVS

4 DB5 D1

8:1 Z

4 C26 2

57

15pF 3

OSCIN

REFIO REFADJ

42 41

TX Build Options

1.6K

Switched instrument/PA TX: omit R56 R57 R58 R59 Only PA TX: omit FB15 FB16 B79 B80 R54 R57 R55 R59 U9 U10 R60 R61 T2 Only instrument TX: omit FB15 FB16 B79 B80 R54 R56 R55 R58 U9 U10 Termination is in two sections so power output to PA and instrument TX can be varied and dissipation split. Total termination for instrument TX should be 24 Ohms on each leg.

R40

1

X4

C

56 15pF C27

XTAL

AVDD_2 AVDD_1

AVDD 21

TP2

+3V3

B81

8

2.2K R46 L6

V+

RXSYNC TXSYNC TXQUIET*

U1B

RFFE_CLK

B77

DB1

38.4 MHz

FPGA

270nH

L4

TXSWbar

2

24 25 26 27 28 29

LS LS LS LS LS LS

REFB

270nH

L2

2

33 32

240nH

TXPAp

R56 10

Vop

8

20 22 23

LS LS LS

B

REFT

R48

2.2K R47

13 14 15

HS HS HS

Rx[5] Rx[4] Rx[3] Rx[2] Rx[1] Rx[0]

1K

R45

R43

7 8 9 10 11 12

HS HS HS HS HS HS

Tx[5] Tx[4] Tx[3] Tx[2] Tx[1] Tx[0]

Vop/2 1K

33 R41

1 2 3 4 5 6

HS HS HS HS HS HS

B83 0.1uF

0.1uF B80

75pF

A

0.1uF B79

65 31 34 36 39 44 47 48 55 18 63 59

C40

RESET*

FB16

33 R42

30

LS

EP AVSS_3 AVSS_2 AVSS_1 AVSS AVSS_6 AVSS_5 AVSS_4 CLKVSS DRVSS_1 DRVSS DVSS

5

TXSWbar

JNC J6

U7

V+

LS LS

4

TXSW

V-

1

53

10K R39

54

JNC J2

61

TP3

62

JNC J3

35 40

B71

B75

C31

C35

C37

0.1uF

0.1uF

1uF

1uF

10uF

FB19

RX Build Options

43

SDO

+3V3 B72

C29

C32

0.1uF

1uF

10uF

B73

C30

0.1uF

1uF

FB17

MODE CONFIG CLKOUT2 PWR_DWN

CLKVDD

DRVDD DRVDD_1 DVDD

AD9866BCPZ

PA TR switch RX: include B85 TX power tap sensing: include B86 Instrument RX: include B87 B85 B86 and B87 may all be concurrently installed provided at most one antenna is connected at a time. Clock Build Options

58

17 64 60

C

C33

FB18

10uF FB20

B66

B74

B76

C34

C36

C38

0.1uF

0.1uF

0.1uF

1uF

1uF

1uF

If RFFE_CLK supplied, omit C26 C27 X4 C26 C27 X4 only if layout allows as option for inexpensive local clock with worse phase noise.

C39 10uF

KF7O Steve Haynal SofterHardware Sheet: /RF Frontend/ File: RFFrontend.sch

D

Op Amp Design by Jim N2ADR TX Filter Design by Claudio IN3OTD/DK1CG RX Filter Design by Andrew G4XZL

D

Title: RF Frontend Size: USLetter Date: 2016-07-03 KiCad E.D.A. kicad 4.0.1-stable

1

2

3

4

Rev: 2.0-pre2 Id: 5/6 5

Title: RF Frontend -

If RFFE_CLK supplied, omit C26 C27 X4. C26 C27 X4 only if layout allows as option for inexpensive local clock with worse phase noise. Clock Build Options.

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