IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 10, OCTOBER 2004

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Timing Extraction of a 10-Gb/s NRZ Signal Using an Electrooptic Multiplication Scheme E. Shumakher, A. Hayat, A. Freimain, M. Nazarathy, Member, IEEE, and G. Eisenstein, Fellow, IEEE

Abstract—We report a new scheme for timing extraction of a 10-Gb/s nonreturn-to-zero signal. The scheme uses electrooptical multiplication of the optical signal by its delayed electrical replica in a Mach–Zehnder modulator. The modulator output injection locks an oscillator whose output is a high-quality 10-GHz clock used to synchronize a bit-error-rate (BER) measurement receiver. The quality of the clock signal depends on the modulator nonlinearity which is controlled by its dc bias and the delay between the two multiplied signals. BER performances with the extracted clock signal were found to be essentially identical to measurements with a clock from the BER system, proving the high quality of extracted timing signal.

II. RESULTS The new timing extraction system is shown schematically in pseudorandom binary sequence input Fig. 1. A 10-Gb/s NRZ signal is split in an asymmetric directional coupler with the 90% port feeding a LiNbO Mach–Zehnder modulator through a tunable delay line. The signal at the 10% port is detected while the electrical signal is split between the BER tester and (following amplification) the RF input of the modulator. The modulator multiplies the NRZ optical signal by its delayed electrical replica making use of its electrooptic transfer function

Index Terms—Injection-locked amplifiers, optical processing, timing circuits.

(1)

I. INTRODUCTION

T

IMING extraction is a key function in any digital receiver. Several optical and electrooptical techniques have been demonstrated [1], [2] for timing extraction in high bit-rate fiberoptic communication systems operating with the RZ modulation format. A return-to-zero (RZ) signal contains a spectral component at the bit-rate frequency [called the clock frequency component (CFC)] which is used to lock the clock oscillator. For data sequences using the nonreturn-to-zero (NRZ) format, no such signal is, in principle, available. Imperfect NRZ modulation and signal distortion due to dispersion result in some CFC however, reliable sampling requires enhancement of such CFC at the receiver. This is achieved by some form of preprocessing, transforming the NRZ sequence into a pseudo-RZ (PRZ) [3] signal that contains a strong CFC. The most common processing procedure involves a multiplication of the signal by its delayed replica, which can be implemented by a variety of optical means such as cross-gain modulation in an optical amplifier [4] or four-wave mixing in a nonlinear fiber [5]. This letter describes a new timing extraction scheme for NRZ signals, employing electrooptic multiplication to generate the required CFC. Due to the limited bandwidth of any practical system, CFC generation is possible even for an ideal (zero rise time) NRZ input signal. The CFC serves to injection lock a clock generator which is then used to synchronize the receiver of a bit-error-rate (BER) tester.

Manuscript received April 5, 2004; revised June 25, 2004. The authors are with the Electrical Engineering Department, Technion-Israel Institute of Technology, Haifa 32000, Israel (e-mail: [email protected]). Digital Object Identifier 10.1109/LPT.2004.834507

where is the modulator bias and denotes normalized optical intensity. The modulating signal was amplified and offered a . The modulator output is a PRZ signal whose swing of detected spectrum contains an enhanced component at the bitrate frequency. The input polarization was set to maximize the modulation efficiency using a polarization controller. Two degrees of freedom, the tunable delay and the modulator bias, control this clock signal. Fig. 2(a) describes the results of a calculation of the signal-to-noise ratio (SNR) of the CFC at three bias levels as functions of delay, characterized in terms of fraction of the bit-slot duration. Operation in the vicinity of the quadrature point yields a large SNR for small delays where the same bit is fed into both arms of the modulator yielding classical NRZ-to-PRZ translation with a strong CFC and, hence, a large SNR. For large delays, however, the probability of multiplying two bits of opposite value increases causing a deterioration of the average CFC level leading to a low SNR. The observed fluctuations at large delays show a periodicity of one bit slot and represent correlations or anticorrelations among the multiplied components. In or ) contrast, operation at an extremum point ( results in a high-quality CFC signal with a large, and delay-independent, SNR, as seen in Fig. 2(a). The 5-dB SNR drop near 1–2 bit-slot delay is caused by a reduced contribution of direct multiplication which stems from the extension of the modulating voltage swing to the vicinity of the quadrature. The origin of CFC generation can also be understood heuristically by noticing that the lack of CFC in an ideal NRZ spectrum is due to the spectral null of the Fourier transform of a time do, where is the bit rate). main square signal ( (for ) are The frequency components at nonzero, however. Therefore, a mixing process between these components can produce a CFC at exactly the frequency ,

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IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 10, OCTOBER 2004

Fig. 1. Experimental setup.

Fig. 2. Dependence of CFC on the relative delay in bit-slot fractions. (a) Calculated SNR for three biasing levels. (b) Measured CFC power for maximum transmission bias.

thereby creating the seed for synchronization. The nonlinear beor havior of the modulator when biased at causes that mixing process while when biased at quadrature, the modulator is almost linear. Fig. 2(b) describes measured CFC power for a bias of and a range of delays. Some fluctuations (with a repetition of one bit slot) are apparent but the CFC is always large. The fluctuations resemble the behavior of the modulator when biased

Fig. 3. CFC SNR versus normalized bias voltage: (a) calculated (b) measured.

at quadrature , hence, we conjecture that some portion of the generated CFC is actually due to classic half-bitshift multiplication. The second degree of freedom controlling the CFC signal is the modulator bias. Fig. 3(a) depicts calculated SNR values as a function of bias for a delay of ten bit slots. It is clearly seen that the SNR is periodic, reaching a maximum at zero bias and at multiples of . The calculation shown in Fig. 3(a) was convalue of firmed by an experiment described in Fig. 3(b). The the modulator used was 2.9 V.

SHUMAKHER et al.: TIMING EXTRACTION OF A 10-Gb/s NRZ SIGNAL USING AN ELECTROOPTIC MULTIPLICATION SCHEME

Fig. 4.

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Measured CFC for different bias levels. Fig. 5. Measured BER performance.

Fig. 4 compares measured clock signals for three modulator bias levels versus the frequency offset relative to 10 GHz. At both extremum points, the SNR is 60 dB, whereas, at quadrature, it decreases to 12 dB. The displayed power spectra were measured with a video bandwidth which was smaller than that used for extracting the data in Figs. 2 and 3 and, therefore, the SNRs are not to be compared. Fig. 4 is only meant to compare qualitatively the CFC dependence on bias. The results are consistent with the tendencies predicted by Fig. 3(a) and measured in Fig. 3(b). The CFC quality dependence on bias is summarized in Fig. 3(b) which shows measured SNR for all bias levels. The . The measurement SNR peaks are separated at precisely exhibits a positive bias offset of about 1 V which is attributed to a long-term bias shift, common to LiNbO devices. The measured SNR results confirm the prediction of Fig. 3(a). To further characterize the timing extraction scheme, we performed BER measurements as a function of the input power to the system and compared them to BER measurements with a clock from the BER system. As the input power is reduced, the modulator output decreases, narrowing the injection-locking range but having no effect on the quality of the clock as long as the clock oscillator remains locked. The timing extraction scheme used optimized bias conditions and the comparison is shown in Fig. 5. A small penalty of 0.5 dB, at most, is observed, establishing that the extracted clock practically adds no jitter and can indeed be used for timing recovery of a 10-Gb/s NRZ signal.

III. CONCLUSION We have demonstrated a new technique for timing extraction of high bit-rate NRZ data. The scheme generates a clock signal by electrooptically multiplying the optical NRZ signal by its delayed electrical replica. The extracted clock quality was established by a BER measurement at 10 Gb/s.

REFERENCES [1] K. Murata, K. Sano, T. Akayoshi, N. Shimizu, E. Sano, M. Yamamoto, and T. Ishibashi, “Optoelectronic clock recovery circuit using resonant tunneling diode and uni-travelling-carrier photodiode,” Electron. Lett., vol. 34, no. 14, pp. 1424–1425, 1998. [2] R. Ludwig, W. Pieper, A. Ehrhardt, E. Jahn, N. Agrawal, H.-J. Ehrke, L. Kuller, and H. G. Weber, “40 Gb/s demultiplexing experiment with a 10 GHz all-optical clock recovery using a modelocked semiconductor laser,” Electron. Lett., vol. 32, pp. 327–328, 1996. [3] H. K. Lee, J. T. Ahn, M.-Y. Jeon, K. H. Kim, D. S. Lim, and C.-H. Lee, “All-optical clock recovery from NRZ data of 10 Gb/s,” IEEE Photon. Technol. Lett., vol. 11, pp. 730–732, June 1999. [4] A. Bilenca, D. Dahan, J. Lasri, G. Eisenstein, and D. Ritter, “High bit rate clock recovery of NRZ data by all-optical processing in a semiconductor optical amplifier and direct optical injection locking of a self-oscillating phototransistor,” IEEE Photon. Technol. Lett., vol. 14, pp. 399–401, Mar. 2002. [5] A. Bilenca, D. Dahan, J. Lasri, and G. Eisenstein, “All-optical processing by fiber delay and four-wave mixing of high-bit-rate nonreturn-to-zero signals for timing extraction by optical injection locking,” IEEE Photon. Technol. Lett., vol. 14, pp. 852–854, June 2002.

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multiplication of the optical signal by its delayed electrical replica ... site value increases causing a deterioration of the average CFC level leading to a low SNR.

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