Materials Science Forum Vols. 556-557 (2007) pp 847-850 online at http://www.scientific.net © (2007) Trans Tech Publications, Switzerland Online available since 2007/Sep/15

Time Dependent Trapping and Generation-Recombination of Interface Charges: Modeling and Characterization for 4H-SiC MOSFETs S. Potbhare1, a, N. Goldsman1, b, G. Pennington1, c, A. Lelis2, d and J.M. McGarrity3, e 1

Department of Electrical Engineering, University of Maryland, College Park, MD 20742, USA 2

U.S. Army Research Laboratory, 2800 Powder Mill Road, Adelphi, MD 20783, USA 3

Berkeley Research Association, Springfield, VA 22150, USA

a

[email protected], [email protected], [email protected], [email protected], e [email protected]

Keywords: Interface traps, Capture/emission time constants, Generation-recombination

Abstract. SiC MOSFETs have very large interface trap densities which degrade device performance. The effect of traps on inversion layer mobility and inversion charge concentration has been studied, and mobility models suitable for inclusion in Drift-Diffusion simulators have been developed for steady state operation of SiC MOSFET devices. Here, we attempt to model the transient behavior of SiC MOSFETs, and at the same time, extract the time constants for the filling and emptying of interface traps. As compared to the inversion layer, interface traps in SiC MOSFETs are slow in reacting to change in gate bias. So, at the positive edge of a gate pulse, we see a large current in the MOSFET, which then decays slowly to the steady state value as the interface traps fill up. We have developed a generation/recombination model for minority carriers in a SiC MOSFET based on the Shockley-Read-Hall recombination model for electrons and holes. In our model, the generation/recombination takes place between minority carriers in the inversion layer, and the traps at the SiC-SiO2 interface. Comparing our simulated current vs. time curves to experiment, we have been able to extract time constants for the filling and emptying of traps at the SiC-SiO2 interface. Introduction In steady state operation of SiC MOSFETs, occupied interface traps cause mobility degradation and reduction in mobile charge in the inversion layer, thereby lowering current and degrading device performance [1-4]. In MOSFET switching applications, the rate at which the interface traps can be filled and emptied will affect the transient response of the device and also pose stability concerns. Here, we describe how we characterize the transient behavior of SiC MOSFETs, and discuss how to extract time constants for the filling/emptying of interface traps. Our method combines measurements with detailed numerical device modeling. We introduce a generation-recombination model for carriers in the semiconductor that can occupy the interface traps, and thereby obtain a time dependent trap occupation model. These are incorporated in our drift diffusion simulator for SiC MOSFETs [5]. Simulated transient characteristics are compared with experiment to extract trap physics. Time Dependent Trapping and Generation-Recombination Model The occupation of traps at the interface of a SiC MOSFET can be thought of as recombination of a mobile carrier in the semiconductor with an empty trap state at the interface. Similarly, emission of an electron from a trap will cause a generation event in the semiconductor. Thus, this generationrecombination process is a single carrier process. In the case of filling/emptying of the interface traps, there is a net shift in charge from the semiconductor to the interface, or vice-versa. An initial net non-zero generation-recombination rate takes a finite time to become zero and reach steady state, giving a constant occupied trap density and mobile charge concentration.

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Our generation-recombination model is analogous to SRH recombination [6], but it involves only one type of carrier. We write the generation-recombination rate for electrons inside the semiconductor due to trapping/de-trapping by different types of interface and near-interface traps. Inside the semiconductor p-type region of a n-channel MOSFET, at a time t, the rate of recombination of electrons at (x, y) in a small volume dy will be proportional to the number of unoccupied traps at (x, 0) and the number of electrons at (x, y)

[

]

R i ( x, y, t ) dy = κ Ri N iti Total − N iti (x, t ) n(x, y, t ) p( y )

(1)

where, R i ( x, y, t ) is the recombination rate for electrons due to interaction with the ith type of traps,

n( x, y, t ) is the electron concentration, N iti Total is the total density of the ith type of traps, and N iti ( x, t )

is the occupied ith type trap density. The element dy transforms the 3D recombination process to a 2D interface trap occupation process. κ Ri is the average of the product of the thermal velocity (vth) and the capture cross-section area of the ith type of interface (or near interface) trap. p( y ) is the probability for an electron at a depth y to reach the interface. Similarly, at time t, the generation of electrons at position (x, y), due to emptying of traps will be proportional to the number of occupied traps at (x, 0) and number of free electrons states at (x, y).

Gi ( x, y, t ) dy = κ Gi Niti ( x, t ) [N c − n( x, y, t )] p( y )

(2)

where, G i ( x, y, t ) is the generation rate for electrons at (x, y) at time t, κ Gi is the average of the product of the thermal velocity (vth) and emission cross-section by the ith type of trap, and NC is the total electron density of states in the semiconductor. The total net recombination rate at any location (x, y) inside the semiconductor due to all the different types of traps is then given as

R Net (x, y, t ) = ∑ [R i (x, y, t ) − G i (x, y, t )]

(3)

i

The net recombination term becomes a part of the electron current continuity equation in the drift diffusion scheme. The occupation of the ith type of traps at a time t+∆t is written as

N iti ( x, t + ∆t ) = N iti (x, t ) + ∆t ∫  R i ( x, y, t ) − G i ( x, y, t ) dy y   

(4)

Experiment

We carried out transient measurements on a 424µm×5µm n-type 4H-SiC MOSFET with a gate oxide thickness of approximately 50nm. The threshold voltage for the MOSFET was approximately 2 V. The gate of the MOSFET was pulsed from 0V to 5 V while holding the drain at 4 V and the source grounded. This ensured that the MOSFET was operating in saturation at all times. The rise time of the pulse was 100ns. Fig. 1 shows the drain current that was observed when a pulse was applied at the gate. We can see a large initial transience and then the current keeps on decreasing at different rates till it reaches a steady state value of around 415µA. From the experiment we were able to measure several time constants for the current decay, from as low as 1µs to as high as several tens of milliseconds. These different time constants suggest the presence of a large number and different types of interface, near-interface and oxide traps in the 4H-SiC MOSFET device. Fig. 2 shows the current immediately after the gate pulse was applied. After accounting for the intrinsic capacitance (Cint = CoxWL=1.4634 pF) device, and the associated time constant (τint=CintRD=1.4634 ns) of the circuit, we can say that this transient behavior is due to the gradual filling up of the near interface traps. Simulation

From our steady state model and simulation [5], we first extracted the interface trap density of states for this particular device, with a mid-gap value of 1.26×1011 cm-2eV-1 and a band-edge value of

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Fig. 1. Transient drain current observed in the Fig. 2. Drain current observed immediately after experiment when a fast gate pulse was applied to the applying the gate pulse. The slow decay in current indicates the slow filling of near-interface traps. 4H-SiC MOSFET.

7.6×1013 cm-2eV-1 as shown in Fig. 1. This gives us the total density of interface traps as 5.6×1012 cm-2. Using the new generation-recombination model and the time dependent trapping model we simulate the dynamics of the interface and near-interface traps. We have considered two types of traps, with two different capture and emission cross-section areas, to model the initial transient characteristics of Fig. 2. One type of trap is a fast interface trap, which responds at a rate comparable to or faster than the rise time of the applied gate pulse (100ns). The other type of trap is a near-interface trap that is slower to react to the applied pulse and is responsible for the initial transient behavior. Experiments show that there are many other types of near-interface and oxide traps which react much more slowly. We simulated MOSFET operation for a 0-5V gate pulse with a 100ns rise time, the drain at 4V, and source grounded. On application of the gate pulse, there is a sudden increase in the inversion layer charge concentration. But as the near-interface traps are slow to react, the occupied trap density does not reach its steady value corresponding to VGS = 5V instantaneously. Hence, an initial increase in the channel current (Fig. 4) is seen. Then, as the near-interface traps get occupied, the total inversion charge decreases and reaches steady state (Here steady state implies the steady current seen right after the initial transience as shown in Fig. 2). The change in occupied nearinterface trap density, and the change in inversion charge with time are shown in Fig. 5. The peak current is limited by the number of fast interface states that get occupied as the gate voltage rises. The number of slow near-interface states and their capture cross-sections give the decay in the current. Also, the final steady state current is determined by the ratios of the capture and emission cross-sectional areas of the traps, as shown in Fig. 6. The larger is the emission cross-

Fig. 3. Interface trap density of states extracted from Fig. 4. Simulated transient characteristics for a 4Hcomparing steady-state simulations to experiment. SiC 424 µm × 5 µm MOSFET at room temperature.

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Fig. 5. Slow near-interface trap density and inversion charge varying with time. Slowly rising trap density with time causes a slow decay in the inversion charge density, and hence a decay in the drain current.

Fig. 6. Steady state current depends upon the ratio of emission and capture cross sections. Larger κG/κR ratio implies larger steady state current.

section, the lesser is the steady state trap occupancy, and hence, the higher is the steady state current. Analysis We compare simulation (Fig. 4) to experiment (Fig. 2) to extract trap dynamics. The agreement between simulated and measured peak current gives us an estimate of the number and capture crosssection of the fast interface states, whereas the conformity of the rate of decay of the current gives us the number and cross-section area of the slower near-interface trap. Simulations indicate that the fast interface states have a κR of approximately 1×10-10 cm3/s corresponding to an approximate cross-sectional area of 5×10-16 cm2. The slower near-interface traps responsible for the decaying current, have a κR value of 2×10-13 cm3/s and cross-sectional area of approximately 1×10-18 cm2. We also see that for the gate voltage of 5V, more than 90% of the total occupied traps are the fast interface trap states. Conclusion A single carrier generation-recombination model for recombination of minority carriers with interface trapped states, and a time dependent trapping model have been proposed for 4H-SiC MOSFETs. Simulations show a sharp increase in channel current on application of a gate pulse to a SiC MOSFET. This sharp increase is due to fast increase in minority carriers and slow response of interface traps. Comparison of simulation with experiment has been done and the model is validated qualitatively. Experiments show that trapping time constants for interface and near interface traps in 4H-SiC MOSFETs can be as large as several microseconds, and those for oxide traps can be several seconds. References [1] N. S. Saks and A. K. Agarwal: Appl. Phys. Letters Vol. 77 (2000), p. 3281 [2] N. S. Saks, S. S. Mani, and A. K. Agarwal: Appl. Phys. Letters. Vol. 76 (2000), p. 2250 [3] H. Yano, T. Kimoto, and H. Matsunami: Appl. Phys. Letters Vol. 81 (2002), p. 301 [4] S. Potbhare, G. Pennington, N. Goldsman, J. McGarrity, and A. Lelis: Proc. of SISPAD (2005), p. 95 [5] S. Potbhare, G. Pennington, N. Goldsman, J. McGarrity, and A. Lelis: (to be published) J. Appl. Phys. Vol. 100, (2006) [6] W. Shockley and W. T. Read Jr.: Phys. Rev. Vol. 87 (1952), p. 835

Materials Science Forum Vols. 556-557

Silicon Carbide and Related Materials 2006 doi:10.4028/www.scientific.net/MSF.556-557 Time Dependent Trapping and Generation-Recombination of Interface Charges: Modeling and Characterization for 4H-SiC MOSFETs doi:10.4028/www.scientific.net/MSF.556-557.847

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