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The Next Generation of Sensor Node in Wireless Sensor Networks S.Charoenpanyasak and W.Suntiamorntut Abstract—Wireless sensor networks are widely used in data gathering applications from the environmental to the health care system. This type of networks composes of a large amount of tiny and cheap devices called node. The challenge of node development is posed for designer such as energy usage, processing power, memory size and sensing capability. The original node architecture has been developed for many years. It consists of microcontroller, memory, radio module and sensing unit. Wireless sensor network applications become more complex and more computing-intensive. The existing node may not be a good choice for a battery-limited device likes sensor node. This paper presents a survey of modern sensor nodes. We suggest the next generation of sensor node based on the dynamically partial reconfigurable hardware. Index Terms—Wireless sensor network, Dynamic Partial Reconfigurable, FPGA.
IRELESS sensor networks (WSNs) have been developed and used widely in many fields such as health care, agriculture and environment. In a medical field, each sensor for example blood pressure or EKG has been attached on the patients’ body. The observation system will report the signals to the hospital when some parameters are altered . In an environment domain, the researcher deployed wireless sensor network in the forest fire detection system. The neural network was applied to provide a higher accuracy . Additional, the precision agriculture monitoring system also employed wireless sensor network technology to monitor the agricultural environment of plants. The data was used improved the crops’ productivity . Wireless sensor network may consist of hundreds or thousands of nodes depend on its applications. The large amount of sensor nodes in the field makes a difficulty of battery replacement. Therefore, energy efficiency is an important key for the research challenges. The typical node architecture consists of processing unit, memory, sensor, battery and radio communication device. The sensed information is processed locally by a small processing unit whilst the results, data and software are kept in memory unit. Node may contain several types of sensing device such as temperature, light and pressure sensors depending on it applications. Energy storage in sensor node is very small. Thus the effective power salvaging as solarcell is considered to attach on sensor node. Finally, each node can form a network to communicate wirelessly using short-range radio module ————————————————
• S.Charoenpanyasak is with the Department of Computer Engineering, Faculty of Engineering, Prince of Songkla University, Hatyai, Songkhla, Thailand 90112. • W.Suntiamorntut is with the Department of Computer Engineering, Faculty of Engineering, Prince of Songkla University, Hatyai, Songkhla, Thailand 90112.
corresponding to IEEE 802.15.4 standard. Reconfigurable computing  has been introduced in wireless sensor network in order to increase the computation-intensive and flexibility in a sensor node. The examples of using reconfigurable device in WSNs are found in multimedia , signal processing, security and adaptive networking applications. In this paper, we summarize the state of the art in hardware development using reconfigurable computing. The potential of combining reconfigurable platform in sensor node for an energy efficient purpose and the research challenge are discussed. The rest of the paper is organized as follows. We describe the typical sensor node architecture and the existing node platforms in Section 2. The existing reconfigurable sensor nodes are illustrated in Section 3. The opportunity to employ the next generation of sensor node based on a run-time reconfigurable hardware called Dynamically Partial Reconfiguration (DPR) is discussed in Section 4. The existing dynamically reconfigurable node is introduced in Section 5. Finally, the conclusion is drawn in Section 6.
2 TYPICAL SENSOR NODE ARCHITECTURE 2.1 Node Architecture The traditional architecture of sensor node is shown in Fig.1. Processing unit performs only necessary computation. Tiny and low power microcontroller is usually chosen due to its power saving. However, in some applications as multimedia or security, the system may require a powerful processing unit to execute the complex tasks. The reconfigurable hardware is thus considered to accelerate the computing.
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Fig. 1. The traditional architecture of sensor node.
A memory is normally embedded on microcontroller to keep both data and program. However, some additional external memory may be required to collect the sensed data. A communication module will help node to form a network. Therefore, network protocol development is necessary in sensor node. By using a radio transceiver, node can transmit the data wirelessly based on IEEE 802.15.4 standard. The last module in node architecture is power supply. Node is powered by a battery which may need energy scavenging techniques in some cases. The choice of processing unit implementation depends on the applications and the result of processing unit selection will also dominate to the choice of memory size. We can conclude the possible processing unit as follows. 1. Microcontroller offers a small size, low cost, low power and programming flexibility. It is suitable for low intensive computing applications. Normally, it can be programmed with assembly or C language. 2. Digital Signal Processor (DSP) is more powerful than microcontroller, especially in numerical computation. Therefore, DSP is a good choice for multimedia and signal processing WSN applications. DSP can help to improve the transmission signal due to noise or interference problems. 3. Application-Specific Integrated Circuit (ASIC) can provide ultra low power node and optimal cost when the mass production is made. However, it spends too much time to design and it is not flexible. 4. Field Programmable Gate Array (FPGA) gives the most flexible in its application compared to other processing units. FPGA also supports parallel processing. Unfortunately, it is difficult to program FPGA device.
2.2 Existing Sensor Nodes We survey the existing sensor nodes both in-house and commercial platforms. Most sensor nodes were introduced around 2005. We classify sensor node by the ability of microcontroller and its functionality into two categories; small scale node and medium scale node. The small scale node uses low-power microcontroller running at the frequency less than 16 MHz. The medium scale node operates more than 16 MHz. A small node usually is used to sense the physical environment and forward data to base station or cluster head. Only a simple processing such as data rearrange-
ment is performed on sensor node. A little size of memory is needed because there is no need to store the data locally. This type of sensor node is low-power and low cost. Thus we can deploy a large amount of node in the field. First example of small node is XYZ node  designed for educational projects and experimentation. The node is 2 x 2 inch2 in size and consists of OKI ARM ML67Q500x and CC2420. The commercial node named Mica  used RFM TR1000 has been proposed in 2002. Then later, Mica2 was proposed follow on the Mica platform by replacing MCU with ATmega128. The last generation of Mica platform is MicaZ  which CC1000 was replaced with CC2420. The famous low power node platform is Telos  composed of ultra low power MSP430f1611 microcontroller and CC2420. The ultra low power and tiny node is Eco  only 12 x 12 mm2. This node used embedded 8051 compatible (DW8051) and nRF24E1. The final example is S-Mote  which has only System-On-Chip CC2430-F128 working together with sensing board. A medium node is more powerful than a small node due to its complicated processing such as signal or image processing. This node may be used as a cluster head collecting the data from neighbor nodes before it will forward the whole pack of data back to base station. Therefore, some external memory is required. In some applications, this type of node will be a gateway connecting to another networking likes internet. Intel Mote or iMote  was first introduced in 2005 using wireless ARM7 core named Zeevo, Bluetooth radio and running on TinyOS. SunSPOT  uses a powerful microprocessor which can run Java, 6LowPan and AODV. Therefore, SunSPOT has been encouraged to develop several new wearable applications such as PDAs, smart phone and MP3 player.
3 THE EXISTING RECONFIGURABLE SENSOR NODES The classic WSNs node was made by microcontroller. This generation of node made the applications restricted. The reconfigurable sensor node is therefore introduced to expand the application domains. This type of node also reduces time-to-market. Even the FPGA of reconfigurable node consumes more power than microcontroller, it gives a good efficient processing in an image applications. The example of FPGA node used in the image processing domain was presented in . It was developed for surveillance systems to detect the intrusion. Whilst the FPGA based image processor was proposed in  aiming for sensor nodes in WSNs. This processor can operate template matching method and background subtraction method for target tracking and object extraction, respectively. Another example is the development of FPGA-based sensor node in signal processing domain. Research work in  proposed the reconfigurable smart sensor for Computer Numerically Controlled (CNC) machine monitoring. This FPGA node helps to perform complex signal-
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processing, sensor interface and network protocol. By computing on sensor node, the amount of data sent through the wireless network has been reduced. Security is a key important for wireless sensor networks, especially in health care monitoring and military applications. Data is required to be encrypted on node before sent out wirelessly. This leads to increase more constraints of sensor node. Due to the encryption process has to be quick and not affect to the real-time system. Moreover, it should not consume too much power consumption. In , the authors introduced the hyperchaos encryption based on FPGA with the wide application on wireless sensor networks. The transported data has been encrypted in the network using FPGA node.
THE NEXT GENERATION OF SENSOR NODE USING A RUN-TIME RECONFIGURABLE HARDWARE
A run-time reconfigurable hardware is an advance research topic in the reconfigurable computing. The reconfigurable device can be configured at the run-time or called Dynamically Reconfigurable System which changing hardware construction during operations. Currently, only Xilinx and Atmel FPGA have this feature that can update the hardware at run-time and at anytime in some part of its device, some called Dynamically Partial Reconfigurable system. Partially reconfigurable FPGA allows their logics modified at run-time without affect the running logics. For such system, an application is divided into small tasks called hardware tasks. Hardware tasks run concurrently on the FPGA. When a task finishes execution, the system removes it from the FPGA and its area can be relocated and reused by incoming tasks. This feature can give energy and area efficiency in WSNs due to only necessary hardware module is activated on sensor node. Therefore, the run-time reconfiguration in WSNs can be valided by the next generation of sensor node using dynamically reconfigurable device. It allows the sensor nodes in WSNs can be tuned, debuged and reconfigured remotely. The large number of sensor nodes has been deployed in the field and the sensing objects can be moving around. Thus the network topology is frequently changed. To have the best efficient data gathering and communication, smart node has to be adaptive both in processing unit and networking protocol using dynamic partial reconfiguration technique. It also allows the sensor network to be adapted the different key size of security algorithms corresponding to the applications or energy budget. A modern FPGA contains both hardcore processor and reconfigurable circuits on a single chip. Processor inside FPGA will be used to communicate with RF module and reprogram the reconfigurable circuits by uploading the bitstream from the memory.
Fig. 2. Next generation of sensor node architecture.
The next generation of sensor node architecture has been shown in Fig.2. The existing modern FPGA device can support the proposed architecture whereas the radio module is widely sold in the market. Thus the developing time is very short and the cost is low. Inside FPGA, we can choose between microcontroller and processor as a main control unit which may or may not apply embedded operating system. Microcontroller or processor takes responsibilities to get the physical data from various sensors such as temperature or camera. After the data has been processed, microcontroller or processor can forward the results to another nodes or based-station via radio module. If some job or task requires an intensive computing, the controller can reprogram the configuration memory to form the new suitable logic circuits inside the reconfigurable hardware area. This changing will not affect to another processing inside the microcontroller. In addition, the user can send a new configuration via the radio module to reprogram the reconfigurable hardware remotely. The next generation of sensor node proposed in this paper, is practical to implement and be deployed in wireless multimedia sensor networks. The applications which concerned to security or adaptive protocol are strongly recommended to use this sensor node architecture.
5 THE EXAMPLE OF RUN-TIME PARTIAL RECONFIGURABLE SENSOR NODES
The example of the partial reconfigurable wireless sensor node called Cookie can be found in . The Cookie used 8052 microcontroller and Xilinx Spartan XC3S200 as a processing unit. The microcontroller is connected to FPGA via JTAG port for a remote reconfiguration purpose. Zigbee ETRX2 (Telegesis) is the communication module and controlled by microcontroller. Cookie node has various sensors such as acceleration, temperature, humidity, light, infrared and deformation to measure the environment. Another example is a new generic node platform using dynamically reconfigurable hardware for wireless sensor networks proposed in . This node is different from the previous example at the run-time partial reconfigurable area. In this research work, they proposed reconfigurable function unit (RFU) which was combined into 32-bit
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LEON2 RISC processor. This RFU has a heterogeneous datapath suitable for WSNs domain. The processor will run system control and control-domimated tasks whilst RFU will perform data processing. Therefore, this node is a coarse-grained reconfigurable hardware. The hardware modules are formed corresponding to the incoming instructions.
6 CONCLUSION We can achieve energy and flexibility improvement when the dynamic partial reconfigurable device is used in wireless sensor network. This changeable hardware at runtime increases the capability of wireless sensor network applications. Therefore, the dynamic partial reconfigurable device is key technology in the next generation of wireless sensor node.
ACKNOWLEDGMENT The authors would like to thank Centre of Excellence in Wireless Sensor Network, CoE-WSN, funded by NECTEC, NSTDA Thailand.
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S. Charoenpanyasak received the MEng degree from Prince of Songkla University, Thailand and the PhD degree from Institute National Polytechnique of Toulouse (INPT), France. During 20042005, she did a joint collaborative research project with Network Excellent in Wireless Communications (NEWCOM) in Europe. She is currently a lecturer at the department of computer engineering, Prince of Songkla University, Thailand. Her current areas of research are Wireless networks, Algorithm design, Cross layer for MANETs and Routing protocols for Wireless ad hoc and sensor networks. W. Suntiamorntut received the Ph.D Degrees from the University of Manchester, UK. She was a research assistant at the School of Computer Science, the University of Manchester for 3-year, during she was doing the Ph.D. program. Since 1999, she was a lecturer at computer engineering department at Prince of Songkla University, Hatyai Thailand. During her scientific activities, she has published more than 40 papers in IC design and wireless sensor networks. In 2008, she became the Director of Collaborative Research Unit in Wireless Sensor Network (CRU-WSN), a joint collaboration between National Electronics and Computer Technology Center and Prince of Songkla University. She is currently an assistant professor of computer engineering department at Prince of Songkla University.