USO0RE38134E
(19) United States (12) Reissued Patent
(10) Patent Number: US (45) Date of Reissued Patent:
Ross et al. (54)
(75)
SYSTEM FOR COMMUNICATIONS WHERE FIRST PRIORITY DATA TRANSFER IS NOT DISTURBED BY SECOND PRIORITY DATA
RE38,134 E Jun. 3, 2003
5,546,392 A 5,574,911 A 5,699,345 A
* 8/1996 Boal et a1. ................ .. 370/395 * 11/1996 D’Angelo et a1. ........... .. 707/1 * 12/1997 Watanuki et al. ......... .. 370/232
5,761,445 A
*
6/1998
Nguyen .................... .. 710/100
gggggggggqg gggggggggggm
5,799,002 A
*
8/1998
Krishnan e. . . . . .. . . .
. . . .. 370/234
PROCESS TERMINATES ABNORMALLY
5,805,821 A
*
9/1998 SaXena et al. ..
709/231
5,956,509 A
*
9/1999
Inventorsi Patrick Delaney R988, Sunnyvale, CA
K
..................... .. 709/304
5,991,308 A * 11/1999
(US); Bradley Davld Strand, Los Gatos, CA (US); Dave Olson, Palo
6,222,856 B1 * ' '
Alto, CA (US); Sanjay Singal,
et a1. ........ .. 370/474
4/2001 Krishnan 61 al. ......... .. 370/464
* Clted by examlner
Mountain View, CA (US)
_
Primary Examiner—]effrey Gaf?n Assistant Examiner—Tanh Nguyen (74) Attorney, Agent, or Firm—Schwegman, Lundberg,
(73) Assignee: Silicon Graphics, Inc., Mountain View, CA (Us)
Woesnner & Kluth, PA.
(21) Appl. No.: 09/679,447
(57)
(22)
The present invention comprises a method and system for implementing prioritized communications in a computer
R .
Filed:
Oct‘ 3’ 2000
f Related US‘ Patent Documents
6215511; 2 ' t N _
( ) I a end 0"
system having a microprocessor and a plurality of peripheral
J’
devices coupled to the computer system. The system of the
un'
’1 1999 ’
present invention determines a ?rst priority level and deter
08/805,991
F1 d_
.
F b 2 4 1997
1 e '
(51)
system. The present invention is implemented on a computer
5 909 59 4
Ssue ' Appl. No.:
e '
(58)
.
.
mines a second priority level. The system of the present
’
invention receives a bandwidth allocation request from a
Int. c1.7 ......................... .. G06F 13/14; G06F 3/06;
software process to transfer data at the ?rst priority level
G061? 11 /()()~, G061? 13/()0
(52)
ABSTRACT
between two or more P eriP heral devices. The s Ystem sub
us. Cl. ........................... .. 710/20; 710/21; 710/29;
Sequen?y allocates a ?rst Priority data transfer bandwidth
710/32; 710/36; 710/40; 710/117; 370/232;
between the devices in response to the request and performs
370/235; 709/235 370/229 232
465. 71’0/20’
a ?rst data transfer between the devices using the ?rst priority data transfer bandwidth. In addition, the system of the present invention performs a second data transfer
21 29’ 32 36 3,7 46 58 ’59 1,07 108’ lil 1’13_’117’ 20b 2,40 541’ 243’ 244?
between other devices using a second priority data transfer bandwidth. The second data transfer occurs at a second
Field of Search 370 ’
’
’
’
’
769/235’
priority level. Thus, the system of the present invention
ensures the ?rst data transfer at the ?rst priority level is not
(56)
References Cited
disturbed by the second data transfer. In this manner, the system of the present invention guarantees the ?rst priority
U-S- PATENT DOCUMENTS O’Connell et al.
data transfer bandwidth for the software process.
5,241,632 A
*
8/1993
5,282,207 A
*
1/1994 Jurkevich .............. .. 370/110.1
....... .. 395/325
24 Claims, 15 Drawing Sheets
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US RE38,134 E
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Jun. 3, 2003
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US RE38,134 E
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Jun. 3, 2003
Sheet 6 0f 15
US RE38,134 E
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Process A
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Jun. 3, 2003
Sheet 9 0f 15
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US RE38,134 E
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Sheet 10 0f 15
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US RE38,134 E
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US RE38,134 E
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US RE38,134 E 1
2
SYSTEM FOR COMMUNICATIONS WHERE FIRST PRIORITY DATA TRANSFER IS NOT DISTURBED BY SECOND PRIORITY DATA TRANSFER AND WHERE ALLOCATED BANDWIDTH IS REMOVED WHEN PROCESS TERMINATES ABNORMALLY
One of the major bottlenecks in designing fast, high performance computer systems is the method in which the various hardware devices comprising the computer system
Matter enclosed in heavy brackets [ ] appears in the original patent but forms no part of this reissue speci? cation; matter printed in italics indicates the additions made by reissue.
devices of the computer system. The bus acts as a shared conduit over which electronic signals are conducted,
communicate with each other. This method is dictated by the “bus” architecture of the computer system. A “bus” is comprised of a set of wires that is used to electrically interconnect the various semiconductor chips and hardware
10
enabling the various components to communicate with each other. FIG. 1 shows a typical prior art bus architecture 100. Virtually all of today’s computer systems use this same type of busing scheme. Computer system 100 includes a central
15
processing unit (CPU) 101 coupled to a host bridge/memory
FIELD OF THE INVENTION
The present invention pertains to a novel system for prioritized communication within a computer system. More particularly, the present invention relates to a method and system for a prioritized communication function which
controller 102, which in turn coupled to a random access
memory system (hereafter memory) 103 and a bus 104. Various devices 105—108 are coupled to computer system
allows communications between multiple devices of a com
puter system to be organized such that higher priority
100 via bus 104. Bus 104 is used to electronically interconnect the CPU 101 with the memory 103 via bridge/memory controller 102. CPU 101 also accesses the various other devices 105—108 via bus 104. Bus 104 is comprised of a set of physical wires which are used to convey digital data, address information
communications receive a preferential allocation of resources within the computer system. BACKGROUND OF THE INVENTION
In the past, computers were primarily applied to process
ing rather mundane, repetitive numerical and/or textual tasks
25
involving number-crunching, spread sheeting, and word processing. These simple tasks merely entailed entering data
erate a request to retrieve certain data stored on hard disk
from a keyboard, processing the data according to some computer program, and then displaying the resulting text or numbers on a computer monitor and perhaps later storing these results in a magnetic disk drive. However, today’s computer systems are much more advanced, versatile, and
105. This read request is communicated via bridge/memory controller 102 and via bus 104 to hard disk 105. Upon receipt of this read request, hard disk 105 accesses and reads the desired data from its internal media and subsequently sends the data back over bus 104 to the CPU 101. Once the
sophisticated. Especially since the advent of digital media applications and the Internet, computers are now commonly called upon to accept and process data from a wide variety
for specifying the destination of the data, control signals, and timing/clock signals. For instance, CPU 101 may gen
35
of different formats ranging from audio to video and even
realistic computer-generated three-dimensional graphic images. Apartial list of applications involving these digital media applications include the generation of special effects for movies, computer animation, real-time simulations,
CPU is ?nished processing the data, it can be sent via bus 104 for output by a device coupled to bus 104 (e.g., graphics output device 106 or network adapter device 107). One constraint with this prior art bus architecture is the fact that it is a “shared” arrangement. All of the components 105—108 share the same bus 104. They each rely on bus 104 to meet their individual communication needs. However,
video teleconferencing, Internet-related applications, com
bus 104 can transfer only a ?nite amount of data to any one
puter games, telecommuting, virtual reality, high-speed databases, real-time interactive simulations, medical diag
measured as millions of bytes per second, or MB/sec). The
nostic imaging, and the like. The proliferation of digital media applications is due to
of devices 105—108 in any given time period (e.g., typically
45
the fact that information can be more readily conveyed and
comprehended with pictures and sounds rather than with text or numbers. Video, audio, and three-dimensional graphics render a computer system more user friendly, dynamic, and
total amount of data which can be transferred in a given time period is often referred to as the data transfer “bandwidth” or simply bandwidth. The total amount of data which can be transferred over bus 104 in a given time period is referred to as the bandwidth of bus 104, and for a typical computer system is often between 100 to 300 MBytes/sec.
realistic. However, the added degree of complexity for the design of new generations of computer systems necessary for processing these digital media applications is tremen
Computer system 100 uses a relatively simple arbitration scheme to allocate bus bandwidth. Hence, if bus 101 is
dous. The ability of handling digitized audio, video, and
devices (e.g., device 105 and device 106), then all the other devices (e.g., memory 102, device 104, and CPU 103) must
graphics requires that vast amounts of data be processed at extremely fast speeds. An incredible amount of data must be processed every second in order to produce smooth, ?uid,
currently busy transmitting signals between two of the
55
wait their turn until that transaction is complete and bus 104 again becomes available. If a con?ict arises, an arbitration
and realistic full-motion displays on a computer screen.
circuit, usually residing in bridge/memory controller 102,
Additional speed and processing power is needed in order to
resolves which of the devices 105—108 gets priority of
provide the computer system with high-?delity stereo sound and real-time, and interactive capabilities. Otherwise, if the
access to bus 104. Because of this, it becomes very difficult to predict and account for how the bandwidth is allocated
computer system is too slow to handle the requisite amount
among devices using the bus. There is not an ef?cient means
of data, its rendered images would tend to be small, grainy and otherwise blurry. Furthermore, movement in these images would likely be jerky and disjointed because its
for controlling bus bandwidth allocation among competing
update rate is too slow. Sometimes, entire video frames
might be dropped. Hence, speed is of the essence in design
ing modern, state-of-the-art computer systems.
65
devices. In computer system 100, as in other typical com puter systems, it is difficult to efficiently coordinate among competing devices for use of the computer system’s bus. In addition to coordinating for use of the computer
system’s bus, another constraint results from the fact that
US RE38,134 E 3
4
individual hardware devices have internal schemes for coor
bandWidth betWeen the devices in response to the request and performs a ?rst data transfer betWeen the devices using
dinating among competing data requests. For example, hard disk 105 may be accessing frames of video data for output to graphics device 106 for display. Subsequently, hard disk
the ?rst priority data transfer bandWidth. In addition, the system of the present invention performs a second data transfer betWeen other devices using a second priority data transfer bandWidth. HoWever, the second data transfer occurs at a second priority level. Thus, the system of the
105 receives a request to store data output from CD-ROM 108 and a request for data from netWork adapter device 107. Since, data retrieval and output by hard disk 105 cannot occur instantaneously, the competing requests are placed into an internal queue. The competing data requests are
subsequently serviced by hard disk 105 serially. Thus, When
present invention ensures the ?rst data transfer at the ?rst 10
graphics device 106 requests the neXt frames of data, the
Width requirements of the above high priority applications Without shutting out requests from loWer priority applica
request must Wait in the internal queue With the other
requests. Because of this, a video stream played by graphics device 106 could drop several frames, or even fail entirely. Even though access to the video data may be a much higher priority to the user than the data request from CD-ROM 108
tions. In so doing, the system of the present invention accommodates the critical real-time data requirements of 15
digital video, digital audio, 3D graphics, real-time compres sion and decompression applications, and the like. In addition, the present invention includes a priority
or netWork adapter 107, the higher priority request must Wait in the internal queue With all other loWer priority requests.
scheduling process Wherein higher priority requests for
These constraints make it dif?cult for current computer
computer system services are scheduled for processing
systems (e.g., computer systems in accordance With com puter system 100) to run the latest, most real-time critical, softWare applications. As such, applications Written for these
before loWer priority requests. The priority scheduling pro cess of the present invention is capable of functioning Without speci?c supporting hardWare. In so doing, the
systems are structured to function around the bandWidth and
priority limitations of the computer system 100. The nature of data the applications transfer via the system bus is accordingly dictated by the total bandWidth and bandWidth
priority level is not disturbed by the second data transfer. The system of the present invention services the band
25
present invention provides communications ef?ciency ben e?ts in computer systems Which do not provide speci?c hardWare support for prioritiZed peer to peer communica
tion. Hence, the present invention provides advantageous
allocation constraints of the system bus. As a result, there are
bene?ts to older applications and computer systems.
very feW full motion 3D simulation applications Written for
In this manner, the system of the present invention guar antees the ?rst priority data transfer bandWidth for the softWare process. This alloWs loWer priority data to be transferred form one device coupled to the computer system to another device coupled to the computer system Without
desktop systems. In the 3D applications that do eXist, the realism and richness of the 3D applications are greatly simpli?ed in order to reliably and responsively run Without sloWing the computer system to a craWl. TomorroW’s appli cations Will be rich 3D simulations. They Will include
extensive video manipulation by the computer system’s processor. Multiple video streams, digital synthesis, digital
impacting high priority, real-time critical, data transfer band 35
audio are a feW of the many applications envisioned. Given
their constraints, typical computer systems (e.g., computer
3D graphics. BRIEF DESCRIPTION OF THE DRAWINGS
system 100) are rapidly becoming insuf?cient in light of the demands imposed by tomorroW’s neW applications.
The present invention is illustrated by Way of eXample and not by Way of limitation, in the ?gures of the accom panying draWings and in Which like reference numerals refer
Thus, What is required is a method and system Which
greatly increases communication ef?ciency among applica
to similar elements and in Which: FIG. 1 shoWs a typical prior art bus architecture used in
tions of differing priority. What is required is a method and system Which accommodates the critical real-time data
requirements of digital video, digital audio, 3D graphics, real-time compression and decompression applications, and
Width requirements of applications such as digital video and
45
the like. What is further desired is a method of servicing the
most computer systems. FIG. 2 shoWs a priority input output diagram in accor dance With the present invention. FIG. 3 shoWs a digram of prioritiZed data transfer access in accordance With the present invention. FIG. 4 shoWs a diagram of prioritiZed data transfer access using a packet sWitched router in accordance With the
bandWidth requirements of the above high priority applica tions Without shutting out requests from loWer priority applications. The desired solution should provide commu nications ef?ciency bene?ts in computer systems not having solution speci?c hardWare support. The method and system of the present invention provides a novel solution to the
present invention. FIG. 5 shoWs a logic diagram of a portion of the ring
above requirements.
buffer included in the hard disk array in accordance With one
SUMMARY OF THE INVENTION
The present invention provides a method and system for
greatly increasing communication efficiency among appli cations of differing priority. The present invention is imple mented on a computer system having a microprocessor and
a plurality of peripheral devices coupled to the computer
system. To provide for prioritiZed communications, the system of the present invention determines a ?rst priority level and determines a second priority level. The system of the present invention receives a bandWidth allocation
55
embodiment of the present invention. FIG. 6A shoWs a diagram of a priority scheduling process in accordance With the present invention. FIG. 6B shoWs a diagram of the priority scheduling process of a device driver in accordance With the present invention. FIG. 6C shoWs a 64 KB data transfer graph, a 256 KB data
transfer graph, and a corresponding legend that shoWs the amount of time required to complete a typical data transfer
using a process in accordance With one embodiment of the request from a softWare process to transfer data at the ?rst 65 present invention. priority level betWeen tWo or more peripheral devices. The FIG. 7 shoWs a How chart of the steps of a process in accordance With one embodiment of the present invention. system subsequently allocates a ?rst priority data transfer
US RE38,134 E 6
5
mines a ?rst priority level and determines a second priority level. The system of the present invention receives a band Width allocation request from a softWare process to transfer data at the ?rst priority level betWeen tWo or more peripheral
FIG. 8 shows a block diagram of one embodiment of the
packet switched router architecture of the present invention. FIG. 9 shoWs a more detailed diagram of the fundamental
blocks associated With the packet sWitched router of the
devices. The system subsequently allocates a ?rst priority
present invention.
data transfer bandWidth betWeen the devices in response to the request and performs a ?rst data transfer betWeen the
FIG. 10 shoWs a detailed circuit diagram of a link
controller of the present invention. FIG. 11 shoWs a sWitching matrix of the preferred embodiment of the present invention. FIG. 12 shoWs an exemplary sWitched circuit for provid ing concurrent communications. FIG. 13 shoWs one exemplary computer system incorpo ration the architecture of the present invention.
devices using the ?rst priority data transfer bandWidth. In addition, the system of the present invention performs a second data transfer betWeen other devices using a second
priority data transfer bandWidth. HoWever, the second data transfer occurs at a second priority level. Thus, the system of the present invention ensures the ?rst data transfer at the 15
DETAILED DESCRIPTION OF THE INVENTION
softWare process. This alloWs data to be transferred from one
device coupled to the computer system to another device
In the folloWing detailed description of the present invention, a method and system for prioritiZed communica
coupled to the computer system Without impacting high priority, real-time critical, data transfer bandWidth require
tion in a computer system, numerous speci?c details are set
ments of applications such as digital video and 3D graphics. Hence, the present invention provides a method and
forth in order to provide a thorough understanding of the present invention. HoWever, it Will be obvious to one skilled in the art that the present invention may be practical Without these speci?c details. In other instances Well knoWn
methods, procedures, components, and circuits have not
?rst priority level is not disturbed by the second data transfer. In this manner, the system of the present invention guar antees the ?rst priority data transfer bandWidth for the
system for greatly increasing communication efficiency among applications of differing priority. At any given 25
instant, there are several processes running on the computer system. Each process consumes a ?nite amount of data
been described in detail as not to unnecessarily obscure
transfer bandWidth as it performs its designed task. These processes often compete for computer system resources, particularly data transfer resources. On a busy type 100
aspects of the present invention. Some portions of the detailed descriptions Which folloW are presented in terms of procedures, logic blocks,
computer system, high priority softWare applications are
processing, and other symbolic representations of operations
often signi?cantly delayed or even stalled While loWer
on data bits Within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their Work to others skilled in the art. A
priority applications or processes utiliZe the computer sys
procedure, logic block, process, step, etc., is here, and
tem’s bus for data transfer. If computer system resources are
allocated to the high priority applications, the loWer priority 35
applications can be “shut off” or starved for system resources.
generally, conceived to be a self-consistent sequence of steps
The system of the present invention services the band
or instructions leading to a desired result. The steps are those
Width requirements of the high priority applications Without
requiring physical manipulations of physical quantities.
shutting out the bandWidth requirements of the loWer pri ority applications. In so doing, the system of the present invention accommodates the critical real-time data require ments of digital video, digital audio, 3D graphics, real-time
Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherWise manipulated in a computer system. It has proven convenient
compression and decompression applications, and the like,
at times, principally for reasons of common usage, to refer
While still running loWer priority processes. In addition, the present invention includes a priority scheduling process Wherein higher priority requests for computer system ser vices are scheduled for processing before loWer priority requests. The priority scheduling process of the present invention is capable of functioning Without speci?c support ing hardWare. In so doing, the present invention provides communications ef?ciency bene?ts in computer systems Which do not provide speci?c hardWare support for priori
to these signals as bits, values, elements, symbols,
45
characters, terms, numbers, or the like. It should be borne in mind, hoWever, that all of these and similar terms are to be associated With the appropriate
physical quantities and are merely convenient labels applied to these quantities. Unless speci?cally stated otherWise as
apparent from the folloWing discussions, it is appreciated that throughout the present invention, discussions utiliZing terms such as “allocating” or “transferring” or “executing” or “de?ning” or “storing” or “scheduling” or “prioritizing” or the like, refer to the action and processes of a computer
tiZed peer to peer communication. In this manner, the system 55
system (e.g., computer system 700 of FIG. 13), or similar electronic computing device, that manipulates and trans forms data represented as physical (electronic) quantities Within the computer system’s registers and memories into other data similarly represented as physical quantities Within
system of the present invention and its bene?ts are discussed in detail beloW.
FIG. 2 shoWs a priority input output diagram 200 in
the computer system memories or registers or other such information storage, transmission or display devices. The present invention is implemented on a computer
system having a microprocessor and a plurality of peripheral devices coupled to a packet sWitched router included in the
computer system. To provide for prioritiZed communications, the system of the present invention deter
of the present invention bene?ts these “legacy” computer systems in addition to being backWard compatible. Hence, the present invention provides advantageous bene?ts to older applications and computer systems. The method and
65
accordance With the present invention. In FIG. 2, a hard disk array 21 has received a request for a data transfer 25 from the hard disk 21 to a graphics output device 22. In addition, the hard disk array 21 has also received requests for a data transfer 26 from the hard disk array 21 to a netWork adapter card 23, and a data transfer 27 from a CD-ROM 24 to the hard disk array 21.
US RE38,134 E 8
7 Thus, the graphics output device 22, the network adapter
amount of data transfer bandwidth, represented by region
card 23, and the CD-ROM 24 are each competing for the
31, of hard disk array 21. The system of the present invention allocates a portion of data transfer bandwidth 31
data transfer bandwidth of the hard disk array 21. In a
conventional computer system, data transfer 25, data trans fer 26, and data transfer 27 are typically of the same priority. The respective device drivers for the graphics output device
to satisfy high priority data transfer 25. The remaining portion of data transfer bandwidth 31 is used to satisfy the low priority data transfers 26 and 27. Thus, the present invention ensures high priority data transfer 25 is not
22, network adapter card 23, and CD-ROM 24 each require computer system resources (e. g., data transfer bandwidth) to
disturbed or otherwise adversely impacted by low priority
either read from or write to hard disk array 21. As described above, a conventional computer system uses
data transfers 26 and 27. Low priority data transfers 26 and 27 share the remaining portion of data transfer bandwidth
a relatively simple arbitration scheme to allocate bus band width on a shared system bus, wherein graphics output
31. In this manner, the present invention services the data
device 22, network adapter card 23, and CD-ROM 24 each
out shutting out low priority data transfers 26 and 27. FIG. 4 shows a diagram 40 of prioritiZed data transfer
transfer requirements of high priority data transfer 25 with
arbitrate for owner ship of the system bus in order to
complete data transfer 25, data transfer 26, and data transfer 27. In a computer system in accordance with the present
15
access using a packet switched router 201 in accordance
with the present invention. The packet switched router 201 of the present invention is coupled to a plurality of periph
invention, however, hard disk array 21, graphics output device 22, network adapter card 23, and CD-ROM 24 are each coupled to a packet switched router included within the
computer system (e. g., computer system 700 of FIG. 13). By utiliZing the packet switched router (as described below), the
eral devices (e.g., device 48, device 49, device 50, and device 51) along with hard disk array 21, graphics output device 22, network adapter card 23, and CD-ROM 24.
computer system in accordance with the present invention can accomplish data transfer 25, data transfer 26, and data
As described above, data is transferred between two devices coupled to packet switched router 201 in the form of
individually addressed data packets. Thus, high priority data
transfer 27 simultaneously. The graphics output device 22, network adapter card 23, and CD-ROM 24 each transfer data to or from hard disk array 21 in the form of individually
25
addressed data packets. There is not, however, an unlimited amount of data transfer bandwidth to and from hard disk
array 21. Thus, data transfer 25, data transfer 26, and data transfer 27 each compete for the ?nite amount of data transfer bandwidth to and from hard disk array 21. Referring still to FIG. 2, data transfer 25 is for a full
motion video display software application. Data transfer 25 transfers a video stream comprised of frames of video data from hard disk array to a graphics output device. The video
display produced by graphics output put device 22 is often a high resolution, 20—30 frames per second full motion video, thus data transfer 25 involves the transfer of very large amounts of data (often several hundred Mbits/sec or more). The frames of video data need to be transferred to the internal buffers of graphics output device 22 via data transfer 25 in an efficient, orderly manner to prevent buffer under run. If the data transfer bandwidth requirements of data transfer 25 are not met, the video stream played by graphics output device 22 could drop several frames or even fail
35
transfer 25 (shown in FIG. 3) involves the transfer of data packets from hard disk array 21 to graphics output device 22 via packet switched router 201. Similarly, low priority data transfers 26 and 27 involve the transfer of respective indi vidual data packets from hard disk array 21 to network adapter card 23 and from CD-ROM 24 to hard disk array 21, via packet switched router 201. The hard disk array 21, in accordance with the present invention, communicates with the packet switched router by means of “request packets”.
These request packets are managed and manipulated in “packet request queues”. These packet request queues are organiZed to facilitate the prioritiZed communication process of the present invention. A similar set of packet request queues are coupled to each of the devices coupled to packet switched router 201 (eg hard disk array 21, graphics output
device 22, Network adapter card 23, CD-ROM 24, and devices 48—51). The packet request queues temporarily stored the request packets as they are transferred by packet switched router 201. Each output port of the packet switched router has its own request queue. The packet switched router
then arbitrates among the packets, determining which should 45
since data transfer 26 and data transfer 27 are not as
be sent to the destination port ?rst, and which should follow. FIG. 5 shows a diagram of a set of request packets intended for transfer to a particular device (eg the hard disk array 21) in accordance with one embodiment of the present invention. The set of request packets 60 comprises a “reload interval”, which is a unit of time over which the packet switched router manages the How of request packets. For
real-time critical with regard to serving the user of the
eXample, request packets from graphics 22, Network adapt
entirely. As such, data transfer 25 is a high priority data transfer. Data transfer 26 involves an ordinary ?le request from an
external network via network adapter card 23. Data transfer 27 involves a transfer of graphics data (e.g., 3D object textures) from CD-ROM 24 to hard disk array 21. Hence,
computer system, they are both lower priority data transfers. The system of the present invention ensures high priority data transfer 25 is not degraded by lower priority data transfer 26 and lower priority data transfer 27. FIG. 3 shows a diagram 30 of prioritiZed data transfer access in accordance with the present invention. Diagram 30 shows higher priority data transfer 25 and lower priority data
card 24, and CD-ROM 23 might all be destined for trans 55
In the present embodiment, each request packet may be up to one cache line long (ie 128 bytes). As individual request packets are received by the packet switched router, and routed for delivery to a particular device (eg the hard disk array 21) the packet switched router “arbitrates” among these packets to select their order of delivery.
transfer 26 and 27. As described above, data transfer 25 is a
high priority transfer of video data from hard disk array 21 to graphics output device 22. Data transfer 26 and data
Line 61 represents a division of the reload interval 60 into
transfer 27 are both lower priority data transfers to network
adapter card 26 and from CD-ROM 24 respectively. Diagram 30 shows how high priority data transfer 25, and low priority data transfers 26 and 27 each access the ?nite
mission to the hard disk array 21 within a single reload interval.
65
two logical components: a high priority portion 62, and a remainder portion 63. As shown in FIG. 5, 40% of the reload interval has been allocated for high priority transfer, and 60% of the reload interval has been allocated for all other
