SiGe Selective Epitaxy: Morphology and Thickness Control for High Performance CMOS Technology J. R. Holta, E. C. T. Harleya, T. N. Adama, S. J. Jenga, K. Tabakmana, R. Palb, H. M. Nayfeha, L. R. Blackb, J. J. Kempistya, M. W. Stokerc, A. Dubea, D. J. Schepisa a

IBM SRDC Advanced Micro Devices (AMD) c Freescale Semiconductor Hopewell Junction, New York 12533, USA b

Embedded SiGe (eSiGe) has become a widely used method to enhance device performance. The key step in this process is the selective epitaxial growth of a SiGe film in the source/drain region of the transistor. In the present study, we describe how the epitaxial growth may be controlled on multiple levels. On a microscopic level, the morphology is a function of the process conditions and the structure in which the epitaxial film is grown. On a macroscopic level, the loading effect can be characterized by a simple empirical model based on gas phase reactant depletion. Finally, on a global level, the within-wafer thickness variation can be controlled by temperature-based uniformity tuning, and the runto-run growth rate drift can be controlled by an advanced process control (APC) feedback loop.

Introduction To maintain CMOS device performance with continued scaling, it has been necessary to utilize mobility enhancement techniques. One of the most effective and widely used techniques is an embedded SiGe layer grown with selective epitaxy in the source/drain region of the device, also known as “eSiGe” (1-4). As the eSiGe process has been continually improved for higher device performance, the device performance has become more sensitive to the detailed properties of the epitaxial film. Therefore, it may be necessary to precisely control the epitaxial growth to meet the requirements of a given technology. In the present study we describe how the epi growth may be controlled on the microscopic, macroscopic and global levels. At the outset of this paper we would like to clarify our definition of “morphology” vs. “loading effect.” We define morphology to be the epi film shape on a microscopic level. In general, the morphology is a complex interaction between the structure in which the film is grown, the film thickness and composition, and the process conditions under which the growth takes place. On the other hand, the loading effect is defined as a macroscopic-level gas depletion effect. The loading effect describes changes in the epi growth rate due to differences in the percent of exposed Si and/or dielectric material present on the wafer. Finally, the global level is characterized by across-wafer and runto-run thickness variation, which can be caused by variation in the temperature, pressure or gas flow during the epitaxial growth. We will discuss each of these levels in detail.

All selective epitaxial growth described in this work was performed on 300 mm wafers using RT-CVD epitaxial growth in a commercially available lamp-heated quartzwalled chamber. Morphology: Definitions An epi film is typically characterized by measuring its thickness and composition on a large area measurement pad, and then taking a cross-sectional SEM or TEM image of the transistor. However, the terminology that describes the morphology of the epi growth can be difficult to pin down. Terms like “flat,” “rounded,” and “faceted” are rarely quantifiable and so may be applied differently at different sites or even at different projects in the same site. Whenever possible in the present work we will refer to SEM or TEM images to clarify the meaning of such terms. To place the images in context, Figure 1 shows a schematic representation of a typical eSiGe device with the key features labeled.

Figure 1. Schematic representation of an eSiGe device showing a) top-down vs. b) gateperpendicular cross-section vs. c) gate-parallel cross-section. Previous papers on SiGe epitaxy have been concerned primarily with the defectivity of the epi layer, or have regarded epi faceting as a problem to be solved (5-8). We would like to present the epi morphology as a controllable feature, so one may invoke different morphologies as needed to solve different technical problems. Among the many structural influences that can change the epi morphology, we will discuss in detail source/drain recess shape, device width, and gate pitch. Among the many process conditions that can change the epi morphology, we will discuss in detail precursor, HCl gas flow, film composition, and H2 carrier gas flow.

Morphology: DCS vs. SiH4 Figure 2 shows the morphology of a dichlorosilane (DCS)-based epitaxial growth condition on wafers with different recess shapes – one recess is bowl-shaped while the other is relatively flat. The epi growth in the bowl-shaped recess is visibly thicker and sharply peaked. In contrast, Figure 3 shows the same bowl-shaped vs. flat recess shape, but in this case the epitaxial process used SiH4 as a precursor instead of DCS. For SiH4 epi the change in recess shape does not result in a large morphology shift.

Figure 2. Cross-section SEM showing DCS-based eSiGe grown on a) bowl-shaped recess and b) flat recess. Cross-section was performed gate-parallel, as in Figure 1c.

Figure 3. Cross-section SEM showing SiH4-based eSiGe grown on a) bowl-shaped recess and b) flat recess. Cross-section was performed gate-parallel, as in Figure 1c. What could be causing the dramatically different response of DCS vs. SiH4 epi to the recess shape? We will present evidence that the root cause is different growth rate next to the STI oxide sidewall, combined with different crystal plane-limited growth rate. Figure 4 shows the same DCS-based epi wafer used in Figure 2a, comparing the crosssection of a wide vs. narrow device. The epi morphology is nearly identical between the two device widths. On the other hand, Figure 5 shows the same SiH4-based epi wafer used in Figure 3a, comparing the cross-section of a wide vs. narrow device. In this case, the epi is much thinner in the narrow device compared to the wide device. Since the only difference between the wide and narrow structure is the proximity of the shallow trench isolation (STI), we can conclude that the DCS growth rate is not significantly changed by the presence of an oxide surface. In contrast, the SiH4 growth rate is significantly decreased when growing along an oxide sidewall. Another manifestation of this effect is shown in Figure 6, in which the DCS epi is shown growing up the nitride spacer sidewall, while the SiH4 epi remains “pinned” at the bottom edge of the spacer.

Figure 4. Cross-section SEM showing DCS-based eSiGe grown on a) wide device and b) narrow device. Cross-section was performed gate-perpendicular, as in Figure 1b.

Figure 5. Cross-section SEM showing SiH4-based eSiGe grown on a) wide device and b) narrow device. Cross-section was performed gate-perpendicular, as in Figure 1b.

Figure 6. Cross-section TEM showing epi morphology at the spacer edge for a) DCSbased growth vs. b) SiH4-based growth. The relative crystal-plane dependence of the growth rate can be seen in a large gate pitch device, as shown in Figure 7. In this case the DCS growth exhibits “shoulders” next to the spacer, while the SiH4 growth is flat. This shows that the growth rate from the <110> recess sidewall is much larger for DCS compared to SiH4. Put another way, SiH4 growth rate has a much larger crystal-plane dependence, while the DCS growth rate is more comparable on the different crystal planes.

Figure 7. Cross-section SEM in a larger gate pitch device showing a) DCS-based vs. b) SiH4-based epi growth morphology. Taken together, these results help explain the observed behavior shown in Figures 2 and 3. That is, the DCS-based growth in Figure 2b has a sharply peaked epi film morphology due to the growth from the higher sides of the bowl-shaped recess. By contrast, the SiH4-based growth in Figure 3a is relatively lower due to the relatively low growth rate on the <111> crystal plane. Also, comparing Figures 2b and 3b the DCSbased epi is unaffected by the STI oxide sidewall, while the SiH4-based film is

significantly thinner. Further examination and comparison of the underlying reaction dynamics of DCS vs. SiH4 epi growth is beyond the scope of this paper. Morphology: Control In the previous section we presented several results that highlight the different growth morphology of DCS vs. SiH4-based epi. It is natural to ask if the morphology can be controlled by other process parameters beyond simple choice of precursor. To answer this question we use the SiH4-based epi process as a baseline, and we investigate in particular the wide vs. narrow morphology delta shown in Figure 5. In the previous section we concluded that the relative growth rate of the epi proximate to the STI oxide sidewall was responsible for the lower epi thickness in the narrow device. Given that conclusion, process conditions related to the net growth rate on oxide ought to modulate the narrow width epi thickness. Figure 8 shows the wide vs. narrow morphology of a low-HCl flow process compared to a high-HCl flow process. HCl inhibits the non-selective nucleation on dielectric, so higher HCl flow decreases the net growth rate on oxide. Indeed it can be seen that lower HCL flow gives increased fill in the narrow device.

Figure 8. Cross-section SEM in a larger gate pitch device showing wide vs. narrow morphology for SiH4-based epi with a) low HCL flow vs. b) high HCL flow (from Figure 5). In the previous section we showed that the epi morphology in the larger gate pitch device can be used to judge the relative growth rate on different crystal plans. So if the HCL flow can change the narrow vs. wide morphology, does it also change the relative morphology of the large vs. small gate pitch? Figure 9 shows that the morphology of the large pitch is unchanged (flat) for the low-HCl flow condition. Thus, the narrow width morphology in this case is driven purely by the difference in growth rate along the dielectric.

Figure 9. Cross-section SEM in a large gate pitch device showing the low-HCl flow SiH4-based epi growth from Figure 8a. The chrome layer is for decoration only and was added during SEM sample preparation.

Another factor that influences the nucleation rate on oxide is the Ge percentage of the epi growth. That is, higher percentage Ge epi films are known to have an increased nucleation period on oxide. Figure 10 shows the wide vs. narrow morphology of a lowGeH4 flow compared to a high-GeH4 flow, and it can be seen that lower GeH4 flow does give increased fill in the narrow device.

Figure 10. Cross-section SEM in a larger gate pitch device showing wide vs. narrow morphology for SiH4-based epi with a) low GeH4 flow vs. b) high GeH4 flow (from Figure 5). Finally, we consider the effect of carrier gas flow, in which increased carrier gas flow decreases the partial pressure of the reactants and also increases the relative gas velocity over the wafer. Figure 11 shows the wide vs. narrow morphology for different carrier gas flows, and it can be seen that lower carrier gas flow gives increased fill in the narrow device.

Figure 11. Cross-section SEM in a larger gate pitch device showing wide vs. narrow morphology for SiH4-based epi with a) low H2 flow vs. b) high H2 flow (from Figure 5). Loading Effect As we have demonstrated in the previous section, the epi growth strongly depends on the relative partial pressure of the gas phase reactants. However, it is known that only a thin layer of the gas flow above the surface of the wafer actually contributes to the epitaxial growth, sometimes referred to as the stagnant layer or boundary layer (9). Since this thin layer is not an infinite source of reactants, the partial pressures of the reactants may change, resulting in gas depletion-based loading effects. This loading effect has

been studied in great detail previously with a custom-designed mask and complex modeling focused on understanding the underlying reaction mechanism (10). However, we are interested in a far simpler question – that is, given a well characterized epi process and a density map for a given chip layout, we would like to predict the growth rate variation due to loading effect. Given this requirement, we have developed an empirical model that can be used for precisely this calculation. The model uses only two free parameters per material present on the wafer. The model parameters can be determined by appropriate measurements on virtually any mask for which a density map exists, and can be used to generate a predicted growth rate and Ge percentage map for any other density map available. To test the model we used existing test site masks to construct a series of wafers with amounts of exposed Si that varied from 0.13% to 5.5% to 67%. For each wafer the epi thickness was determined at multiple sites with AFM step height measurement. The density map of each mask and the measured epi thicknesses were used as inputs to the model to determine four fit parameters. Figure 12 shows the agreement between the model and experiment over the entire span of the percentage of exposed Si. The line through the data is 1:1 correspondence. The agreement is striking, and gives us confidence in the fitness of the model across a large range of exposed Si and growth rate. This method can be used to rapidly characterize potential epi process conditions so that any conditions with an unacceptable loading effect can be avoided. A more detailed discussion of the model and the loading effect delta due to various epi process parameters is beyond the scope of this paper (11).

Figure 12. Comparison of the epi growth rate as measured by AFM (x-axis) vs. predicted by a gas-depletion based loading effect model (y-axis). The solid line is a 1:1 correlation and is shown for reference only.

Thickness Control Since the epi film thickness can change the device performance and affect yield it is important to try to minimize the epi thickness variation. Typically a single-wafer epi reactor has a rotating susceptor, so uniformity tuning is performed by running a test wafer and then adjusting the temperature offsets or lamp power center to edge until the best within wafer uniformity is achieved. At the end of this procedure the resulting within wafer thickness distribution is one that cannot be further tuned by simple center-to-edge deltas, typically characterized by a “W” or “M” shape in which the R/2 region of the wafer is either the lowest or highest point on the wafer. To improve the uniformity beyond the limitations of simple center-to-edge changes, we have developed a method of within-wafer temperature tuning based on Rs measurement of annealed implant wafers. This idea is not new – historically rapid thermal anneal systems are tuned and monitored using implant monitors. However, it was necessary to find an implant condition with good sensitivity in the temperature range typically used for epi. Once the implant condition was chosen we were able to measure the spatial effect of each lamp zone by independently changing the power given to that lamp zone. By building up a library that included the spatial effects of each lamp zone we were able to apply an optimization algorithm to give a significantly more uniform temperature distribution. This significantly improved the within-wafer uniformity on patterned wafer, as shown in Figure 13.

Figure 13. Within-wafer uniformity optimization on patterned wafer. In addition to the within-wafer component of thickness variation, it is also necessary to control run-to-run drift. We have implemented an advanced process control (APC) feedback loop that adjusts the deposition time based on the measured growth rate of previously deposited wafers. Figure 14 shows the normalized epi overfill before and after uniformity tuning and APC feedback control, showing the improved scatter and drift.

Figure 14. On-product measurement data a) before and b) after uniformity optimization and APC feedback control. Each lot includes data points from three wafers, all points are plotted. The solid line shows the target overfill value. Summary We have shown how the embedded SiGe (eSiGe) selective epitaxy process may be controlled on multiple levels. On a microscopic level the morphology can be effectively controlled through choice of precursor and relative gas flows. On a macroscopic level the loading effect can be well characterized by a simple empirical model based on gas phase reactant depletion. Finally, on a global level the within-wafer thickness variation can be controlled by temperature-based uniformity tuning, and the run-to-run thickness drift can be controlled by an advanced process control (APC) feedback loop.

Acknowledgments J. Holt acknowledges many helpful discussions with Carsten Reichel, Jinping Liu and Tsutomu Sato. This work was performed by the Research Alliance Teams at the IBM East Fishkill Research and Development Facility. References 1. 2. 3. 4.

S. Narasimha et al., IEDM Tech. Digest 2006, p. 689. A. Wei et al., ECS Trans., Vol. 3, No. 7, p. 719 (2006). T. Ghani et al., IEDM Tech. Digest 2003, p. 978. G. Eneman et al., IEEE Transactions on Electron Devices, Vol. 53, No. 7, p. 1647 (2006). 5. D. Harame and B. Meyerson, IEEE Transactions on Electron Devices, Vol. 48, No. 11, p. 2555 (2001). 6. S. Bedell et al., ECS Trans, Vol. 3, No. 7, p. 807 (2006). 7. P. Cheng et al., Semicond. Sci. Technol., 22, S140 (2007). 8. D. Dutartre et al., IEDM Tech. Digest 2007, p. 689. 9. B. El-Kareh, Fundamentals of Semiconductor Processing Technologies, p. 93, Kluwer Academic Publishers, Boston (1995). 10. J. Hallstedt et al., J. Appl. Phys., 103, 054907 (2008). 11. E. C. T. Harley, to be published.

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