USO0RE42976E
(19)
United States
(12) Reissued Patent
(10) Patent Number:
Ahn et a]. (54)
(75)
US RE42,976 E
(45) Date of Reissued Patent:
Nov. 29, 2011
SEMICONDUCTOR MEMORY DEVICE WITH
5,625,602 A *
REDUCED DATAACCESS TIME
5,715,423 A *
2/1998 Levy ........................... .. 711/103
5,892,724 A
4/1999 Hasegawa et a1.
Inventors: Jln-Hong . Ahn, Kyoungkl'dQ . (KR); Sang-H0011 Hong, Kyoungkl-do (KR); Se-Jun Kim, Kyoungki-do (KR);
4/1997 Hasegawa et a1. .......... .. 365/222
5,917,745 A * 11/1999 5,996,041 6/1999 F ,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,, 711/103 6,023,423 A * 2/2000 Aritorne ................. .. 365/18511 6,058,065 A * 5/2000 Lattimore et a1. ..... .. 365/23003
Jae_Bum K0’ Kyoungki_do (KR)
6,125,071 A
9/2000 Kohno et a1.
(Continued)
(73) Assignee: HyniX Semiconductor, Inc. (KR)
FOREIGN PATENT DOCUMENTS
(21)
Appl. No.: 11/897,516
(22) Filed:
JP
02443982
Aug. 29, 2007
(Continued)
Related US. Patent Documents
E221; sugaotgm NO _ Issued: “ Appl. No.:
6 937 535 Aug. 30, 2005
Filed:
Oct. 28, 2003
()THER PUBLICATIONS
Park, Y.K., “Highly Manufacturable 90 nm DRAM Technology”, 2002 IEEE’ pp‘ 819822‘ (Continued)
10/696,144 _
(30)
_
_
_
_
Primary Examiner * Son L Mai
Forelgn Apphcatlon Prmnty Data
(74) Attorney, Agent, orFirm * Blakely, Sokoloff, Taylor &
Oct. 29, 2002
(KR) ...................... .. 10-2002-0066269
Zafman
Feb. 21, 2003
(KR) ...................... .. 10-2003-0011121
(57)
(51)
(52) (58)
Int. C]. G1 1 C 7/00 GIIC 7/10 GIIC 8/00
@1990
ABSTRACT
A memory device includes at least tWo cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectivel y connecting the global bit line to each cell block
(2006.01) 2006.01 2006.01
US. Cl. ............. .. 365/222; 365/189.04; 365/230.05 Field of Classi?cation Search ................. .. 365/222
under Control Of a Control block, one global bit line connec IiOn unit being allocated betweenthe two cell blocks; and Said
See application ?le for Complete Search history
control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted
References Cited
data of the global bit line to the ori g inal cell block or another
( 56 )
cell block Which is determined by depending upon Whether U.S. PATENT DOCUMENTS 5,210,723 A 5/1993 Bates et 31‘ 5,299,157 A *
3/1994
5,555,529 A
9/1996 Hose, Jr. et a1.
data in response to a next instruction is outputted from the original cell block or another cell block.
Kimura et a1. ......... .. 365/189.02
7 Claims, 37 Drawing Sheets
770 LATCH UNTT
710 FIRST CELL ARRAY
705
790
CONTROL
CONNECTION UNIT
SECOND CELL ARRAY
IBL
720
US RE42,976 E Page 2 U.S. PATENT DOCUMENTS
6,134,169 6,191,988 6,445,611 6,522,600 6,545,936 6,661,706 6,768,663 6,768,692 7,088,637 7,248,538 7,327,616 7,382,641 7,480,766 2001/0014046 2002/0016967 2002/0031014 2002/0154536 2002/0159319
10/2000 2/2001 9/2002 2/2003 4/2003 12/2003 7/2004 7/2004 8/2006 7/2007 2/2008 6/2008 1/2009 8/2001 2/2002 3/2002 10/2002 10/2002
Tanaka ........................ .. 365/222
DeBrosse
2003/0051148 2003/0076719 2006/0181924 2007/0195635
Ohshima et a1. Yoo et a1. Kawai et a1. ........... .. 365/185.12 Luk et a1. .................... .. 365/205
K0 et a1
365/230.03
IiZuka
....... ..
365/189.17
Kameda et a1
.. 365/189.09
365/145
Gorobets Sakamoto
3/2003 4/2003 8/2006 8/2007
Garney Byeon et a1. ................ .. 365/200 Cha ............ ..
..
365/185.12
Chen et a1. ............. .. 365/230.08
FOREIGN PATENT DOCUMENTS
Ogata
Kang et a1
A1 A1* A1* A1*
. 711/115
JP JP JP JP JP JP JP
03-127144 06-131867 07-169295 11-306751 11-339466 2002-334579 2002-334580
5/1991 5/1994 7/1995 11/1999 12/1999 11/2002 11/2002
OTHER PUBLICATIONS
................... .. 365/205
Carlile Yabe et a1. ............. .. 365/189.05
Perner Kirihata et a1.
Marc Haberland, “Synchrone laufen schneller”, Funktionsweise und Technologie synchroner DRAMs, Elektronik, 19/ 1995, pp. 113-119. * cited by examiner
US. Patent
Nov. 29, 2011
Sheet 3 0f 37
US RE42,976 E
FIG. 3
(PRIOR ART) INSTRUCTION
INSTRUCTION ACTIVE PERIOD
I
I
FIDO
901
l
I
WLO OF THE UNIT WLI OF THE UNIT
DATA OUTPUT OF THE BLOCK 0
*I‘ I
|In.>|
NORMAL Row)‘. NORMAL ROW CYCLE TIME
CYCLE TIME
FIG. 4
(PRIOR ART) H 0
DI
M 0IIn
0W.R ..0r I D w80
ST3.TIF .HV8BR CPUNN0TKTI W0W1.mmw * mm‘I. IA0INCNA0 TIA UE0ADAUWK.H? T_lD
F IU Dw B
0I F
0
W. B
HOW CYCLE PERIOD
US. Patent
Nov. 29, 2011
Sheet 6 0f 37
US RE42,976 E
FIG. 7
770 LATCH UNTT
710 FIRST CELL ARRAY
780
705
790
CONTROL BLOCK
CONNECTION UNIT
SECOND CELL ARRAY
lBL
720
US. Patent
Nov. 29, 2011
Sheet 11 0137
US RE42,976 E
FIG. 12 GBLO
IGBLO
...____..__.___J
US. Patent
Nov. 29, 2011
Sheet 14 0f 37
m2:
2?
F.
__ I
__ ___ a:
= =
Q2.01
§e\sew
__ __
F I|l
15111;:
(Swen
US RE42,976 E
US. Patent
Nov. 29, 2011
Sheet 15 0f 37
m2:
23
F
Q
_
gr 2
ofGE
\
LJcnq:
US RE42,976 E
US. Patent
Nov. 29, 2011
Sheet 16 0137
US RE42,976 E
FIG. 14
r.____..____..__.1__.._______zl‘?°_? 1416
1412 1426
1412 1426
1412
G L o B A L B W...» U N E S E N S E M u F EH U N n
l‘n.'|»
____._.....______-.-___._-____.____-__.J
