IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 15, NO. 2, MAY 2002

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Supply-Voltage Optimization for Below-70-nm Technology-Node MOSFETs Hitoshi Wakabayashi, Member, IEEE, Ganesh Shankar Samudra, Member, IEEE, Ihsan J. Djomehri, Hasan Nayfeh, Student Member, IEEE, and Dimitri A. Antoniadis, Fellow, IEEE

Invited Paper

Abstract—A tradeoff between the performance and power consumption is discussed for below-70-nm technology-node MOSFETs, as a function of power-supply voltage. In order to optimize ) and energy-delay product the supply voltage, gate-delay ( ( 2 3 ) trends are evaluated using the characteristics of down to 24-nm physical-gate-length nMOSFETs. The gate-delay dependence on the supply voltage down to 0.9 V is almost constant at the same OFF current of 100 nA/ m. On the other hand, an optimum supply voltage for the energy-delay product significantly depends on the short-channel characteristics, and is interpreted with analytic expressions. Therefore, for the below-70-nm technology node at sub-1.0 V, it is important to design the power-supply voltage taking into consideration of a short-channel effect (SCE). Index Terms—CMOS, power consumption, power-supply voltage, gate delay, energy-delay product, short-channel effect.

I. INTRODUCTION

B

ELOW-70-nm technology-node CMOS devices have been investigated using a physical polycrystalline-silicon (poly-Si) gate length of sub-50-nm for high-performance system LSIs [1]–[4]. For a processor application, a power consumption drastically increases with the progress of technology generation [5]. Therefore, the power consumption should be suppressed even for high-performance large-scale integration (LSI), and the tradeoff between the performance and the power consumption must be investigated. In order to enhance a device performance, it is important to reduce a performance factor of gate delay , as expressed by (1) is an oxide capacitance per unit area, is a where power-supply voltage and is equal to a gate voltage is a MOSFET saturation current, is a MOSFET body-effect Manuscript received December 23, 2001. H. Wakabayashi was with with Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139-4307 USA. He is now with Silicon Systems Research Laboratories, NEC Corporation, Sagamihara, Kanagawa 229-1198, Japan (e-mail: [email protected]). G. S. Samudra was with Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139-4307 USA. He is now with The National University of Singapore, Singapore 119260. I. J. Djomehri, H. Nayfeh, and D. A. Antoniadis are with Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139-4307 USA. Publisher Item Identifier S 0894-6507(02)04473-1.

coefficient, is an effective channel length, is an is an effective channel width, and effective mobility, is a threshold voltage [6]. In order to reduce the gate delay, the small effective channel length and large supply voltages with lower threshold voltages are required. is given On the other hand, an active power dissipation , where is a frequency. In order by to reduce the active power dissipation, the supply voltage suppression must be effective for high-performance system LSI. However, there is the tradeoff relationship between the performance and the power consumption, as a function of powersupply voltage. In order to estimate the optimum supply voltage, it might be effective to use an energy-delay product [7]. In this paper, a supply-voltage selection at sub-1.0 V has and energybeen discussed to minimize gate delay on the basis of the electrical characdelay product teristics using as small as 24-nm physical poly-Si gate length nMOSFETs. II. SUB-35-nm nMOSFETS In order to investigate the relationship between the shortchannel characteristics and the supply voltages, the nMOSFETs down to 24-nm gate length are fabricated [3]. An SiON gate dielectric film with a physical thickness of 1.7 nm and an inversion thickness of 2.5 nm was fabricated by an oxynitridation process using nitrogen oxide (NO) gas. In order to form a precise gate electrode with a higher throughput, mix-and-match (M&M) lithography was carried out using a point electron-beam (EB) system (JBX-9300FS) and deep ultraviolet (DUV) radiation. Arsenic with the dose of 5 10 cm at a lower energy of 2 keV was implanted for the source/drain extensions (SDE), and BF with the dose of up to 2.5 10 cm at 30 keV with a tilt of 30 was used for the halo. Fig. 1 shows the simulated impurity profiles of SDE and high-dose halo using TSUPREM4 before an activation process. The halo, SDE, and source/drain (S/D) regions were formed by the reverse-order source/drain (R-S/D) and conventional-order S/D (C-S/D) formations using a high-ramp-rate spike annealing (HRR-SA) process, which has a fast ramp-up rate of 300 C/s and a fast ramp-down rate of 100 C/s. Thermal budget for the SDE and halo using the R-S/D formation is smaller than that using the C-S/D formation. Furthermore, in

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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 15, NO. 2, MAY 2002

(a)

Fig. 1. Simulated impurity profiles of SDE and high-dose halo before spike annealing using TSUPREM4.

(b) Fig. 3. I -V characteristics for 24-nm nMOSFETs using high-dose halo. (a)

function of halo dose. The ion-implantation (I/I) doses of low-, and cm , mid- and high-dose halos are respectively. The short-channel effect (SCE) is remarkably suppressed by the higher-dose halo. Fig. 2(b) shows the I -I characteristics, as a function of the halo dose. The higher drive current of 800 A/ m at an OFF current of 100 nA/ m is achieved by each halo dose, approximately. Fig. 3(a) and (b) shows good - characteristics of nMOSFETs with a high peak transconductance of approximately 1000 S/ m, because of the fine gate electrode as small as 24 nm.

III. ON SUPPLY VOLTAGE (b) Fig. 2.

Short-channel characteristics, as a function of halo dose.

the case of an activation process, the defect density around the SDE and halo is suppressed by the R-S/D formation. Therefore, the shallower SDE and steeper halo profiles might be formed by the suppressions of both the thermal diffusion (TD) and the transient-enhanced diffusion (TED). A cobalt-silicide (CoSi ) film of 7 /sq. was formed after a final gate-sidewall formation. A threshold-voltage dependence on the gate length at the higher drain voltage of 1.2 V is shown in Fig. 2(a), as a

In order to evaluate the low-voltage behavior for short-channel devices, we have investigated the dependence on the gate length, the halo dose and the supply voltage. Fig. 4(a)–(c) shows the I -I characteristics for various halo doses at the supply voltage below 1.5 V. The drive currents are significantly reduced by a supply-voltage decreasing for each halo dose. Simultaneously, the OFF currents also remarkably decrease with a decrease in the supply voltage, as shown in Fig. 5. It obtains the suppression of standby power dissipation. For the high-dose halo, the supply voltage of 0.9 V achieves an OFF current of 100 nA/ m. Furthermore, the higher dose halo , because of the suppressions of enhances the slope of

WAKABAYASHI et al.: SUPPLY-VOLTAGE OPTIMIZATION FOR BELOW-70-nm TECHNOLOGY-NODE MOSFETs

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Fig. 5. I

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(c)

characteristics for nMOSFETs at less than 1.5 V.

dependence on power-supply voltage, as a function of halo dose.

the subthreshold-slope and the drain-induced barrier lowering (DIBL). In order to investigate the dependence on the supply voltage for short-channel devices, the drive current can be explained with a qualitative analysis using expressions of the short-channel factors, as shown in and

the dependence on the gate delay for various halo doses at a supply voltage below 1.5 V, with the symbols as in Fig. 4. The gate delay decreases with an increase in the OFF current at a higher supply voltage for each halo dose. Furthermore, the suppression of short-channel effect remarkably suppresses the gate delay at an OFF current of 100 nA/ m, because of a gate-length reduction. However, the gate delay value at OFF current of less than 100 nA/ m significantly increases with a decrease in the supply voltage at below 0.8 V, approximately. From Fig. 6(a), the gate-delay dependence on the inverse of supply voltage for the low-dose halo is shown in Fig. 7(a). The gate-delay values significantly increase with a decrease in the supply voltage. Furthermore, the values of gate delay naturally decrease with a decrease in a gate length. From Fig. 6(a)–(c), the gate delay dependence on the inverse of supply voltage for 24-nm nMOSFETs is shown in Fig. 7(b). A higher dose halo enhances the gate delay, especially at a lower supply voltage. These results are caused by the decrease in a drive voltage . Therefore, the gate delay is a function of OFF leakage current in addition to the shot-channel effect. From (2) and (3), the derivative of gate delay is given by

(2) (3)

is a short-channel threshold voltage, is a longwhere channel threshold voltage, is a short-channel length parameter, is a parameter of DIBL, is a technology parameter, is a velocity saturation pawhich equals to rameter, and is a channel-length modulation parameter [6], slopes increase with a decrease [8]. From Fig. 4(a)–(c), in the supply voltage. This is caused by the suppression of the , as shown in (2). With these simple expresDIBL factor and the sions, derivatives of the gate delay with respect to the supply energy-delay product will be formed in following sections. voltage IV. GATE DELAY In order to achieve the high-performance devices, a gatedelay suppression has the highest priority. Fig. 6(a)–(c) shows

(4)

This equation shows obviously that a slope of gate delay is always negative for positive threshold voltages. Especially for , and equal zero and equals long channel devices, if two, the derivative of gate delay is expressed by (5) , the slope of gate delay is always negawhen tive in the long channel regions. These calculations are consistent with the experimental results, as shown in Figs. 7(a) and (b). On the other hand, from Fig. 6(b), the gate-delay values at are almost the same at higher supply voltages 100-nA/ m

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(a) Fig. 6. I

(b)

(c)

dependence on gate delay for nMOSFETs at less than 1.5 V, with the same symbols in Fig. 4.

(a)

(b)

(c)

Fig. 7. Gate delay (CV =I ) dependence on supply voltage, as a function of halo dose.

for each halo dose. Fig. 7(c) shows the gate delay dependence on the supply voltage at an OFF current of 100 nA/ m. In the case of the OFF current of less than 100 nA/ m at the lower voltage for the higher halo dose, the minimum gate delay values are used for each voltage. The gate-delay values are almost the same at higher supply voltage above 0.9 V for each halo dose. Furthermore, the gate delay decreases with an increase in a halo dose. This is because the short-channel-effect suppression using the high-dose halo reduces the gate length at the same OFF current. However, at the lower supply voltage, the gate delay values suddenly increase with a decrease in the supply voltage. From Fig. 7(c), the supply voltage at above 0.9 V should be selected to maintain the higher device performance. At the same time, a low OFF current of less than 100 nA/ m is achieved for high-dose halo at 0.9 V, as shown in Fig. 5.

energy-delay product has complicated loci, however, the OFF current and energy-delay product values are simultaneously suppressed by a decrease in the supply voltage at a higher supply voltage. In contrast, the energy-delay product values are enhanced by the supply-voltage suppression at smaller supply voltage. for the From (2) and (3), an optimum supply voltage energy-delay product is given by

V. ENERGY-DELAY PRODUCT

These equations indicate that there is an optimum supply voltage for each technology, and the optimal supply voltage strongly depends on the short-channel effect. Table I shows the optimum supply voltage estimation using short-channel-effect factors, led by the experimental results. For nanoscale devices, most increase of the drive current in a saturation region might

In order to achieve both lower power dissipation and high performance, an energy-delay product should be suppressed [7]. Fig. 8(a)–(c) shows the OFF current dependence on an for various halo doses at energy-delay product supply voltage below 1.5 V, with the symbols as in Fig. 4. The

(6) (7) and

(8) (9)

WAKABAYASHI et al.: SUPPLY-VOLTAGE OPTIMIZATION FOR BELOW-70-nm TECHNOLOGY-NODE MOSFETs

(a) Fig. 8.

I

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(b)

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dependence on energy-delay product for nMOSFETs at less than 1.5 V, with the same symbols in Fig. 4.

TABLE I OPTIMUM SUPPLY-VOLTAGE ESTIMATION USING SHORT-CHANNEL-EFFECT FACTORS FOR 24-nm nMOSFETs

be accounted for by the DIBL. Therefore, values turn out to be significantly small. This table indicates that the high-dose halo enhances the optimum supply voltage. Fig. 9(a) and (b) shows the energy-delay product dependence on the supply voltage, as functions of the gate length and the halo dose, respectively. From Fig. 9(a), the energy-delay product in 24- to 105-nm channel length range has a minimum value for each gate length at sub-1.0 V. Furthermore, the optimum supply voltage and its energy-delay product simultaneously and slightly decrease with a decrease in gate length. In contrast from Fig. 9(b) for 24-nm gate length, an optimum voltage of energy-delay product strongly depends on halo dose, as well as from (7). This result indicates that the optimum supply voltage significantly depends on the short-channel characteristics. However, the optimum supply voltage and energy-delay product simultaneously increase with an increase in the halo dose. However, from the gate delay results as discussed in Section IV, the supply voltage at above 0.9 V should be selected to maintain the device performance. Therefore, the supply voltages between the optimum and 0.9 V might be the tradeoff regions, from the view points of both the gate delay and the energy-delay product. At the same time, a low OFF current of less than 100 nA/ m is achieved for high-dose halo at below 0.9 V, as shown in Fig. 5. However, the process window is comparatively small for the high-dose halo. Therefore, if further higher dose halo were used for less than 24-nm gate length, the energy-delay products become significant to optimize the power-supply voltage. Furthermore, the suppression of supply voltage might be difficult for less than 24-nm MOSFET with a stronger halo. In order to further reduce the supply voltage, the short-channel effect should be suppressed by other technologies, i.e., super shallow

(a)

(b) Fig. 9. Energy-delay product (C V =I ) dependence on supply voltage.

source/drain extensions, elevated source/drain extensions, ultrathin SOI devices, double-gate CMOS devices, etc. VI. CONCLUSION A tradeoff between performance and power consumption was investigated for below-70-nm technology-node MOSFETs. and In order to optimize a supply-voltage, gate-delay trends were discussed using energy-delay product the characteristics of down to 24-nm physical-gate-length nMOSFETs. The gate-delay dependence on a supply voltage

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down to 0.9 V is almost constant at the same OFF current of 100 nA/ m. On the other hand, an optimum supply voltage for the energy-delay product significantly depends on the short-channel characteristics, and is interpreted with analytic expressions. Therefore, for below-70-nm technology-node, it is important to design the supply voltage taking into the account of the short-channel effect. ACKNOWLEDGMENT The authors would like to thank Drs. T. Watanabe, H. Abe, M. Fukuma, T. Kunio, T. Baba, T. Mogami, Y. Ochiai, K. Takeuchi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, and K. Yoshida for useful discussions. REFERENCES [1] Y. Taur, C. H. Wann, and D. J. Frank, “25 nm CMOS design considerations,” in IEDM Tech. Dig., 1998, pp. 789–792. [2] R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, “30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays,” in IEDM Tech. Dig., 2000, pp. 45–48. [3] H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, and T. Kunio, “45-nm gate length CMOS technology and beyond using steep halo,” in IEDM Tech. Dig., 2000, pp. 49–52. [4] B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, and M.-R. Lin, “15 nm gate length planar CMOS transistor,” in IEDM Tech. Dig., 2001, pp. 937–939. [5] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, “Device scaling limits of Si MOSFET’s and their application dependencies,” Proc. IEEE, vol. 89, pp. 259–288, Mar. 2001. [6] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998. [7] M. Rodder, S. Hattangady, N. Yu, W. Shiau, P. Nicollian, T. Laaksonen, C. P. Chao, M. Mehrotra, C. Lee, S. Murtaza, and S. Aur, “A 1.2 V, 0.1 m gate length CMOS technology: Design and process issues,” in IEDM Tech. Dig., 1998, pp. 623–626. [8] R. T. Howe and C. G. Sodini, Microelectronics, An Integrated Approach. Englewood Cliffs, NJ: Prentice-Hall, 1997.

Hitoshi Wakabayashi (M’99) graduated from the Electrical Engineering Department, Kure Technical College, Hiroshima, Japan, in 1989. He received the B.E. degree in electronic engineering with the award from the University of Tokushima, Tokushima, Japan, in 1991, and the M.E. degree in electronic engineering from the Tokyo Institute of Technology, Tokyo, Japan, in 1993. In 1993, he joined the Microelectronics Research Laboratories (currently, Silicon Systems Research Laboratories), NEC Corporation, Sagamihara, Kanagawa, Japan. He was a Visiting Scientist at the Microsystems Technology Laboratories, Massachusetts Institute of Technology, from 2000 to 2001. He is involved in the research of scaled CMOS devices and advanced device technologies including a silicon-on-insulator technology at NEC Corporatione. Mr. Wakabayashi is a member of the IEEE Electron Device Society and the Japan Society of Applied Physics. He was awarded the 8th Young Scientist Award for the Presentation of an Excellent Paper from the Japan Society of Applied Physics in 2000.

Ganesh Shankar Samudra (M’87) received the M.Sc. degree from Indian Institute of Technology, Mumbai, and M.S., M.S.E.E., and Ph.D. degrees from Purdue University. From 1986 to 1989, he was with Texas Instruments where he was elected as Member, Group Technical Staff for outstanding technical contributions in process and device simulation. He is Associate Professor at National University of Singapore and is currently Visiting Professor at Massachusetts Institute of Technology, Cambridge, MA. He has published about 50 articles in international journals and conferences. His research interests are in the area of development and application of technology computer-aided design.

Ihsan J. Djomehri was born in San Francisco, CA, in 1976. He received the B.S. degree in electrical engineering and computer science and the A.B. degree in physics from the University of California at Berkeley in 1997. He received the S.M. degree while developing a novel nanofabrication technology from the Massachusetts Institute of Technology, Cambridge, MA, in 1998. Currently, he is pursuing the Ph.D. degree in electrical engineering and conducting research with Prof. D. A. Antoniadis on inverse modeling of sub-100 nm MOSFETs, sponsored by the SRC. His professional interests include device technology and computational physics.

Hasan Nayfeh (S’97) received the B.S. degree from the University of Illinois at Urbana-Champaign in 1996 and the M.S. degree from the Massachusetts Institute of Technology (MIT), Cambridge, MA, in 1998, both in electrical engineering. He is currently pursuing the Ph.D. degree at MIT in electrical engineering. His thesis topic is SiGe based MOSFET devices for CMOS application. Mr. Nayfeh is a member of the IEEE Electron Device Society, the American Physical Society, and the Materials Research Society.

Dimitri A. Antoniadis (M’79–SM’83–F’86) a native of Greece, received the B.S. degree in physics from the National University of Athens in 1970 and the Ph.D. degree in electrical engineering in 1976 from Stanford University. His initial research activities were in the area of measurement and modeling of the earth’s ionosphere and thermosphere ranging from instrument design to computer simulation. After earning the Ph.D. degree, he led the development of the first two generations of the SUPREM process simulator, and since then his technical activity has been in the area of semiconductor devices and integrated circuit technology. He has worked on the physics of diffusion in silicon, thin-film technology and devices, and quantum-effect semiconductor devices. His current research focuses on the physics and technology of extreme-submicron Si, SOI and Si/SiGe MOSFETs. In 1978, he joined the faculty at the Massachusetts Institute of Technology (MIT), Cambridge, MA, where he currently holds the Ray and Maria Stata chair in Electrical Engineering. He was co-founder and first Director of the MIT Microsystems Technology Laboratories and from 1993 to 2000, he was Director of the SRC MIT Center of Excellence for Microsystems Technology. Currently, he is Director of the multi-university Focus Research Center for Materials Structures and Devices centered at MIT. Dr. Antoniadis was the recipient of the Solid State Science and Technology Young Author Award of the Electrochemical Society in 1979, the Paul Rappaport Award of the IEEE in 1998, and the Andrew Grove Award of the IEEE in 2002.