USO0RE40205E

(19) United States (12) Reissued Patent Funaba et al. (54)

(45) Date of Reissued Patent:

SEMICONDUCTOR DEVICE AND TIMING CONTROL CIRCUIT _

(75) Inventors: Seiji Funaba, Chryoda-ku (JP); Yoji Nishio, ChiyOda-ku (JP); Yuichi Okuda, Chryoda-ku (JP); Yoshlnobu Nakagome, chlyoda-ku (JP) 73

( )

Assi nee: El ida Memo

g

P

ry,

2/2002 Hashimoto ................ .. 327/158 4/2002 Akioka et a1. . 365/194

6,525,585 B1 *

2/2003

JP

y ( )

Flled:

11427062

JP

Aug‘ 23’ 2002 Related U-s- Patent Documents

JPO Notice of Reason of Refusal dated Oct. 26, 2007, in Japanese W1th Engl1sh translatron.

6,269,051

_

JUL 31, 2001 09/640 670

Primary ExamineriTan T. Nguyen (74) Attorney, Agent, or FirmiReed Smith LLP; Stanley P.

Filed.

Aug 1,8 2000

Fisher, Esq.; Juan Carlos A. Marquez, Esq. (57) ABSTRACT

.

,

Division of application No. 09/563,160, ?led on May 1,

[Control on the speed of operation of a delay loop from the

2000, now Pat. NO. 6,212,127.

output of a variable delay circuit to a delay control input

(52) (58)

thereof is performed. For example, frequency-dividing cir

Foreign Application Priority Data

Jun. 18, 1999

(51)

_

Issued: APPI' NO‘:

U.S. Applications:

(30)

10/1997

* cited by examiner

Patent No.:

.

(62)

10/1997

11-127063

OTHER PUBLICATIONS

Reissue of: (64)

Iida et a1. ................. .. 327/279

FOREIGN PATENT DOCUMENTS 10412182 0/1996 10-283060 4/1997

JP JP

Inc., Tok 0 JP

Apr. 1, 2008

6,351,166 B2 * 6,366,507 B1 *

(21) Appl. No.: 10/226,019 (22)

US RE40,205 E

(10) Patent Number:

cuits are respectively placed at the input and output of the

variable delay circuit. A signal obtained by frequency

(JP) ......................................... .. 11-171864

dividing a signal outputted from the variable delay circuit is

Int. Cl. GIIC 11/4076

supplied to one input of a phase comparator through a

(2006.01)

dummy delay circuit, and a signal obtained by frequency dividing the input of the variable delay circuit is supplied to 327/ 161

the other input of the phase comparator. Phase control is performed according to the result of comparison between the

Field of Classi?cation Search ................ .. 327/161

phases of both signals.] Control on the speed of operation of

US. Cl. ..................... .. 365/194; 365/233; 327/158;

a delay loopfrom the output ofa variable delay circuit to a

See application ?le for complete search history. (56)

delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the

References Cited

input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the

U.S. PATENT DOCUMENTS 5,430,394 A

*

5 939 913 A * 5’987’6l9 A

7/1995

McMinn et a1.

variable delay circuit is supplied to one input ofa phase . . .

.......... .. 327/292

8/1999 Tomita

* “H999

'''

327/l58

comparator through a dummy delay circuit, and a signal

' ' ' " 713/401

obtained by frequency-dividing the input of the variable

327/149

delay circui’ is Supplied Z0 [he 01h” MP1” of [he Phase comparator Phase control is performed according to the

5,990,714 A * 11/1999 Takahashi ...... 6,128,248 A 10/2000 Idei et a1‘

6,134,182 A * 10/2000 P110 et al. ................. .. 365/194 6,269,051

B1

*

7/2001

Funaba et a1.

......

. . . ..

mull OfCO/WPWI'SOn between [he Phases Ofbolh Signals

365/233

6,333,875 B1 * 12/2001 ShinoZaki et al. ........ .. 365/194

15 Claims, 25 Drawing Sheets

"""""""""""""""""""""

DUMMY LOAD

"1.151

DUMMY LOAD

FREQUENCY cmcum

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ma

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192B

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VARIABLE DELAY CIRCUIT

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CNTLP\ XQNTLN Q1111 COMPARISON

CONTROL

s|§s1N2AL

SIGNAL

‘fan

DELAV CONTROL CIRCUIT 1405 105

RESET DUMMY DELAY CIRCUIT (CORRESPONDING To INPUT cLocK BUFFER To OUTPUT BUFFQ) $114

U.S. Patent

Apr. 1, 2008

Sheet 1 0f 25

US RE40,205 E

N3 I.

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U.S. Patent

Apr. 1,2008

Sheet 2 0f 25

US RE40,205 E

ExTERNAL CLOCK

OUTPUT SIGNALEXTCLK(101}HHHII OF man i m DEER“: DlVIDE-BY-EIGHT 5 CYCLE FREQUENCY CIRCUIT 5 :,___

(11°) INTERNAL CLOCK

5 i

5 z

i ;

UUUL

SIGNAL INTCLK (102) 5 OUTPUT OF SECOND DIVIDE-BY-EIGHT ; FREQUENCY CIRCUIT ;

td L»

OUTPUT DELAY CIRCUIT OF DUMMY (111) 5i

wrap

__



PHASE COMPARISON i SIGNAL(112)

401

C

H402 502

'

=

H501 503

INPUT

TIMING

CLOCK

= CONTROL

CLK BUFFER CIBCLK CIRCUIT m1

P1403 7

LONG -_r 404

DLLCLK W'RE m2

#405 DATA

_

DATA

REGISTER

REGCLK

4/06 407 BUFFER f. DATAOUT

_ OUTPUT

U.S. Patent

Apr. 1, 2008

Sheet 3 0f 25

US RE40,205 E

FIG. 4 CYCLE TIME Ick INPUT CLOCK

SIGNAL (CLK)

sI'GNAL DELAY TINIE td1

OUTPUT SIGNAL OF INPUT CLOCK BUFFER (CIBCLK) ‘

CLOCK SIGNAL

I

OUTPUTTED FROM E TIMING CONTROL CIRCUIT (DLLCLK) I CLOCK SIGNAL

(m=2 IN FIGURE)

i

5

isIGNAL DELAYI ITIILIE Id2

2

TRANSMITTED TO 5 DATA REGISTER

s'IGNAL ‘DELAY TIME mxtck-(tdI humus)

I

|

'

l

-

(REGCLK) (DATAOUT)

E

|

p

‘b

|

I

IS'IGNAL 'DELAY :TIME td3

I

:.

i.

' I l

l

I

OUTPUT SIGNAL

. |

y

U.S. Patent

Apr. 1, 2008

Sheet 4 0f 25

US RE40,205 E

m l l

.hwemo?

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U.S. Patent

Apr. 1, 2008

Sheet 5 0f 25

US RE40,205 E

FIG. 6

m3

"M801 """"" "815i """""""" "861'""d""

101

E

I

J

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1‘? ________________________________ __j 901

10s

{906 if/saov N908 gréNTLP 903

: 3% DOWN 5'5?»

'

;

904

U.S. Patent

PHASE

I

COMPARISON

Apr. 1, 2008

Sheet 6 0f 25

US RE40,205 E

U.S. Patent

Apr. 1, 2008

Sheet 7 0f 25

US RE40,205 E

FIG. 1 1 ' ' 1:; ' ' ' _ ' — ‘55.13.:.ililtliggétg ' ' ~ I:

5

92°

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908

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CNTLP

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FIG. 12 10°‘? '

DIVIDE-BY-

DIVIDE

TWO

TWO

5‘ FREQ 1003;: CIRCU

‘T’WBDE'

CY 'FREQuENcY‘FREQu CIRCUIT

'

Ii

Y ' FKF % FQF }

CIRCUI

"up R‘E’sET ................................................................ SIGNAL -_

107

'

=

U.S. Patent

Apr. 1, 2008

Sheet 8 0f 25

US RE40,205 E

INPUT 5 1302

3

; DATA

; INPUT

FIG. 15 1013' /\./

QwgJE-BY;

1015

1016

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1012 3

1014 JM/

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i o

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_

QUENCY FREQUENCY FREQUENCY

HRESPONDING 5

CUIT

F/F)

CIRCUIT

CIRCUIT

RESET SIGNAL

3 von

g

,VDD

vss

:

vss

U.S. Patent

Apr. 1, 2008

Sheet 9 0f 25

US RE40,205 E

U.S. Patent

RESET F

Apr. 1, 2008

120g

E

1204

i

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Sheet 10 0f 25

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- -

-

. .

. _

.

_ _ _

US RE40,205 E

1203

. -_,'

i

U.S. Patent

Apr. 1, 2008

US RE40,205 E

Sheet 11 0f 25

VARIABLE DELAY

EXTCLK‘

.

CIRCUIT DIVIDE-BY EIGHT FREQUENCY CIRCUIT

, "VARIABLE DELAY

CIRCUIT

.'

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COMPARISON

ggh’IIaoL

.

.

-

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DUMMY DELAY CIRCUIT CORRESPONDING TO INPUT CLOCK BUFFER TO

I <" E :

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PHASE

PHASE COMPARISON SIGNAL

COMPARATOR 5

E P '

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S'GNAL

UTPUT BUFFER) .

5

j 5

I PHASE

L

_

DUMMY DELAY CIRCUIT

CONTROL SIGNAL

DELAY CONTROL CIRCUIT

CORRESPONDING TO INPUT CLOCK UFFER TO OUTPUT BUFFER)

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-

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U.S. Patent

5.mPU9

Apr. 1,2008

Sheet 12 or 25

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US RE40,205 E

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Apr. 1, 2008

Sheet 13 0f 25

US RE40,205 E

2 M Eu 8 a 5 i 2 % 8 Q m 0 6 Z 2 w E 5 s : m O i . Q 625éz8wm:a z6.o2ck:mwz6. 65M2%5:8 w5U2za%é.:o [email protected] >“8Q:6589 .w2_m<6z5 25m9m Eu2 9m 35

U.S. Patent

Apr. 1,2008

Sheet 14 or 25

US RE40,205 E

FIG. 23

2g n 4|__ "nV "PC

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Apr. 1, 2008

Sheet 15 0f 25

US RE40,205 E

D LVm T

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un. “r . ._ ..

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U.S. Patent

Apr. 1, 2008

Sheet 17 0f 25

US RE40,205 E

FIG. 28 CLOCK SIGNAL

(1502)

-.

SMS WNélu 3w.U ms. UH0 WGG AMEDIEum5

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Apr. 1, 2008

Sheet 18 0f 25

US RE40,205 E

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U.S. Patent

Apr. 1, 2008

Sheet 19 0f 25

US RE40,205 E

FIG. 31 EXTERNAL CLOCK

SIGNAL EXTCLK

I

_|

I

i

(319)

:

TIMING SIGNAL

I

ENABLE SIGNAL PULSE F0 W-UP REQUEST NAL

;

GENERATION

E f

-

.

'



I

E

i E

§ E

(I

(101)

TIMING SIGNAL REQUEST SIGNAL

-

§ i

:



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5

c

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i

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f

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in I:

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(320)

PULSE ATTAINMENT E PREDICTION SIGNAL (321)

SIGNAL INTERNALINTCLK CLOCK(102); td+tdriep

I 0

I

FIRST PHASE







c PAR TIMING; SIGNAL (313) I E

I E

I 3

I}, III

I E

PHASE COMPARISON;

I

I

51

I

i

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coMPARING TIMING I

SIGNAL HAVING PASSED THROUGH DE LooP

i 5 I

GIR

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5

T (314)

ND

ASE

SIGNAL (315)

i

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Semiconductor device and timing control circuit

Jul 31, 2001 - Foreign Application Priority Data. Jun. ... 327/161. See application ?le for complete search history. (56) ..... n 1 H"Mm, InE D V.Rn u .L: ..F nS'u.

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