RESEARCH ARTICLE Advanced Science Letters

Copyright © 2016 American Scientific Publishers All rights reserved Printed in the United States of America

Vol. 22, 3662–3666, 2016

2048-Point Fast Fourier Transform Processing Based on Twiddle Factor Reduction and Dynamic Data Scaling Bang Chul Jung1 ∗ , Choul-Young Kim1 , Hyoungho Ko1 , and Ji-Hoon Kim2 1 2

Department of Electronics Engineering, Chungnam National University, Daejeon, 34134, Republic of Korea Department of Electrical and Information Engineering, Seoul National University of Science and Technology, Seoul, 01811, Republic of Korea

In this paper, we present a new fast Fourier transform (FFT) algorithm to reduce the table size of twiddle factors required in pipelined FFT processing. The proposed algorithm can reduce the table size to half, compared to the radix-22 algorithm, while retaining the simple structure. In addition, a new dynamic data scaling approach is presented to reduce hardware complexity without degrading signal-to-quantization-noise ratio (SQNR). To verify the proposed algorithm, a 2048-point pipelined FFT processor is designed using a 0.18 m CMOS process. By combining the proposed algorithm and the radix-22 algorithm, the table size is reduced to 35% and 53% compared to the radix-2 and radix-22 algorithms, respectively. The FFT processor occupies 1.95 mm2 and achieves SQNR of more than 55 Delivered dB without increasing the internal wordlength by Ingenta to: Ji-Hoon Kimprogressively using the proposed dynamic data scaling. IP: 117.17.198.113 On: Mon, 13 Feb 2017 10:51:34

Copyright: American Scientific Publishers Keywords: FFT (Fast Fourier Transform), Pipelined Processing, Data Scaling.

1. INTRODUCTION The fast Fourier transform (FFT) is a major signal processing block being widely used in communication systems, especially in orthogonal frequency division multiplexing (OFDM) systems such as digital video broadcasting, digital subscriber line and WiMAX (IEEE 802.16). As such a system requires large-point FFT computation for multiple carrier modulation, usually more than 1024 points, it is desirable to reduce computational complexity as well as hardware complexity. To reduce the computational complexity, various FFT algorithms have been proposed such as radix-22 , radix-23 as well as radix-2 and radix-4 algorithms.1 2 Although the previous algorithms could reduce the computational hardware resources such as multipliers and adders, they did not seriously take into account the number of twiddle factors to be stored into tables. In the implementation of a large-point FFT processor, however, the tables become large enough to occupy significant area and power consumption.3 In this paper, a new FFT algorithm is proposed to overcome the problem of the large table requirement, which not only reduces the table size by a factor of two compared to radix-22 algorithm but also retains the simple structure of radix-2 algorithm. Since additional computations incurred by applying the proposed algorithm can be implemented with a few adders, ∗

Author to whom correspondence should be addressed.

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Adv. Sci. Lett. Vol. 22, No. 11, 2016

the overall computational complexity is almost the same as that of radix-22 algorithm. When a fixed-point representation is employed to implement a FFT processor, the wordlength has a significant influence on the accuracy and dynamic range. Although a long wordlength is required to achieve high signal-to-quantization-noise ratio (SQNR), it results in a large hardware complexity as the word sizes of memories and computational units such as complex multipliers and complex adders should be increased in proportion to the wordlength.4 An efficient dynamic data scaling technique is also presented in this paper to lower the hardware complexity without degrading SQNR.

2. PROPOSED FFT ALGORITHM The proposed algorithm can be derived by applying the Cooley and Tukey radix-2 decimation-in-frequency (DIF) decomposition two times.5 The N -point Discrete Fourier Transform (DFT) of a sequence xn is defined as Xk =

N −1 n=0

xnWNkn 

0≤k
(1)

where xn and Xk are complex numbers. The twiddle factor is defined as follows.     2kn 2kn WNkn = e−j2kn/N  = cos − j sin (2) N N 1936-6612/2016/22/3662/005

doi:10.1166/asl.2016.7918

RESEARCH ARTICLE

Adv. Sci. Lett. 22, 3662–3666, 2016

The two decompositions can be expressed if n and k are replaced with 3-dimensional linear index maps shown below. N N n + n + n2 2 1 4 2 k = k1 + 2k2 + 4k3

n=

If n3 is odd (= 2m + 1), the sum becomes     N N /4n2 +n3 k1 n + n3  k1 WN B 4 2 n2 =0 1 

(3)

N /4n +n 2k +4k 

2 3 2 3 × WN    N k1 k1 k2 k1 = WN Bn3  k1  + −1 −j WN B n3 +  k1 4

Using the above index maps, Eq. (1) can be rewritten as

N /2n1 +N /4n2 +n3 k1 +2k2 +4k3 

=

N /4n2 +n3 2k2 +4k3 

× WN

=

N /4−1



n3 =0



(4)

where B· represents the following butterfly structure.  N n2 + n3  k1 4     N N N =x n2 + n3 + −1k1 x n2 + n3 + 4 4 2

 B

(7)

Xk = Xk1 + 2k2 + 4k3 

    N N /4n2 +n3 k1 n2 + n3  k1 WN B 4 n2 =0

1  

n3 =0

4n3 k3

WN

where m is an integer between 0 and N /8 − 1. By substituting Eqs. (6) and (7) to Eq. (4), we obtain the following expression.

× WN N /4−1

2mk1 +2k2 

2k

· WN 2 WN

Xk = Xk1 + 2k2 + 4k3    N /4−1 1 1    N N = x n1 + n2 + n3 2 4 n3 =0 n2 =0 n1 =0

(5)

2mk1 +2k2 

Hk1  k2  n3 WN

 N − pointDFT 4

4n3 k3

WN

(8)



In (8), the expression of H· also depends on the value of n3 . For even n3 , H· is expressed as   N Hk1  k2  n3  = Bn3  k1  + −1k2 −jk1 B n3 +  k1 (9) 4

If n3 is odd, then H· is arranged below. The main idea of the proposed algorithm is to take into account Delivered by Ingenta to: Ji-Hoon Kim k the value of n3 in the summation of n2 . For even n3 = 2m, the k k2  n3 10:51:34 = WN1 Bn3  k1  + −1k2 −jk1 WN1 B IP: 117.17.198.113 On: Mon, 13 Hk Feb1 2017 sum is arranged as follows. Copyright: American Scientific Publishers   N 2k     1 + (10)  k × n · WN 2  N 3 N /4n2 +n3 k1 4 1 n2 + n3  k1 WN B 4 n2 =0 As k1 is either 0 or 1, Eq. (9) indicates that the butterfly has N /4n2 +n3 2k2 +4k3  × WN a trivial multiplication of −j at the input side if n3 is even,    and Eq. (10) implies that an additional constant multiplication N = Bn3  k1  + −1k2 −jk1 B n3 +  k1 of WN1 is required at the input side if n3 is odd. By performing 4 the constant multiplications at the input side, all the exponents 2mk +2k  2k 2mk +2k  4n3 k3 2mk1 +2k2  in the twiddle factors WN 1 2 and WN 2 · WN 1 2 to be WN (6) × WN

x[0] x[1] x[2] x[3] x[4] x[5] x[6] x[7] x[8] x[9] x[10] x[11] x[12] x[13] x[14] x[15]

-j W2 W4 W6 W1 W2 W3 -j -j -j -j

-j

-j

W3 W6 W9

-j

X[0] X[8] X[4] X[12] X[2] X[10] X[6] X[4] X[1] X[9] X[5] X[13] X[3] X[11] X[7] X[15]

x[0] x[1] x[2] x[3] x[4] x[5] x[6] x[7] x[8] x[9] x[10] x[11] x[12] x[13] x[14] x[15]

Even & Odd Exponents

(a) Fig. 1.

-j W2 W4 W6

-j

W2 W2

-j

W2 W6 W8

-j

W1 W1 -j -jW1 -j -jW1

X[0] X[8] X[4] X[12] X[2] X[10] X[6] X[4] X[1] X[9] X[5] X[13] X[3] X[11] X[7] X[15]

Only Even Exponents

(b)

Signal flow graphs of 16-point FFT. (a) Radix-22 algorithm and (b) proposed algorithm.

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multiplied in Eq. (8) become even values, while the exponents of the twiddle factors in other FFT algorithms such as radix-2, radix-22 , and radix-23 have both even and odd values. Compared to the radix-22 algorithm, the proposed algorithm associated with only even exponents reduces the size of twiddle factor table by half at the cost of an additional constant multiplier per two stages, as shown in Figure 1 that illuminates the signal flow graphs of 16-point FFT corresponding to the radix-22 algorithm and the proposed algorithm.

Overflow Detection Unit

n+1

n+1

INre al



OV



OUTre al

0

Complex Multiply

n >> 1

n+1

n+1

INimag Re 12

OV



1



n >> 1

1

WN(n)

3. DYNAMIC DATA SCALING

OUTimag

0

Im 12

OV

(a)

As a butterfly contains an adder and a subtractor, one bit should Ove rflo w De te c tio n Unit be increased in the result to avoid overflow, increasing the hardware complexity of memories and computational units. The simTwo plest way to avoid the increase of the internal wordlength is MSBs XOR to scale down the output value of each stage to half. If all the OV OR internal wordlengths are set to the wordlength of input, however, XOR the resulting SQNR is very low because of severe information loss. To achieve a SQNR enough to meet the standard specificaTwo n+1 n+1 tion, therefore, this approach needs an internal wordlength that MSBs is much longer than the input wordlength, increasing the overall Re al Imag hardware complexity significantly. (b) Another data scaling approach is to dynamically scale the Fig. 3. Proposed dynamic scaling technique. (a) Dynamic scaling. (b) Overinternal wordlength. One of the approaches is the block floatflow detection. ing point (BFP) method.6 When a pipelined architecture is used, however, the BFP method is not suitable because of its huge overflow occurs in the computation, and tagging this information latency to normalize all outputs from a certain stage. Instead, a on the internal word. We examine the output value of a complex method called convergent block floating point (CBFP) has been multiply unit toKim check whether it can be represented in n bits or in Figure 2, proposed for pipelined architectures.7 As shown Delivered by Ingenta to: Ji-Hoon not13asFeb shown in Figure 3(a). The overflow can be easily detected 117.17.198.113 2017 10:51:34 the CBFP method also suffers fromIP: large memory overheadOn: and Mon, Copyright: Publishers by performing an Exclusive-OR operation for two most signifincreased latency caused by the intermediate buffer asAmerican well as Scientific icant bits (MSBs) shown in Figure 3(b). If overflow occurs in complex normalization. Furthermore, the intermediate buffer in either the real value or the imaginary value, both the real value the CBFP logic has to store full-precision values because the norand the imaginary value is scaling down to half, which leads to malization can be performed after the scaling factor is known.8 Although a data scaling method that does not need additional less hardware complexity. buffers and latency has been proposed, it still requires the comThe internal word format of the proposed dynamic scaling plex normalization that should be implemented with a number of method is shown in Figure 4(a). The data field in the intercompare and shift units connected in series at the output of each nal word format is to represent the scaled data value, and the stage.9 tag field is to indicate how many times the scalings are applied The proposed data scaling technique is based on an observation from the original input values to generate the corresponding data. that there is no need to scale down the internal value if overflow If the proposed data scaling method is applied to the L-th stage, does not occur in computing the value. Even if overflow occurs, at most log2 L bits are enough for the tag field. Therefore, scaling down to half, which can be achieved by a simple operation of 1-bit right shift, is all to accommodate the overflow. Based n-bits n-bits m-bits on this observation, we present an efficient dynamic scaling techtag data (real) data (imag) nique. The main idea of the proposed algorithm is to condition(a) ally scale down the output value of a complex multiplication if IN1 IN2

n+13

INre al

Complex Multiply

n+1

n+13 Intermediate Buffer

n+13

INimag

IN1 tag

Next Stage

IN2 tag

m

Im 12

WN(n)

Fig. 2. CBFP logic in a pipeline stage.

0



m

m

• + – ADD diff

Re 12

3664

n+13

Normalization

CBFP Lo g ic n+1

data

Shift Amount

Max. tag

diff – diff

data •



diff sign

0



1

diff sign

diff sign

(b)

0

Shifter 1 •

0

1 n

0

1 n

diff s ig n

Butte rFly Unit

• m

1

n+1

To Co mple x Multiplier

n+1

To FIFO

(c)

Fig. 4. Proposed processing unit. (a) Internal word format. (b) Tag processing. (c) Data processing.

RESEARCH ARTICLE

Adv. Sci. Lett. 22, 3662–3666, 2016

the number of bits in the tag field increases gradually in log scale. In general, the two data words participating in a butterfly computation have different tag values. As shown in Figures 4(b and c), the difference of the two tag values is calculated first, and then one data word with the smaller scale is shifted by the difference to make the scales of two data words equal. The tag value of the output word of a butterfly computation is initially set to the larger tag of the two input words. After the complex multiplication is completed, the output tag value is increased by one if overflow is detected. At the final pipeline stage of N -point FFT, each output has the different tag value in general because each value experiences a different number of scalings. To obtain appropriate precision, the output is scaled up by the amount of the corresponding tag value. As the proposed conditional scaling technique makes the internal wordlength short, it leads to a lower hardware complexity without severe information loss.

4. PROPOSED 2048-POINT PIPELINED FFT

Table I. Complexity of constant multipliers. Constant operand

MSD representation

cos2/2048 sin2/2048 cos2/512 sin2/512

1000000000000 0000000001100 1000000000000 0000000110010

is not increased notably but the costs of multipliers and tables are increased significantly.4 The complexity of the constant multiplier depends on the number of non-zero bits in the binary representation of the constant. To minimize the number of non-zero bits, the constants are expressed in the minimal signed digit (MSD) representation, as shown in Table I. Due to the sparse non-zero bits in the sine and the cosine values, the constant multipliers can be implemented with a few adders. By employing these two simple constant multipliers, we can reduce the required sizes of two largest tables to half. As the two tables takes more than 75% of the total table sizes required in the radix-22 algorithm, the reduction plays a significant role in lowering the overall complexity of the 2048-point FFT processor.

In pipelined DIF FFT processing, the twiddle factor table is largest at the first stage and reduced by a factor of two at the successive stages. Reducing the table sizes at the first several stages can be significant because the original table sizes are large 5. IMPLEMENTATIONS enough to pay off the additional constant multipliers. The reducWe should the format of Sensor Letters. The hardware complextion is not considerable, however, at the latter stages. At each ities required in the proposed algorithm and the previous algopipeline stage, we have to decide whether to apply the proposed rithms are compared in Table II for the case of 2048-point FFT. algorithm or not with considering both the cost of the additional The required table size indicates the total number of entries of Delivered by Ingentathe to:ROM Ji-Hoon constant multiplier and the table size reducible by the proposed tables.Kim The /2 symmetric property of the twiddle facIP: 117.17.198.113 On: 13isFeb 2017 10:51:34 algorithm. When the cost of the additional constant multiplier is Mon, tors considered in counting the table size. We can reduce the Copyright: American not compensated by the table reduction at a certain stage, the Scientific table size Publishers further if we employ the /4 symmetric property. As radix-22 algorithm should be applied from that stage to the last the reduction ratio is independent of what symmetric property is stage. used, the reduction ratio shown in Table II also applies to the By combining the proposed algorithm with radix-22 algocase of /4 symmetry. As indicated in Table II, the proposed rithm, we designed a 2048-point pipelined FFT processor of algorithm needs the minimal table size compared to other algowhich Single-path Delay Feedback (SDF) structure is shown rithms and the overhead is just two constant multipliers which in Figure 5.1 The overall table size can be reduced to almost can be implemented with a few adders. half, compared to the structure that uses only radix-22 algorithm, Assuming that the input is represented in 12 bits, we comby applying the proposed algorithm to the first four stages. In pare four scaling schemes shown in Table III. Table IV shows this case, two constant multipliers are required to compute nonthat the internal wordlength configurations and SQNR perfor1 1 and W512 . In implementing the trivial multiplications by W2048 mances resulting from the scaling methods. If no scaling is used, 2048-point FFT processor, the wordlength of the twiddle factors the wordlength is increased progressively, one bit per stage to is set to 12 bits by performing several simulations. The longer twiddle factors are not cost efficient, as the SQNR performance Table II. Hardware complexity comparison for 2048-point FFT. C : Constant Multiplier

Proposed Algorithm

: General Multiplier 1024 x[n]

BF

512 C

256

BF

1 W2048

BF

C

FIFO

Wi(n) : Twiddle factor Table

BF

1 W 512

W1(n)

:

128

W2(n)

FFT algorithm

Constant multiplier

General multiplier

Radix-2 Radix-22 Radix-23 Proposed

0 0 3 2

10 5 4 5

Required table size 1023 682 584 362

(100%) (66.7%) (57.1%) (35.4%)

Radix-22 Algorithm

Table III. Scaling configurations. X[k]

1

2

4

8

16

32

64

BF

BF

BF

BF

BF

BF

BF

W5(n)

W4(n)

W3(n)

Fig. 5. SDF pipeline architecture of the proposed 2048-point FFT processor.

Case I II III IV

Scaling method Always scaling-to-half No scaling + scaling-to-half Proposed dynamic scaling always No scaling + proposed dynamic scaling

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Table IV. SQNR and internal wordlength of computational units. Stage Number Case

1

2

3

4

5

6

7

8

9

10

11

SQNR (dB)

I II III IV

12 12 12 12

12 13 12 13

12 14 12 13

12 15 12 13

12 16 12 13

12 17 12 13

12 18 12 13

12 19 12 13

12 19 12 13

12 19 12 13

12 19 12 13

18.9 56.1 51.2 55.8

Table V. Memory requirement for 2048-point FFT. Scaling method Convergent block floating point (CBFP) Proposed dynamic scaling

FIFO memory requirement

Intermediate buffer requirement

2047

2046

2047

0

implemented using RAM memories, and small-sized RAM and ROM memories are replaced with registers and logic circuitry, respectively.

6. CONCLUSIONS We should the format of Sensor Letters. We have proposed a new FFT algorithm to reduce the size of twiddle factor tables and an efficient dynamic scaling method to lower overall hardware complexity in the implementation of large-point pipelined FFT processors. By applying the proposed FFT algorithm to the first several stages, the table size required in pipelined FFT processing is reduced approximately by half at the cost of a few simple constant multipliers compared to the radix-22 algorithm. Since the constant multipliers can be implemented by a few adders, the proposed algorithm is efficient in large-point FFT computation, especially in terms of area and power consumption. Based on the proposed FFT algorithm, we can design a 2048-point pipelined FFT processor that reduces the total size of twiddle factor tables to 35% and 53% compared to the radix-2 and radix-22 algorithms, respectively. In addition, the proposed dynamic scaling technique enables the proposed processor to achieve SQNR of more than 55 dB without increasing the internal wordlength progressively.

avoid overflow. On the contrary, both the proposed dynamic scaling technique and the scaling-to-half method maintain the internal wordlengths constant. As denoted in Table IV, the proposed dynamic scaling technique (case III) can improve SQNR impressively, about 30 dB improvement, compared to the scaling-to-half method (case I) although those two configurations have similar hardware complexity. If the first stage is allowed to extend one Acknowledgments: This study was supported by the bit as in case IV, we can obtain a SQNR performance of more Research Program funded by the Seoul National University of than 55 dB using the proposed dynamic scaling technique. To Science and Technology. achieve a SQNR of more than 55 dB by progressively increasing the internal wordlength, the wordlength should be lengthened to Ingenta to: Ji-Hoon Kim 19 bits, leading to huge hardware complexityDelivered at the latterby stages Notes IP: 117.17.198.113 On: Mon,References 13 Feb 2017and 10:51:34 as in case II. 1. S. He and M. Torkelson, Design and implementation of a 1024-point pipeline Copyright: American Scientific Publishers Compared to the CBFP method that requires additional buffers FFT processor, Proceedings IEEE Custom Integrated Circuits, Conference to store a group of values to be normalized, the proposed (1998), pp. 131–134. 2. S. He and M. Torkelson, Designing pipeline FFT processor for OFDM dynamic scaling method requires less memory as well as less (de)modulation, Proceedings IEEE URSI International Symposium Signals, computational delay. Table V shows memory sizes required to System Electron. (1998), pp. 257–262. process 2048-point FFT. The memory requirement indicates the 3. W. Li and L. Wanhammar, A pipeline FFT processor, Proceedings IEEE Worktotal sizes of FIFO memories and intermediate buffers. The memshop on Signal Processing Systems (1999), pp. 654–662. 4. S. Johansson, S. He, and P. Nilsson, Wordlength optimization of a pipelined ory overhead resulting from the CBFP method is enormous, as FFT processor, 42nd Midwest Symposium on Circuits and Systems (1999), the full-precision values should be stored in intermediate buffers pp. 501–503. and the size of the buffers is comparable with that of the FIFO 5. J. W. Cooley and J. W. Tukey, Math. Computation 19, 297 (1965). 6. Y. W. Lin, H. Y. Liu, and C. Y. Lee, IEEE J. Solid-State Circuits 39, 2005 (2004). memories. In addition, the latency is also increased considerably 7. E. Bidet, D. Castelain, C. Joanblanq, and P. Senn, IEEE J. Solid-State Circuits by the intermediate buffers. 20, 300 (1995). We designed a 2048-point pipelined FFT processor using 8. J.-R. Choi, S.-B. Park, D.-S. Han, and S.-H. Park, A 2048 complex point FFT architecture for digital audio broadcasting system, Proceedings of IEEE Intera 0.18 m 4-Metal CMOS process. The internal wordlengths national Symposium on Circuits and Systems (2000), pp. 693–696. are configured as indicated in case IV in Table III. The pro9. T. Lenart and V. Owall, A 2048 complex point FFT processor using a novel data 2 posed FFT processor occupies 1.95 mm and the gate count is scaling approach, Proceedings of IEEE International Symposium on Circuits 75,809 excluding memories and ROMs. The FIFO buffers are and Systems (2003), pp. IV-45–IV-48. Received: 15 February 2016. Accepted: 10 March 2016.

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RESEARCH ARTICLE 2048-Point Fast Fourier ...

2Department of Electrical and Information Engineering, Seoul National University of Science and Technology,. Seoul, 01811, Republic of Korea ... FFT computation for multiple carrier modulation, usually more than 1024 points, it is desirable to ...

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