USO0RE43 870E

(19) United States (12) Reissued Patent

(10) Patent Number: US RE43,870 E (45) Date of Reissued Patent: *Dec. 25, 2012

Lee et a]. (54)

7,016,226 B2 7,064,980 B2

REDUCING THE IMPACT OF INTERFERENCE DURING PROGRAMMING

(75) Inventors: Dana Lee, Milpitas, CA (US); Emilio

Yero, Milpitas, CA (US)

(Us) (*)

Notice:

7,073,103 B2

7/2006 Gongwer

7,110,276 B2

9/2006 Park

7,139,192 B1

11/2006 Wong

7,221,589 B2 7,260,016 B2

5/2007 Li 8/2007 Kouno

7,580,290 B2 7,630,249 B2

(73) Assignee: SanDisk Technologies Inc., Plano, TX This patent is subject to a terminal dis claimer.

3/2006 Shibata 6/2006 Cernea

7,869,273 2005/0207259 2006/0004952 2006/0164890

B2 A1 A1 Al*

8/2009 Fong 12/2009 Fong 1/2011 Lee 9/2005 Kouno l/2006 Lasse 7/2006

Lee ........................ .. 365/185.28

(Continued) (21) Appl.No.: 13/289,108 (22) Filed:

OTHER PUBLICATIONS

Nov. 4, 2011

International Search Report dated Dec. 16, 2008, PCT Appl. No. PCT/US2008/074621, ?led Aug. 28, 2008.

Related US. Patent Documents

Reissue of:

(64) Patent No.:

(51) (52) (58)

(Continued)

7,869,273

Issued:

Jan. 11, 2011

Primary Examiner * Connie Yoha

Appl. No.: Filed:

11/849,992 Sep. 4, 2007

DeNiro LLP

Int. Cl. G11C 16/04

(74) Attorney, Agent, or Firm *Vierra Magen Marcus &

(57) ABSTRACT A system for programming non-volatile storage is proposed

(2006.01)

US. Cl. ....... .. 365/185.02; 365/185.22; 365/185.23;

that reduces the impact of interference from the boosting of

365/230.04 Field of Classi?cation Search ........... .. 365/185.02,

neighbors. Memory cells are divided into tWo or more groups. In one example, the memory cells are divided into odd and

365/185.22, 185.23, 230.04 See application ?le for complete search history.

used. Prior to a ?rst trigger, a ?rst group of memory cells are

(56)

References Cited U.S. PATENT DOCUMENTS 6,118,696 A *

9/2000

6,523,132 B1

2/2003 Harari

Choi ...................... .. 365/185.11

6,882,567 B1

4/2005 Wong

6,888,758 B1 6,937,520 B2 6,956,770 B2

5/2005 Hemink 8/2005 Ono 10/2005 Khalid

6,967,872 B2

11/2005 Quader

even memory cells; however, other groupings can also be

programmed together With a second group of memory cells. Subsequent to the ?rst trigger and prior to a second trigger, the ?rst group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the ?rst group of memory cells are programmed together With the second group of memory cells. Before and after both triggers, the ?rst group of memory cells are veri?ed together With the second group of memory cells.

49 Claims, 18 Drawing Sheets S91 magnitude Of inilial Vpgm and 591 PC = 1

ye.

step Vpgm and increment PC 522

yes 524 additional

lockout

apply program pulse, program we 111mm

US RE43,870 E Page 2 US. PATENT DOCUMENTS 2006/0193176 2006/0245269 2006/0250850 2006/0291291

A1 A1 A1 A1

2009/0285023 A1*

8/2006 11/2006 11/2006 12/2006

Li Martines Lee Hosono

11/2009

Cho et al. ............... .. 365/185.03

2010/0046301 A1

2/2010 Fong

2011/0075477 A1

3/2011 Lee

OTHER PUBLICATIONS

Of?ce Action dated May 6, 2010, US. Appl. No. 11/849,922. Response to Of?ce Action dated Sep. 7, 2010, US. Appl. No.

11/849,922. Notice ofAlloWance dated Sep. 16, 2010, US. Appl. No. 11/849,922. Notice ofAlloWance dated May 26, 2011,U.S.Appl.No. 12/962,902. Notice ofAlloWance dated Sep. 20, 2011,U.S.Appl.No. 12/962,902. US. Appl. No. 13/221, 147, ?led Aug. 30, 2011. Of?ce Action dated Oct. 18, 2011, US. Appl. No. 13/221,147. Response to Of?ce Action dated Nov. 1, 2011, US. Appl. No.

13/221,147. Written Opinion of the International Searching Authority dated Dec. 16, 2008, PCT Appl. No. PCT/US2008/074621, ?led Aug. 28,2008. International Preliminary Report on Patentability dated Mar. 9, 2010, PCT Appl. No. PCT/US2008/074621, ?ledAug. 28, 2008, with Writ ten Opinion of the International Searching Authority dated Dec. 15, 2008, PCT Appl. No. PCT/US2008/074621, ?led Aug. 28, 2008.

Supplementary European Search Report, dated Aug. 12, 2010, Euro pean Patent Appl. No. EP 08829629.

Response dated Mar. 15, 2011, European Patent Appl. No. EP 088296298.

European Of?ce Action dated Aug. 5, 2011, European Patent Appl. No. EP 088296298.

Of?ce Action dated Jan. 4, 2010, US. Appl. No. 11/849,922. Response to Of?ce Action dated Feb. 4, 2010, US. Appl. No. 1 1/ 849,922.

Notice ofAlloWance dated Feb. 24, 2012, US. Appl. No. 13/221,147. Chinese Of?ce Action dated May 21, 2012, Chinese Patent Appl. No. 2008801145674.

Taiwan Of?ce Action dated Sep. 19, 2012, Taiwan Patent Appl. No. 097133784.

International Preliminary Report on Patentability dated Mar. 9, 2010, PCT Appl. No. PCT/US2008/074621, ?led Aug. 28, 2008. Written Opinion of the International Searching Authority dated Dec. 15, 2008, PCT Appl. No. PCT/US2008/074621, ?led Aug. 28,2008. Fong, et al., US. Appl. No. 11/766,583, ?led Jun. 21, 2007. Fong, et al., US. Appl. No. 11/766,580, ?led Jun. 21, 2007. Supplementary European Search Report, dated Aug. 12, 2001, Euro pean Patent Appl. No. EP 08829629.

* cited by examiner

US. Patent

Dec. 25, 2012

Sheet 2 0f 18

US RE43,870 E

Data

t I/O COLUMN DECODER 2425

CONTROL CIRCUITRY

ADDR

READ/WRITE CIRCUITS 230B Sense Sense P‘ 300 Block Block 1 2

>mQOwWm_Q ADDRI 4

>MmoOwWM_

MEMORY ARRAY 200

READ/WRITE CIRCUITS 2M Sense Block .1

ADDR

Sense Block D

Sense Block 2

A 300

Sense Block D

COLUMN DECODER 242A AL Data l/O

Controller

2%

US. Patent

Dec. 25, 2012

Sheet 3 0f 18

block 0

US RE43,870 E

Fig. 4

block 1

block 2 \f 200

block 3

block i

block ‘I023 block i

BLO

BL1

BL2

IJ

BL3

BL4

BL5

“J

BL69,622 BL69,623

IJ

b

1

source

US. Patent

Dec. 25, 2012

Sheet 4 0f 18

300

US RE43,870 E

bit line

480 _ _ _J_ __________________ _ _ 2

l l l l l

Core

—> I

|

"

|

j

470 | | |

—>

I I

A

State Machine

I

| | | | State Machine

:

Bitline Latch

I l l

4

470

482

l l l l

Processor

I

l

| | |

l l l

493

A

l

V

: | | | | | | |

I Data Latches 494

492

|

: l l l l l l l

common

420

" Data

Fig. 5

US. Patent

Dec. 25, 2012

US RE43,87 0 E

Sheet 5 0f 18

Fig 6 number of cells

A M VT

Fig. 9 H

550

pre-program block V

/-/ 55

2

erase block

v

H 554

soft program block "

/_J 556

program memory cells in block

Hg 8 WLO WLl WL2 WL3

First Page

Second Page

Third Page

1 2 4 7

3 5 8 10

6 9 11 12

US. Patent

Dec. 25, 2012

Sheet 6 0f 18

US RE43,870 E

number of cells

A

[Q1

Fig. 7A

#1

504 -/\

502

111

911

VT

number of cells

m

502

504

78%

Fig. 7B

Fig. 7C 506

I101

C*

number Cells of 502

30

T T011

E**

E*

536

m

Q

—>

E1:

OO A

6*

508

510

34

86

T 0*

V

r 6*

VT

US. Patent

Dec. 25, 2012

numberof cells

Sheet 7 0f 18

US RE43,870 E

numberof cells

111

T110 VT B

numberof cells

numberof cells

508 A

T T011 E*

numberof

cells

Q 111

Fig. 7|

T110 T101 T100 T011 T010 T001 T000 VT B OP

US. Patent

Dec. 25, 2012

Sheet 8 0f 18

US RE43,870 E

set magnitude of initial Vpgm and set /\- 608 PC = 1

i

Fig. 10

_ apply program pulse, N 610 7 program all bit lines

"

/ 612

Verify

:

616

verify status?

630

unsuccessfully programmed memory cells 5 predetermined number?

620

yes

632

step Vpgm and increment PC

status I

pass /—/ 622

no A

634 status = fail

yes 624 additional lock-out conditions

626

low?

F’

apply program pulse. program even bit lines

//

apply program pulse, program odd bit lines

628

US. Patent

Dec. 25, 2012

805

Sheet 9 0f 18

US RE43,870 E

Fig. 11A 802

two/E @806 808

Fig. 115

808

804

Fig. 110

US. Patent

Dec. 25, 2012

Sheet 10 0f 18

US RE43,870 E

www w?E“NE8

NEownwk0RwkNEon

Nwww

m?.mE

ER8

US. Patent

Dec. 25, 2012

Sheet 11 0f 18

US RE43,870 E

Fig. 14

70a

720

Fig. 15 730 732 722

724

726

verify pulses A

728

verify pulses A

US. Patent

Dec. 25, 2012

Sheet 12 0f 18

US RE43,87 0 E

Hg. 16 Bit lines Precharge

I

& Boosting

5(1)

(2)

SGS

(4)

.

D|s
(5)

i

VPAss VPGM

I

0v

5 SGD

(3)

Program

:

WL_unsel WL_sel VS

v

\ 56

V1.4v

BL inhibit

:

/ VDD

BL pgm

f

\ 0v

V.»

H’Ch nnel Boostin eniablec ‘ '

US. Patent

Dec. 25, 2012

Sheet 13 0f 18

US RE43,870 E

Fig. 1 7 compare each

850

memory cell to its /

neighbors count number X of _

_

_

potential transitions //

852

into lockout condition

854 no

yes

chance of additional lock-out conditions is low

chance of additional lock-out conditions is not low

Hg. 1 8 Data Latches 494

I .

/ 880

/ 882

.

Bit

shift register

1

888

State Machine

Accumulator

886

/ 884 —

Bit

O

US. Patent

Dec. 25, 2012

US RE43,87 0 E

Sheet 14 0f 18

Fig. 19 count number of memory cells still

/ 902

being programmed

less than threshold?

/ 906

/ 908

chance of additional lock-out conditions is low

chance of additional lock-out conditions is not low

Fig . 20 Processor 492

/ 920 Processor

492

comparator

Stat?

Machine

Processor 492

parameter

/ 922

US. Patent

Dec. 25, 2012

Fig. 21 V

v

Fig. 22 /1 050

// 1002

erase block

=

/1004

with odd columns always selected for programming, apply program pulses up to

erase block

w

/ 1052

with odd columns always selected for programming, program even columns to Vth of Vx

Vpgm_test

"

US RE43,87 0 E

Sheet 15 0f 18

/1006

"

/1054

measure Vth distribution for

store number of pulses

even columns

applied

"

r, 1008

erase block

W

,7

f, 1056

erase block

/1010

with odd columns always

W

/ 1058

inhibited, apply program

with odd columns always inhibited, program even

pulses up to Vpgm_test

columns to Vth of Vx

"

"

/1012

f, 1060

measure Vth distribution for

store number of pulses

even columns

applied "

/ 1062

compare measure Vth

compare measure number of

distributions for both tests

pulses for both tests

1016

1064

yes difference > threshold?

yes difference > threshold?

f/1018 increase Vpg m_test

/102O set trigger to Vpgm_test ‘

/1 O66 increase Vx

//1 068 set trigger to Vpgm_max ‘ from second test

US. Patent

Dec. 25, 2012

>

US RE43,87 0 E

Sheet 16 0f 18

erase block

1

/1104

with odd columns always

selected for programming, program even columns to

Vth of Vy

l

/1 106

measure number of over

programmed memory cells on even columns

l

/1 108

with odd columns inhibited,

apply next program pulse

l

/1

110

measure number of over

programmed memory cells on even columns

l/i

112

compare measure number of

over programmed cells for both measurements 1114

yes difference > threshold?

/1116 increase Vy

//1 118 set trigger to Vpgm_max <—

US. Patent

Dec. 25, 2012

Sheet 17 0f 18

US RE43,870 E

Fig. 24 /1240 perform X program/erase

cycles

l

/1242

raise trigger voltage

1

/1244

perform Y program/erase

cycles

1

/1246

raise trigger voltage

1 /1248 program program/erase cycles

Fig. 25 /1282

/1286

trigger

compensation

parameter

circuit

222 \ state machine

/1284 cycle parameter

US. Patent

Dec. 25, 2012

US RE43,87 0 E

Sheet 18 0f 18

Fig. 26 /1302 measure temperature

i

/ 1304

adjust trigger voltage

i

/1306

perform programming

Fig. 27

trigger parameter 222

compensation circuit

/1354

\ state machine

temperature sensor