Comments on “Reducing Register File Power Consumption by Exploiting Value Lifetime Characterisitics” by Zhigang Hu and Margaret Martonosi Aarul Jain CSE520: Advanced Computer Architecture, Fall 2007

Hu and Martonosi’s paper [1] argues that register file power consumption can be reduced by buffering results between functional units and register file and servicing data accesses from the buffer instead of the register file. In this note, main contributions and limitations of the paper are discussed. Contributions of the paper 1. The paper brings out a novel technique to reduce register file power consumption by taking advantage of lifetime characteristics of register values. The paper does a good work in explaining how lifetime characteristics of register values can be exploited and supports its argument with standard benchmark suite (SPECINT95). 2. The paper does a good work in explaining the impact on performance due to addition of Value Added Buffer (VAB) and justifies it by presenting statistics on power reduction achieved due to addition of VAB. 3. The paper discusses issues such as exception and misprediction that become more complex to handle with the VAB architecture. Limitations of the paper 1. The technique can be applied to superscalar processors however processors having shallow pipeline may not follow the lifetime characteristics as presented by authors. With the current trend towards multicores and having small and less complex cores, implementation of this technique may be overkill. 2. Debugging applications with the VAB architecture can be quite a challenge. The paper does not discuss how to handle debug requests. 3. Although the paper explains architecture level details of VAB and performance issues, micro-architecture implementation of VAB is not explained. For example, in [2] a similar technique is used but the authors explain the details more clearly. References [1] Z. Hu and M. Martonosi, “Reducing Register File Power Consumption by Exploiting Value Lifetime Characteristics,” Proc. Workshop Complexity-Effective Design, 2000. [2] G. Kucuk, D. Ponomarev and K. Ghose, “Low-Complexity Reorder Buffer Architecture,” Proc. Int. Conf. on Supercomputing, 2002.