Project Report Performance Analysis of low power high speed pipelined adders for Digital Delta Sigma Modulators Prof. Michael Peter Kennedy (Supervisor)

Prateek Bhansali (Author)

Dept. of Microelectronic Engineering University College Cork, Cork Ireland

Dept. of Electrical Engineering Indian Institute of Technology, Kanpur, India

The phase-locked loop (PLL) frequency synthesis technique is widely used to get accurately defined frequencies. It is a closed-loop feedback control system that generates and outputs a signal in relation to the frequency and phase of an input signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the output frequency (fout) of a controlled oscillator until it is matched to the reference (fref) in both frequency and phase. It is typically composed of phase-frequency detector (PFD), low pass filter (LPF), voltage controlled oscillator (VCO), frequency divider and digital delta-sigma( ΔΣ ) modulator (DDSM) for fractional frequency synthesis applications. A simplified block diagram of such a system is shown in Fig. 1.

The DDSM is utilized to modulate the instantaneous division ratio. The division ratio alternations take place in a random/pseudo-random fashion. The importance of DDSM lies in the fact that it pushes the phase noise and spurious contents to higher offset frequencies, where the already existing loop filter can easily cut them off. A digital implementation of the first order DDSM is shown in Fig. 2. The building blocks of a DDSM are adders and latches. In order to achieve higher operational speeds pipelined adders are employed in DDSM’s. Carry out bit K

X X+Y

Y Latch

fref

Phase Detector

fdiv

K

Loop Filter

VCO

fout

Multi Modulus Divider

Δ Σ

Fig.1: PLL frequency synthesis block diagram

Fig.2: First-order ΔΣ modulator The choice of different adder topologies directly affects area, power and glitch content (in carry out bit) and hence the performance. In this project, we analyze two adder topologies Carry Skip Adder (CSA) and Carry Lookahead Adder (CLA) for total power, glitch power and area occupied in the specific context of DDSM. The result and conclusions are presented in the manuscript

of the paper submitted to IEE Electronics Letter Journal. The present work can be extended by studying various other adder topologies and furthermore to the field of A/D and D/A conversion where ΔΣ modulators are extensively used. Enclosure: The manuscript of the paper.

Acknowledgments: The author would like to express sincere gratitude to Prof. Peter Kennedy, project advisor, for his guidance throughout the project. His invaluable suggestions and guidance helped in continuing the work in spite of the challenges involved. The author would also like to pay special thanks to Dr. Sverre Lidholm and Dr. Emanuel Popovici for providing their constant support. Also, the author is highly indebted to Mr. Kaveh Hosseini, for his constant motivation and sincere help.

Manuscript of the research paper Performance analysis of low power high speed pipelined adders for Digital Delta Sigma Modulators P. Bhansali, K. Hosseini and M. P. Kennedy Abstract: The Carry Skip Adder (CSA) is widely assumed to outperform the Carry Lookahead Adder (CLA) in terms of power and area. However, for pipelined adders used in Digital Delta Sigma Modulators (DDSM), we show that the CLA has similar performance to the CSA architecture when low bit blocks are used. Furthermore, the CSA outperforms the CLA in terms of glitch content and hence the CSA is more suitable for the operational frequencies of DDSMs.

The design of the adders used for comparison: A 16-bit adder was designed from 4-bit and 8-bit blocks with registers inserted in carryout signal path [5]. The 16-bit pipelined adder using 4-bit blocks is shown in Fig. 1.

Introduction: In a fractional-N frequency synthesizer, a digital delta sigma modulator (DDSM) is used to control the division modulus of a multimodulus divider that performs fractional division. The basic building blocks of DDSMs are adders and latches. In order to maximise the speed of high resolution DDSMs, pipelined adders are used [1]. In this Letter, we analyze the performance of pipelined modified variable sized carry skip adders (CSA) [2] and pipelined carry lookahead adders (CLA) and compare these in terms of total average power, area and glitch content using PrimePower [3] and Design Analyzer [4]. Background: The CLA is generally assumed to have better speed performance compared to the CSA, while the latter typically has lower power consumption and smaller area. In this Letter, we show that, in the specific context of DDSMs, where pipelining is used to increase the speed, the CSA outperforms the CLA, having almost the same power and area performance as CLAs, but with fewer glitches. To address the issue of hardware complexity and speed, adders are constructed from small adder modules with pipelining in the carry out signal [1].

Fig. 1 16-bit pipelined adder structure The alignment registers are used to synchronize the input, the carry-in and the output signals. The Partial Full Adder (PFA1) was constructed as shown in Fig. 2. The modified 4-bit variable width CSA [2] and 4bit CLA are shown in Figs. 3 and 4, respectively, using PFA1 as a sub-block.

Fig. 2

Partial full adder structure

The results of our comparison are shown in Table 1. Parameter

4-bit blocks CSA CLA Total Power (mW) 0.9528 0.9416 Glitch Power ( μW) 0.3705 0.6080 Area ( μm2 ) 40450.4 39397.6

8-bit blocks CSA CLA 0.8524 0.8422 0.6574 1.787 21144.0 18947.6

Table 1: Simulated results for 16-bit pipelined adder at 3.3 V and 5 MHz

Fig. 3

Fig. 4

4-bit Carry lookahead adder

4-bit modified carry skip adder

Performance Analysis: The 16-bit adder structures were simulated using 0.35 μm Austria Micro Systems libraries at 3.3 V supply voltage and a 5 MHz clock frequency using Synopsys PrimePower. The adder inputs were chosen to be random to reflect the DDSM application.

Note that the CSA consumes both greater power and area than its CLA counterpart. However, its glitch content is significantly less in both the cases, when 4-bit and 8-bit sub blocks are used. This is contrary to the widely held assumption that the CSA outperforms the CLA in terms of power and area. The reason for the difference is that we have used 4-bit or 8-bit adder blocks and random test vectors. The hardware complexity increases exponentially with the number of bits at the adder input [1]. Thus, the higher bit blocks are not favoured in high resolution DDSMs due to their increased hardware complexity. Hence, our application leads to fine graining of the structure. However, we lose the area and power advantages of CSA if the adder is fine-grained as well as pipelined. The overall carry-out signal of the DDSM is applied to the noise cancellation network in multistage noise shaping (MASH) structures and any glitch would lead to a wrong result. Glitch power is a direct indicator of the unwanted transitions [6], the CSA is therefore better from this point of view. Conclusion: We have analyzed the performance of low power high speed pipelined adders for Digital Delta Sigma Modulators. Due to fine-graining, the CLA has similar performance in terms of power and area consumption to the generally preferred CSA in this specific context. However, the CSA is better suited for high frequency DDSMs because of the significantly lower glitch content of its output.

References: [1] M. A. Kozak and I. Kale: ‘A pipelined noise shaping coder for fractional-N frequency synthesis’ IEEE Trans. Instrum. Meas., vol. 50, no. 3, pp. 1154-1161, Jun. 2001 [2] Yu, C.C., Lin, C.S., and Liu, B.D.: 'A generalized block distribution algorithm for fast carry-skip adder design', TENCON99. Proceedings of the IEEE Region 10 conference, Vol. 1, pp. 844-847, Sept. 1999 [3] The PrimePower Manual: The Synopsys Inc., 2006 [4] The Design Analyzer™ Reference Manual: The Synopsys Inc.,2002 [5] M. Perrot, T. Tewksbury, and C.sodini: ‘A 27 mW CMOS fractional-N synthesizer using digital compensation for 2.5 Mb/s GFSK modulation’, IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2059,Dec.1997

[6] Eriksson, H. and Larsson-Edefors, P. : ‘Glitch-conscious low-power design of arithmetic circuits’, Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS '04, Vol.2, pp. 281-284, May 2004 Authors' affiliations: P. Bhansali (Department of Electrical Engineering, Indian Institute of Technology, Kanpur, India) K. Hosseini and M. P. Kennedy (Department of Microelectronics, University College Cork, Cork, Ireland) E-mail: [email protected]