Quantum Information and Computation, Vol. 1, Special (2001) 108-112 © Rinton Press
FABRICATION OF THE STRUCTURE FOR QUBITS USING ELECTRONS ON LIQUID HELIUM JOHN M. GOODKIND AND S. PILLA University of California, San Diego 1,2
In the previous paper the system of qubits using electrons on a liquid helium film was described. In this paper we describe the physical realization of the system that we have begun to fabricate. We will not in this brief discussion describe how we intend to operate the system. We will show that we are nano- and micro-fabricating a new type of electronic device that differs from other microelectronic devices in that the final step of the fabrication deposits a layer of helium rather than some other dielectric. The operation of the device will differ in that it manipulates single electrons and it must operate at low temperatures.
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The qubits; posts and ground plane
For the purposes of this work, we wish to trap and manipulate electrons over selected members of an array of positively charged posts. A schematic drawing of two such posts is shown in Fig 1. In order to accomplish this, we would like the fields from the posts to satisfy the following criteria. 1) The horizontal distance between posts should be ~ 0.5 µ so that the relevant Rabi frequency is ~ 1 GHz. 2) At a horizontal displacement, x, of a fraction of the distance between posts, d, the x component of the field, Ex, from the posts should be at least comparable to the Coulomb field of an electron on its neighbor, ~6.4 kV/m at separation, d~0.5 µ. 3) The vertical component of the field, Ez, over the post should be no greater than a few thousand Volts per meter so that it is a fraction of the field of the image charge in the helium, EHe ~ 36 kV/m. 4) The surface of the liquid helium should be a distance, h, above the tops of the posts, sufficiently large that the image field from the posts, for the post diameter employed, is < EHe. 5) The ground plane must shield the fields from the traces connected to the posts but the field from the image charge of the electron in the ground plane should also be small relative to EHe. This requires that the surface of the helium be at least ~ 0.5 µ above the ground plane. We will show how these requirements can be satisfied for the geometry that we have fabricated. The major uncertainty in fabricating this system was whether we could grow posts as small as required with the required length to diameter ratio. Working with Dr. Roberto Panepucci, at the Cornell Nanofabrication Facility, we were able to fabricate the posts shown in the upper frame of Fig 2 with more than adequate aspect ratio. They were fabricated by writing holes with the VB6, 100 keV ebeam writer into a 1.5 µ thick layer of PMMA. This had been coated onto a gold layer on a silicon wafer. After developing the resist, gold was electroplated into the holes and then the PMMA was dissolved. We then demonstrated that the process could be repeated on top of the traces that supply the Voltages. A preliminary test of the process (on some traces that were damaged before depositing the posts) is shown in the lower frame of Fig 2. We will want the posts to be very uniform in height so that we plan to polish the surface before dissolving the PMMA. A view of this system on a larger scale looks like a conventional integrated circuit chip with contact pads and traces converging toward the micro-components at the center. The working drawing for the photo- and e-beam lithography is shown in Fig 3. The scale is larger than a conventional chip in order to avoid the need to wire bond 80 leads for each new geometry that we test. The pads are large enough to allow easy alignment with spring contacts permanently installed in the cryostat.
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single vacuum h helium round lane insulator substrate
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Figure 1. Schematic of the geometry of two posts and ground plane.
Figure 2. SEM of posts. The upper frame is gold posts deposited on a gold film on a silicon wafer. Center to center separation is 0.5 µ and height is 1.5 µ. The lower frame is posts grown on the trace pattern so that the voltages of the posts may be set individually. The trace pattern in this test was damaged before the posts were deposited so that this is only a test of the plating technique.
In order to optimize the geometry of the posts and ground plane we are computing the electric fields for a variety of geometries. Fig 4 shows computed values of Ex, and Ez over posts separated by 0.6 µ and all at 1V potential relative to the ground plane. The tops of the posts are 0.3 µ above the ground plane and the fields are plotted for three different elevations above the tops of the posts. The posts pass through a rectangular hole in the ground plane which is 1.5 µ by 11 µ. For this geometry, near the center of the array, the peak values of Ex at an elevation of 0.3 µ above the posts is 29 kV/m/V
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Fabrication of the stricture for qubits using electrons on liquid helium
at a distance from the post of 20% of the distance between them. Thus it would equal the Coulomb force with a potential of 0.2 V applied to the posts. For this potential the maximum value of Ez will be ~115 kV/m which is larger than the desired maximum of order 10 kV/m. It would be compensated by applying an appropriate bias between the ground plane and the top plate (see Fig 7). We have not yet computed the fields and equilibrium positions with the electrons in place but it is clear that the equilibrium positions will be increasingly displaced from the positions of the posts as the edge of the array is approached. Therefore it will be desirable to fabricate long arrays and to use only electrons more than one or two positions from the ends.
Figure 3. Drawing of leads to posts. The left frame is the full photolithography pattern, 1.5 X1.5 mm. The rectangle connected to a tab on the upper right corner is the ground plane. The right frame is the center section showing the e-beam pattern on which the posts are deposited. The small rectangles are the openings for the posts. 0 75 0
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Figure 4. Electric field from two rows of 10 posts each at potential 1V, separated by 0.6 µ, at three different elevations above the tops of the posts. The tops of the posts are 0.1 µ above the ground plane. The fields are computed directly over one of the rows. The positions of the posts are marked by vertical bars along the x axis.
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Electron source for charging the bits -V Si PS
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Figure 5. porous silicon diode.
Previous experiments on 2D electrons over liquid helium have used either a hot filament or an electric discharge to spray electrons onto the surface. The former disturbs the system by heating and the latter
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requires that it be warmed close to 1 K in order to have sufficient gas pressure to sustain the discharge. Both techniques would be too slow for our purposes so that we are developing a tunnel diode source. The most promising approach appeared to us to be diodes fabricated using porous silicon3. A thin layer of porous silicon is formed by anodizing a small area of a silicon wafer in a HF solution in bright light. A 10 nm thick layer of gold is then evaporated onto the anodized area. A positive voltage applied to the gold layer relative to the substrate then accelerates electrons out of the porous silicon and through the gold film. These devices have, to our knowledge, been studied only at room temperature. We are attempting to fabricate them so that they will work at low T. 3
Detection of electron states
In the initial stages of this work, we will detect the state of the electrons by applying bias voltages to individual posts that allow the electrons to escape only if they are in the excited state. The escape rates from a pool of electrons on liquid helium have been measured and found to be in agreement with the rates computed by numerical solution of the time dependent Schrödinger equation4. The escape rates for electrons in the first excited state and in the ground state differ by orders of magnitude for a given “pulling” field. The computations4 indicate that for pulse rise times greater than about 0.1 nsec, the tunneling rate will follow the pulse voltage adiabatically. Thus the states of the qubits can be tested in times very short relative to their coherence times. We will detect the escape of individual electrons using micro-fabricated superconducting transition edge detectors.
Figure 6 Drawing for the detectors. The left panel is the full circuit. The rectangle is the gold film, top plate that covers the wires. The right panel shows the micro-wires and the opening through the plate over them. The circles are holes for the electrons to pass through from the source (see fig 7).
By making them small their heat capacity can be made sufficiently small so that deposition of 1 eV of energy will heat them above TC. A positive bias applied to the superconducting element will assure that any electron that escapes will be accelerated to the detector so that all escaping electrons will be detected. 4
The complete system
A schematic diagram of the complete system is shown in Fig 7. The upper and lower plate will be separated by 1 mm. Each will be 15×15 mm. The lower plate is covered with the helium film and the electrons float about 10 nm above the helium surface. The microstructures are exaggerated and of differing scales for illustration.
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Fabrication of the stricture for qubits using electrons on liquid helium tunnel diode electron source transition edge detectors upper plate
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Figure 7. Schematic of the entire system. The upper capacitor plate includes the detectors. The lower plate includes the posts and is covered with the helium film. The electrons float over the posts about 10 nm above the surface of the helium film.
Work supported by the National Science Foundation. We wish to thank Dr. David Vier for his assistance on the numerical simulations of the fields.
References 1. M. I. Dykman and P. M. Platzman, this conference 2. P. M. Platzman and M.I. Dykman, Science 284, 1967 (1999) 3. N. Koshida, X. Sheng, T. Komoda, Applied Surface Science 146, 371 (1999). 4. G. F. Saville and J. M. Goodkind, Phys. Rev. A 50, 2059-2067 (1994).