Postbreakdown Current in MOS Structures: Extraction of Parameters Using the Integral Difference Function Method Enrique Miranda, Member, IEEE, Adelmo Ortiz-Conde, Senior Member, IEEE, Francisco J. García-Sánchez, Senior Member, IEEE, and Eduardo Farkas-Sosa, Member, IEEE

Abstract—This paper deals with the extraction of parameters and simulation of the postbreakdown leakage current in pMOS devices with ultrathin oxides. The model considered is based on the generalized diode equation, i.e., a diode-like equation with series resistance. The current–voltage (I–V ) characteristic can be expressed in a closed-form expression, which makes it is suitable for circuit simulation environments. Model parameters are extracted using the integral difference function (IDF) method. Because the exact expression for the I–V characteristic is used for computing the IDF, the method does not involve any kind of approximation. The effect of including a nonlinear correction term to the voltage drop across the structure is also discussed. Index Terms—MOS, oxide breakdown, reliability.



S it is well known, the application of either a high or a prolonged electrical stress to a thin oxide layer in a MOS device leads inexorably to the formation of a low-resistance current path between gate and substrate. This localized current flow through the insulating layer is the signature of dielectric breakdown [1]. Several attempts have been made not only to enhance the understanding of the electron transport mechanism under such circumstance but also to find a suitable mathematical representation of the phenomenon for circuit simulation purposes. Concerning the so-called final, catastrophic, or hard breakdown (HBD) event, two approaches have been followed, namely 1) there are models that rely on numerical simulation schemes like the oxide thinning model [2] or the multiplequantum-wire model [3] and 2) there are those models that provide a closed-form expression for the current–voltage (I–V ) characteristic like the quantum-point-contact (QPC) model for dielectric breakdown [4]. The latter model predicts that the breakdown path simply behaves as a resistor with conductance values in the order of the quantum conductance unit 2e2 /h ≈ (12.9 kΩ)−1 , where e and h are the electron charge and the Planck’s constant, respectively. Nevertheless, because the Manuscript received August 20, 2005; revised January 23, 2006. This work was supported by the Ministerio de Ciencia y Tecnología, Spain, under Project TIC2003-08213-C02. E. Miranda is with the Departament d’Enginyeria Electrónica, Universitat Autònoma de Barcelona, 08193 Bellaterra, Spain (e-mail: [email protected] uab.es). A. Ortiz-Conde, F. J. García-Sánchez, and E. Farkas-Sosa are with the Laboratorio de Electrónica del Estado Sólido, Universidad Simón Bolívar, Caracas 89000, Venezuela (e-mail: [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TDMR.2006.876563

QPC model assumes metallic-like charge reservoirs at the two ends of the constriction instead of semiconductor electrodes, the model is unable to account for the low-voltage region properly. This work, which is an extension of a recent paper presented at IPFA’05, tries to circumvent this deficiency [5]. We propose that the combined system electrodes–breakdown path is well represented by a diode-type equation affected by a series resistance. Nevertheless, as important as having a good model for the leakage current is the availability of a suitable parameters extraction strategy, and this issue is addressed by means of the integral difference function (IDF) [6]. As it has been demonstrated, the use of an integral method rather than a differential one makes this approach especially immune to measurements errors because of the low-pass filter nature of integration [6]. II. S AMPLES AND M EASUREMENTS For the experiments, we used standard MOS capacitors grown on n-type Si (1015 cm−3 ) with poly-Si gate, oxide thicknesses of 3.8, 4.3, and 4.9 nm, and area of 1.96 · 10−5 cm2 . The samples were subjected to ramped voltage stress in the high integration mode until the detection of the first HBD event. III. M ODEL AND S IMULATION R ESULTS A. Diode-Like Model In Fig. 1, fresh and HBD I–V characteristics for a 3.8-nmthick sample are compared. Inasmuch as the former current flows distributed throughout the device area, the second characteristic corresponds to a highly localized current. In Fig. 2, the HBD curve is replotted together with its normalized differential conductance, d ln(I)/d ln(V ) = (V /I)dI/dV . The latter curve exhibits a change of trend at about 0.7 V associated with the diode-to-resistance-like transition [7]. Following this observation, we proposed for our system the equivalent electric circuit illustrated in Fig. 3, whose I–V characteristic can be written as I = I0 {exp [α(V − IRBD )] − 1}


where I is the terminal current, V is the terminal voltage, RBD is the series breakdown resistance, I0 is a reverse saturation current, α = 1/(nVth ) is a constant, n is a diode ideality factor, and Vth is the thermal voltage.

1530-4388/$20.00 © 2006 IEEE



explicit approximate solutions for modeling purposes. Several of these approximate solutions have been proposed [8], [9], which use only elementary functions. However, nowadays, exact explicit analytical solutions for I [10] that make use of the special function known as the Lambert W function [11]—a function that is not expressible in terms of elementary analytical functions—already exist. The Lambert W function is defined as the solution to the equation W (x) exp[W (x)] = x. It has been used for solving some previously analytically unsolved diode and bipolar transistor circuit analysis problems [12], as well as in device modeling formulations [13]. This type of solutions can also be used directly to study illuminated solar cells, as was recently done [14], by adding the photogenerated current to the ideal junction current. The solution for each variable I and V as an explicit function of the other and of the device model parameters are given as follows:

Fig. 1. Pre- and post-breakdown I–V characteristics measured on the same sample.

1 W {αI0 RBD exp [α(V + I0 RBD )]} − I0 (2) αRBD   I + I0 1 V = IRBD + ln . (3) α I0 I=

In (2), W represents the usual short-hand notation for the principal branch of the Lambert W function (see Appendix). Notice that the solution for the voltage in (3) is given in terms of common elementary functions. These explicit representations are convenient and efficient computational alternatives to iteratively solve the original transcendental function (1) to be used in device models for circuit simulation. As we will show next, they are also suitable for the purpose of extracting the model parameters directly by numerical optimization. B. Extraction of Parameters

Fig. 2.

Experimental HBD I–V and its normalized differential conductance.

Fig. 3.

Equivalent circuit for the breakdown path

It is well known that the transcendental equation above cannot be solved explicitly in general for I using common elementary functions. Therefore, it has been customary to use

The problem of extracting the model parameters is generally attempted by direct vertical optimization [15] using the measured I–V data by minimizing the quadratic error on the vertical axis (i.e., the current). However, this method is quite computationally intensive because of the implicit nature of the original transcendental function (1). Direct lateral optimization was proposed [16], [17] for a diode exhibiting only significant series resistance based on the approach of minimizing the error on the horizontal axis (i.e., the voltage). The motivation for doing so, in the case of a diode with only series resistance, is that the voltage can be explicitly solved from (1) as a function of the current using only elementary analytic functions, which considerably reduces the computation time [see (3)]. Recently, a combination of the lateral and vertical optimization techniques was used to extract the parameters of an illuminated solar cell [18]. Other extraction procedures rely on auxiliary functions or operators [19]–[21]. In this paper, we use the IDF D(I, V ), which involves the integration of the current with respect to voltage. This method has been successfully used to extract the model parameters of diodes [6], [22] and has also found useful applications in other areas, such as for



quickly calculating device harmonic distortion [23]. D(I, V ) is defined as [6] I D(I, V ) ≡

V V dI −


V I dV = I V − 2


I dV.



Substitution of (2) and (3) into (4) and integrating results in a long expression that contains Lambert W functions, V , and I. Replacing the terms that contain Lambert W functions using (2) and (3), and after some algebraic manipulation, function D(I, V ) can be conveniently expressed by a purely algebraic equation of the form D(I, V ) ≡ DV 1 V + DI1 I + V I + DI2 I 2


where the three coefficients are given in terms of the following model parameters: DV 1 = 2I0

DI1 = − 2 RBD I0 + DI2 = − RBD .

1 α

(6) (7) (8)

It should be emphasized that the bivariate polynomial expression (5), which is a particular case of a more general problem [22], was derived without using any approximations, and that, as such, it is valid for any region of operation, including I < I0 . The parameter extraction procedure consists of fitting algebraic (5) to the IDF, which is numerically calculated with (4) from the experimental data. To this purpose, we use the fourth-order Simpson integration algorithm. This bivariate fitting process produces the values of the equation coefficients DV 1 , DI1 , and DI2 . The resulting coefficients are then used to calculate the model parameters RBD , I0 , and α using (6)–(8). Experimental and simulated I–V curves using (2) for three different oxides are shown in Fig. 4. Notice the excellent agreement in the whole bias range investigated. As an example, Fig. 5 illustrates the IDF used for the parameter extraction process and its projections on the constant I–V planes for the sample identified with triangles in Fig. 4(a). IV. D ISCUSSION In view of the experimental results, and in agreement with the proposed model, the current flow through a breakdown spot in a MOS structure exhibits two distinctive regimes. This is clearly illustrated when plotting the normalized differential conductance. As shown in Fig. 2, the system’s behavior is dictated by the spreading resistance effect for voltages above 0.5–0.7 V. Note that for a exponential dependence of the current, d ln(I)/d ln(V ) ∝ V, whereas for a simple resistance, d ln(I)/d ln(V ) = 1. These expressions correspond to the limiting cases of (1). The breakdown resistances found for the curves shown in Fig. 4 are in the order of several kiloohms, which is in total agreement with previous reports indicating the highly localized nature of electron transport [4]. The idea of the formation of a diode-like structure after breakdown is not new

Fig. 4. Various post breakdown I–V characteristics for samples with (a) tox = 3.8, (b) 4.3, and (c) 4.9 nm.

and has been invoked before. Nafría et al. proposed an equivalent electrical circuit consisting of a diode with series resistance in parallel with the fresh oxide structure [24]. More recently, Bearda et al. demonstrated the diode-like behavior by assuming a nanometer size cylindrical structure across the oxide layer [25]. It is generally recognized that the origin of the leakage path is the result of the accumulation of a critical density of defects, the final size of the spot being determined by the power




the model parameters for the same curve using some alternative methods. First, the vertical optimization can be implemented in two different ways. The first implementation consists of fitting straightforwardly the experimental data to (2). This would require the evaluation of the Lambert function by means of approximated expressions or iterative numerical schemes [11]. The second implementation is a bivariate direct fitting, which consists of rewriting (1) as f (V, I) = I0 {exp [α(V − IRBD )] − 1} − I = 0.


Fig. 6. Scatterplot of the model parameters for the samples with tox = 3.8, 4.3, and 4.9 nm shown in Fig. 4.

Then, we fit f (V, I) to zero considering I and V as two independent variables. This second method is easier to implement, but the initial guess should be close to the solution. A lateral optimization method [16], [17] has also been applied to this problem by fitting the experimental voltage to (3). The IDF method, which minimizes the error on the area [28] (i.e., the power), is very computationally efficient, has fast convergence, and can be applied for cases having both series and shunt resistances. The resulting parameter values for the device illustrated with triangles in Fig. 4(a) obtained with the discussed extraction methods are reported in Table I. We observe in this table that both the vertical optimization and the present method yield the extracted parameters with differences of less than 5%. In contrast, lateral optimization produces extracted parameters differ by up to 14% from the latter values. We have also investigated the effect of including a power-law correction term in (3) as suggested by Mikhelashvili et al. [7]. According to these authors, the voltage across the device can be written as follows:   I + I0 1 (10) V = RBD I + aI b + ln α I0

dissipated during the current runaway or by the progressive accumulation of damage at the initial breakdown location [26]. The I–V curves analyzed in this paper correspond to the former case, i.e., they were measured after a sudden loss of the insulating property. Even though several studies indicate that the formation of the breakdown path involves some kind of microstructural change, to this date, there is no definite physical description of the electron transport mechanism at the microscopic level [27]. In order to complete the picture, Fig. 6 shows the scattergraph of the model parameters obtained by the IDF method. Even though this is not a statistical study, it can be seen that the thinnest oxides (tox = 3.8 nm) exhibit higher alpha (> 4.25 V−1 ) and therefore a closer behavior to what is expected for a “macroscopic” diode (lower n). This may be a consequence of the more intimate contact between the electrodes. No clear correlation has been found among the other parameters. In order to compare the results obtained by the IDF method with previous approaches, we have calculated

where a and b are constants. In an ideal Schottky diode, this additional term may be related to double carrier injection at high forward voltages (b = 0.5), whereas in p-i-n diodes, the power-law term has been connected with a carrier drift into the intrinsic region (b = 0.25). As discussed in [7], the value of a is determined by the densities, mobilities, diffusion constant, and diffusion length of thermally generated and excess injected carriers as well as the temperature. Because of the complexity of our system, we are not in conditions of providing a physical interpretation to this parameter, and for the moment, we are only interested in determining whether the incorporation of such nonlinearity can improve the fitting results or not. As shown in Table II, we have tested different combinations of parameters including RBD = 0. The sign “=” in Table II means that we have fixed a priori the corresponding parameter’s value. The different options are labeled from 1 to 4. In this case, the parameters optimization process was accomplished using the lateral optimization method.

Fig. 5. Integral differential function and its projections. Symbols are experimental data. Solid lines are obtained with (4).




Fig. 7. Relative error in voltage as a function of current for different fitting models (see Table II).

conduction process. On the contrary, if this term is absent, the minimum global error is achieved using a nonlinear correction with a power less than unity (option 4). As shown in Fig. 8, this latter option provides the best transition model from diode-like conduction to resistance-like conduction. However, at higher biases, the model is not able to reproduce the experimental behavior exhibited by the logarithmic conductance as occurs with option 1. Unfortunately, the question of whether (1) can be applied or not to model the current evolution during progressive breakdown (PBD) cannot be elucidated from the available data. PBD is nothing but the gradual transition from the fresh I–V characteristic to the final breakdown state and is only observed in sub-2-nm-thick oxides [26]. The first stage of this evolution is often referred to as soft breakdown and shows a power-law voltage dependence in the low bias range and an exponential dependence for larger voltages [4]. From this observation, it seems clear that (1) is not applicable to this limiting case, at least in its present form. An alternative to this approach could be to consider a voltage-dependent series resistance in (1), but this requires further investigation. Nevertheless, it is worth pointing out that the proposed model has been applied to simulate the current evolution in La2 O3 during progressive electrical stress [29]. Even though it is shown that the proposed model is able to capture the evolutionary diode-like I–V characteristics, the physical meaning of the parameters variation is still an open question. V. C ONCLUSION An improved description for the HBD I–V characteristic in MOS devices has been presented. The model is able to capture the essential features exhibited by these characteristics such as the transition from diode-to-resistance-like behavior. Because of its analytical formulation and the availability of a proper method for the extraction of parameters, we think that this model represents a step forward toward the integration of these kinds of effects in circuit simulators. A PPENDIX The Lambert W function is the solution of the following equation [11]: W (x)eW (x) = x

Fig. 8. Logarithmic conductance as a function of applied voltage for the fitting models described in Table II.

According to what is shown in Figs. 7 and 8, the inclusion of a nonlinear term in (10) yields better results than the original model (option 1 in Table II), mainly in the low-voltage region (< 1 V). The major drawback of this approach is that, now, there is no analytical expression for the current. As a special case, we have tested a quadratic correction (option 2). Even though the fitting can be improved when a and b are free parameters (option 3), note that this correction gives very similar results to option 1 with an exponent close to unity (b = 1.07). This means that when present, the linear term dominates the


which has the series expansion ∞  (−1)n−1 nn−2 n x (n − 1)! n=1 3 8 125 5 54 6 x − x +. . . . = x−x2 + x3 − x4 + 2 3 24 5

W (x) =


The Lagrange inversion theorem gives the equivalent series expansion for the principal branch as follows: W (x) =

∞  (−n)n−1 n x . n! n=1



However, this form is useless for practical numerical computations because its terms oscillate between ever larger positive and negative values for x ≥ 0.4 [30]. Alternatively, for x ≥ 0, (12) can be approximated by  W (x) ≈ ln(1 + x) 1 −

ln [1 + ln(1 + x)] 2 + ln(1 + x)



which approximates W (x) with a relative error less than 10−2 [31]. Moreover, the following two asymptotic approximations are very useful for typical diode problems: W (K exp(nx))


[14] [15]

≈ ln(K) + nx − ln (ln(K) + nx) +

ln (ln(K) + nx) ln(K) + nx

ln (ln(K) + nx) (ln (ln(K) + nx) − 2) + ··· + 2 (ln(K) + nx)2

W (K exp(nx)) ≈ K exp(nx) − (K exp(nx))


(15) [17]

which is valid for large values of K · exp(nx), and





3 8 (K exp(nx))3 − (K exp(nx))4 + . . . 2 3


for small values of K · exp(nx).

[19] [20] [21]

ACKNOWLEDGMENT The authors would like to thank J. Suñé, F. Campabadal, and L. Fonseca for sample provision.




[1] J. Suñé, D. Jiménez, and E. Miranda, “Oxide reliability,” in A Summary of Silicon Oxide Wearout, Breakdown and Reliability, vol. 23, D. Dumin, Ed. Singapore: World Scientific, p. 173. [2] Y. Omura and K. Komiya, “Transport characteristics of posthard breakdown thin silicon oxide films and consideration of physical models,” J. Appl. Phys., vol. 91, no. 7, pp. 4298–4306, Apr. 2002. [3] D. Ting, “An embedded quantum wire model of dielectric breakdown,” Appl. Phys. Lett., vol. 74, no. 4, pp. 585–587, Jan. 1999. [4] E. Miranda and J. Suñé, “Electron transport through broken down ultrathin SiO2 layers in MOS devices,” Microelectron. Reliab., vol. 44, no. 1, pp. 1–23, Jan. 2004. [5] E. Miranda, A. Ortiz-Conde, F. García Sánchez, and E. Farkas, “Extraction of parameters and simulation of the hard breakdown I–V characteristics in ultrathin gate oxides,” in Proc. 12th IPFA, 2005, pp. 150–154. [6] F. García Sánchez, A. Ortiz-Conde, and J. J. Liou, “A parasitic series resistance-independent method for device-model parameter extraction,” in Proc. Inst. Elect. Eng.—Circuits Devices and Syst., 1996, vol. 143, pp. 68–70. [7] V. Mikhelashvili, G. Eisenstein, V. Garber, S. Fainleib, G. Bahir, D. Ritter, M. Orenstein, and A. Peer, “On the extraction of linear and nonlinear physical parameters in nonideal diodes,” J. Appl. Phys., vol. 85, no. 9, pp. 6873–6883, May 1999. [8] A. Ortiz-Conde and F. J. García Sánchez, “Approximate analytical expression for equation of ideal diode with series and shunt resistance,” Electron. Lett., vol. 28, no. 21, pp. 1964–1965, Oct. 1992. [9] J. Le Bihan, “Accurate analytical approximation for normalized diode characteristic,” Int. J. Circuit Theory Appl., vol. 29, no. 4, pp. 397–401, Jul./Aug. 2001. [10] A. Ortiz-Conde, F. J. García Sánchez, and J. Muci, “Exact analytical solution of the forward non-ideal diode equation with series and shunt


[25] [26] [27]


[29] [30] [31]


parasitic resistance,” Solid State Electron., vol. 44, no. 10, pp. 1861–1864, Oct. 2000. R. Corless, G. Gonnet, D. Hare, D. Jeffrey, and D. Knuth, “On the Lambert W -function,” Adv. Comput. Math., vol. 5, no. 1, pp. 329–359, Dec. 1996. T. C. Banwell, “Bipolar transistor circuit analysis using the Lambert W -function,” IEEE Trans. Circuits Syst. I. Fundam. Theory Appl., vol. 47, no. 11, pp. 1621–1633, Nov. 2000. A. Ortiz-Conde, F. J. García Sánchez, and M. Guzmán, “Exact analytical solution of channel surface potential as an explicit function of gate voltage in undoped-body MOSFETs using the Lambert W -function and a threshold voltage definition therefrom,” Solid State Electron., vol. 47, no. 11, pp. 2067–2074, Nov. 2003. A. Jain and A. Kapoor, “Exact analytical solutions of the parameters of real solar cells using Lambert W -function,” Sol. Energy Mater. Sol. Cells, vol. 81, no. 2, pp. 269–277, Feb. 2004. A. Ferhat-Hamida, Z. Ouennoughi, A. Hoffmann, and R. Weiss, “Extraction of Schottky diode parameters including parallel conductance using a vertical optimization method,” Solid State Electron., vol. 46, no. 5, pp. 615–619, May 2002. A. Ortiz-Conde, Y. Ma, J. Thomson, E. Santos, J. J. Liou, F. J. García Sánchez, M. Lei, J. Finol, and P. Layman, “Direct extraction of semiconductor device parameters using lateral optimization method,” Solid State Electron., vol. 43, no. 4, pp. 845–848, Apr. 1999. E. Miranda, “A diodelike conduction model for the postbreakdown current in metal-oxide-semiconductor structures,” J. Appl. Phys., vol. 96, no. 11, pp. 6940–6942, Dec. 2004. M. Haouari-Merbah, M. Belhamel, I. Tobías, and J. M. Ruiz, “Extraction and analysis of solar cell parameters from the illuminated current-voltage curve,” Sol. Energy Mater. Sol. Cells, 2005. in Press, Available online. H. Norde, “A modified forward I–V plot for Schottky diode with a high series resistance,” J. Appl. Phys., vol. 50, no. 7, pp. 5052–5053, Jul. 1979. H. Wong and W. H. Lam, “A robust parameter extraction method for diode with series resistance,” in Proc. IEEE Hong Kong Electron Devices Meeting, 2001, pp. 38–41. J. C. Ranuárez, A. Ortiz-Conde, and F. J. García Sánchez, “A new method to extract diode parameters under the presence of parasitic series and shunt resistance,” Microelectron. Reliab., vol. 40, no. 2, pp. 355–358, Feb. 2000. A. Ortiz-Conde and F. J. García Sánchez, “Extraction of non-ideal junction model parameters from the explicit analytic solutions of its I–V characteristics,” Solid State Electron., vol. 49, no. 3, pp. 465–472, Mar. 2005. A. Cerdeira, M. Estrada, R. Quintero, D. Flandre, A. Ortiz-Conde, and F. J. García Sánchez, “New method for determination of harmonic distortion in SOI FD transistors,” Solid State Electron., vol. 46, no. 1, pp. 103–108, Jan. 2002. M. Nafría, J. Suñé, and X. Aymerich, “Exploratory observations of post-breakdown conduction in polycrystalline-silicon and metal-gated thin-oxide metal-oxide-semiconductor capacitors,” J. Appl. Phys., vol. 73, no. 1, pp. 205–215, Jan. 1993. T. Bearda, P. Woerlee, H. Wallinga, and M. M. Heyns, “Charge transport after hard breakdown in gate oxides,” Jpn. J. Appl. Phys., vol. 41, no. 1, pp. 2431–2436, Apr. 2002. S. Lombardo, J. Stathis, B. Linder, K. Pey, F. Palumbo, and C. Tung, “Dielectric breakdown mechanisms in gate oxides,” J. Appl. Phys., vol. 98, no. 121301, pp. 1–36, 2005. C. Tung, K. Pey, L. Tang, M. Radhaskrishnan, W. Lin, F. Palumbo, and S. Lombardo, “Percolation path and dielectric-breakdown-inducedepitaxy evolution during ultrathin gate dielectric breakdown transient,” Appl. Phys. Lett., vol. 83, no. 11, pp. 2223–2225, Sep. 2003. A. Caralli, A. Ortiz-Conde, and F. J. García Sánchez, “Percentage area difference (PAD) as a measure of distortion and its use in maximum enclosed area (MEA), a new ECG signal compression algorithm,” in Proc. Int. Caracas Conf. Cir. Dev. Sys., Aruba, The Netherlands, 2002, pp. I035-1–I035-5. E. Miranda, J. Molina, Y. Kim, and H. Iwai, “Degradation of high-K La2 O3 gate dielectrics using progressive electrical stress,” Microelectron. Reliab., vol. 45, no. 9–11, pp. 1365–1369, Sep./Nov. 2005. E. Weisstein. (1999-2006). Lambert W -function. MathWorld-A Wolfram Web Resource. [Online]. Available: http://mathworld.wolfram.com/ LambertW-Function.html S. Wintzki, “Uniform approximations for transcendental functions,” in Lecture Notes in Computer Science, vol. 2667. New York: SpringerVerlag, 2003, pp. 780–789.



Enrique Miranda (M’01) was born in Buenos Aires, Argentina, in 1963. He received the Ph.D. degree in electronics engineering from the Universitat Autònoma de Barcelona (UAB), Barcelona, Spain, in 1999 and the Ph.D. degree in physics from the Universidad de Buenos Aires (UBA), Buenos Aires, in 2001. From 1987 to 2003, he was an Assistant Professor with the Faculty of Engineering, UBA, and, from 2001 to 2003, an Associated Researcher with the Consejo Nacional de Investigaciones Científicas y Técnicas, Argentina. Since 2004, he has been a Professor with the Escola Técnica Superior d’Enginyeria, UAB. He has received research fellowships from the UBA, INTERCAMPUS (Universidad de Zaragoza), and MUTIS (UAB) from the Spanish International Cooperation Agency (AECI), from the German Exchange Academic Agency (Technical University Hamburg-Harburg), from the Italian government (Universita degli Studi di Padova), RAMON y CAJAL (UAB) from the Ministerio de Ciencia y Tecnología, Spain, MATSUMAE (Tokyo Institute of Technology) from the Matsumae International Foundation, Japan, and TAN CHIN TUAN from the Nanyang Technological University, Singapore. He has authored or coauthored 70 papers, most of them devoted to the electron transport problem through the gate insulator in MOS devices under different circumstances, namely direct and Fowler–Nordheim tunneling, effects of trapped charge, stress-induced leakage current, and post-breakdown conduction. Dr. Miranda serves as a member of the Distinguished Lecturer Program of the Electron Devices Society and is a Reviewer of the IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE ELECTRON DEVICE LETTERS, Journal of Applied Physics, Applied Physics Letters, Thin Solid Films, and Microelectronics Reliability. He also belongs to the Advisory Board of Microelectronics Reliability.

Adelmo Ortiz-Conde (S’82–M’85–SM’97) was born in Caracas, Venezuela, on November 28, 1956. He received the B.S. degree in electronics from the Universidad Simón Bolívar, Caracas, in 1979, and the M.E. and Ph.D. degrees from the University of Florida, Gainesville, in 1982 and 1985, respectively. His doctoral research was in the area of semiconductor device modeling under the guidance of Prof. J. G. Fossum. From 1979 to 1980, he was an Instructor with the Department of Electronics, Universidad Simón Bolívar. In 1985, he joined the technical staff of Bell Laboratories, Reading, PA, where he was engaged in the development of high-voltage integrated circuits. Since 1987, he has been with the Department of Electronics, Universidad Simón Bolívar, and was promoted to a Full Professor in 1995. He was on sabbatical leave at the Florida International University, Miami, from September to December 1993, at the University of Central Florida, Orlando, from January to August 1994 and again from July to December 1998, and at CINVESTAV, Mexico City, Mexico, from October 2000 to February 2001. He has authored one textbook Analysis and Design of MOSFETs: Modeling, Simulation and Parameter Extraction (Kluwer, 1998), 70 refereed journal articles (including 3 invited review articles), and 56 papers (including 7 invited papers) in international conference proceedings. His present research interest includes the modeling and parameter extraction of semiconductor devices. Dr. Ortiz-Conde is a member of Eta Kappa Nu, Tau Beta Pi, Phi Kappa Phi, and the Galilean Society. He is an Electron Devices Society (EDS) Distinguished Lecturer. He is the Chair of IEEE’s Circuits and Systems, Electron Devices, Power Electronics (CAS/ED/PE) Venezuelan Chapter. He was the Editor for Region 9 of the IEEE EDS Newsletter from 2000 to 2005. He is a member of the Advisory Board of Microelectronics and Reliability and of the Engineering and Applied Sciences Commission of the National System for the Promotion of Research. He has served as a Reviewer for national and international journals and conferences. He was the General Chairperson of the first IEEE International Caracas Conference on Devices, Circuits, and Systems in 1995, the Technical Chairperson of the second, fourth, and fifth editions of this conference in 1998, 2002, and 2004, respectively, and the Chairperson of the Steering Committee in 2000.

Francisco J. García-Sánchez (M’74–SM’97) was born in Madrid, Spain, in 1947. He received the B.E.E., M.E.E., and Ph.D. degrees in electrical engineering from the Catholic University of America, Washington, DC, in 1970, 1972, and 1976, respectively. In 1977, he joined the faculty of the Department of Electronics, Universidad Simón Bolívar (USB), Caracas, Venezuela, where he reached the rank of Full Professor in 1987. He has held several directive positions within USB academic administration, such as Coordinator for Undergraduate and Graduate Studies in Electronics Engineering, Coordinator of Applied Sciences Research, and elected faculty Member of USB Academic and Superior Councils. He has been actively involved, both locally and internationally, in the promotion, planning, direction, administration, and evaluation of Research and Development endeavors. He presently holds a Research Professorship Chair at USB and is a Level IV Researcher (highest rank) in Venezuela’s Scientific Research System. He has published more than 120 articles in national and international refereed technical journals and conferences, including 18 invited papers. He is the coauthor of a book on MOSFET modeling and has edited several specialized collective works. His present research interests are in the area of semiconductor device modeling, especially MOSFETs. Prof. García-Sánchez is a member of the Venezuelan Association for the Advancement of Science and a founding member and past Vice President of the Galilean Society. He serves as a Reviewer for specialized technical journals and has been active in editorial work, as well as in numerous conference organization activities. Since 1994, he has shared the responsibility for steering the organization of the IEEE International Caribbean Conference on Devices, Circuits and Systems (ICCDCS). He is an Electron Devices Society (EDS) Distinguished Lecturer. He has been the Chair of IEEE’s CAS/ED/PEL Societies Venezuela Joint Chapter. He is currently a member of the IEEE Leon K. Kirchmayer Graduate Teaching Award and Undergraduate Teaching Award Committee, a member of the EDS Graduate Student Fellowship Subcommittee, the Vice Chair of the EDS Subcommittee for Regions and Chapters for Latin America (SRC-LA), and an elected member of the EDS Administrative Committee (AdCom). He has been the recipient of several awards for excellence in research.

Eduardo Farkas-Sosa (S’01–M’05) was born in Caracas, Venezuela, on July 15, 1978. He received the B.S. degree in electronics engineering from the Universidad Simón Bolívar (USB), Caracas, in 2005. He is currently working toward the M.E. degree in electronics engineering at the same university. His undergraduate degree thesis entitled “Design and implementation of an electrical impedance tomography system” received Honorable Mention at USB and the IEEE-INELECTRA National Award for the best investigation in the electronics area in 2004. He has been a Research Assistant in the field of solid-state electronics at the Solid-State Electronics Laboratory, USB. He has coauthored two papers regarding modeling and parameter extraction of MOS devices and ultrathin gate oxides, which were presented at two IEEE International Conference Proceedings [i.e., Physical and Failure Analysis of Integrated Circuits (IPFA) and IEEE International Caracas Conference on Devices, Circuits and Systems (ICCDCS)]. He has also coauthored three papers regarding electrical impedance tomography, which were presented at two local conferences (i.e., JIFI and AIB) and one international conference (i.e., European Medical and Biological Engineering Conference-European Conference on Biomedical Engineering (EMBEC-IFMBE). In 2002 and 2004, he participated as a member of the Publications Committee of the Fourth and Fifth ICCDCS held in Oranjestad, Aruba, and Punta Cana, Dominican Republic, respectively. He is currently the Coordinating Engineer of the Department of Instrumentation and System Automation, Microinter Corporation, a consulting company at Caracas, Venezuela. His main interests are nanotechnology, bioengineering, and telecommunications.

Postbreakdown Current in MOS Structures: Extraction of ... - IEEE Xplore

series resistance. Nevertheless, as important as having a good model for the leakage current is the availability of a suitable parameters extraction strategy, and ...

308KB Sizes 0 Downloads 117 Views

Recommend Documents

Determination of discharge current equation parameters ... - IEEE Xplore
Jul 6, 2006 - input data current measurements from ESD generators optimises the ... computer simulations for the circuit defined in the Standard to insert.

I iJl! - IEEE Xplore
Email: [email protected] Abstract: A ... consumptions are 8.3mA and 1.lmA for WCDMA mode .... 8.3mA from a 1.5V supply under WCDMA mode and.

Device Ensembles - IEEE Xplore
Dec 2, 2004 - Device. Ensembles. Notebook computers, cell phones, PDAs, digital cameras, music players, handheld games, set-top boxes, camcorders, and.

striegel layout - IEEE Xplore
tant events can occur: group dynamics, network dynamics ... network topology due to link/node failures/addi- ... article we examine various issues and solutions.