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On the Implementation of FPGA-Based Adaptive Synchronizer of DSSS Receiver Hamidreza Merajpour and Mohammad Hossein Madani Abstract— Real time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processors. In this paper, we present a configurable hardware for adaptive synchronization of DSSS receiver. The architecture has been designed to deal with parallel/pipeline processing and composed of adaptive acquisition and tracking. This architecture has been simulated on a FPGA device and implementation results are presented. Index Terms— Adaptive Acquisition, Delay Lock Loop, Spread Spectrum, FPGA.

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1. INTRODUCTION

T

HE pseudo-noise (PN) code synchronization is very important for successful operation of a direct sequence spread spectrum (DS-SS) receiver [1]. Synchronization consists of two step; initial synchronization that called acquisition and fine adjustment which called tracking loop [1]. Extensive research on pseudo noise (PN) code acquisition has been carried out which focused on fixed–threshold acquisition. The received signal power in mobile communication decreases with increasing the distance and it is inversely proportional to some power 3≤n≤4 of the distance[2]. Furthermore, the received signals are also subject to rapid rayleigh fading about a slowly varying mean signal strength. Thus since the received signal level and location are unknown, good acquisition performance of a PN sequence cannot be achieved if a fixed-threshold acquisition scheme is employed. These facts suggest adaptive signal processing techniques employing an adaptive detection threshold. In this paper we use an adaptive PN sequence acquisition scheme employing a sliding window for obtaining the needed local information. After initial synchronization of the local code with the received PN code, receivers’ turns on the tracking loop to do the fine adjustment of the delay between the received and local PN codes. A number of different tracking loops exist. Most commonly used tracking loops belong to the family of the so called delay-lock loop (DLL). Normally, two PN code correlators are used in the DLL tracking loop called early and late correlators. The early and late output signals are ————————————————

• F.A. Author is with the Amirkabir university of Technology,Tehran, Iran. • S.B. Author is with the Amirkabir university of Technology,Tehran, Iran.

used to generate an error signal, which is used to control the timing of the reference PN code by controlling the voltage controlled clock generator. In situations where the carrier phase is unknown, the error signal is formed as difference between the squared outputs of the two correlators and the scheme is known as non coherent tracking. This paper is organized as follows. Section 2 provides the theoretical foundation of CFAR and Digital tracking Loop algorithm. Section 3 presents the hardware architecture of both algorithms and the field programmable gate array (FPGA) implementation and experimental result. Section 4 present the concluding remarks and some directions for further research.

2

THEORETICAL ALGORITHM

2.1 Adaptive Acquisition Block As a basic acquisition scheme for binary-shift keying (BPSK) spreading, a non coherent hypothesis testing device, shown in Fig. 1(a), is employed. It is assumed that the spreading sequence timing is determined before any phase measurement is attempted and there is no frequency error when non coherent reception of rayleigh–fading signals in additive white gaussian noise (AWGN) is considered, the normalized-likelihood functions become [1]: P0 ( Z ) =

Z L −1 e − Z ( L − 1)!

(1)

Z L −1 e − Z P1 ( Z ) =

(1 + µ ) ( L − 1)! (1 + µ ) L

(2)

Where µ is the average signal–to–noise ratio (SNR) and L is the number of post detection integrations (PDI’s). For adaptive operation of decision processors, the detection threshold should be updated in accordance with local situation as shown in Fig. 1(b). This adaptive scheme is well known as the constant false alarm rate (CFAR) detector [3]. Samples Z which are the sum of the squares of L

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JOURNAL OF TELECOMMUNICATIONS, VOLUME 8, ISSUE 2, MAY 2011 42

independent rayleigh observation, are sent serially into a shift register of length M+1=m+1. The statistic X is formed by processing the contents of the neighboring cells in the window surrounding the test cell Y. The threshold TX varies according to local information, i.e., power-level estimate X times threshold coefficient T. Here T is a constant scale factor used to achieve a desired false alarm rate (CFAR) for a window of given size M. According to the design of the power-level estimator, The various adaptive schemes can be realized, which we use mean level acquisition processor (MLAP), In the mean level scheme [3] the power-level estimate is obtained by summing the M cells of the window M . X = Z

∑

i

i =1

H b (Z ) =

1− a 1 − az −1

a ≡ exp( −2πBbTc )

(3)

Where Tc denotes the chip period. The bandwidth, Bb of the branch filters is set to be 1/T , where T is the bit period. The DDLL loop equation is given by:

ε k +1 = ε k − γ ek

(4)

Where εk denotes the interpolating offset in the k-th sampling instant, ek denotes the error signal in Fig. 2, and γ is the NCO sensitivity, which is chosen to be 2-6. We know that, the successful demodulation of the pass band signal depends highly on the good behavior of the PN synchronization, and mainly on the DLL. For the DLL to work properly, the signal level at its input cannot be too low (PN tracking would be too slow) or too high (in this case, the DLL might get unlocked). Thus, the automatic gain control block (AGC) at the input of the receiver is a critical block[4]. Finally the S-curve of DLL is depicted in Fig. 3.

(a)

(b) Fig. 1. (a) Time hypothesis testing for BPSK spreading. (b) Structure of the decision processor

2.2 PN Tracking Block For PN tracking, either a coherent or non coherent loop can be used. In this paper, a non coherent loop is used, which is a delay-locked loop (DLL). In our delay-locked loop, two PN sequences are delayed from each other one chip interval, and they are used for the early and late signals. The block diagram of our delay lock loop is shown in Fig. 2 [4].

Fig. 2. Block diagram of the delay-locked loop

In this diagram, the block labeled Tc represents a delay of one chip interval. The branch filters Hb(Z) are first order low-pass with band with Bb, and transfer functions given by:

Fig.3. DDLL S curve

3

HARDWARE ARCHITECTURE

In this section we explain the configurable architecture of two part of receiver synchronizer module: adaptive acquisition and Digital Delay lock loop (DDLL). The proposed architecture was modeled using the VHDL hardware description language under a structural approach [5]. The VHDL model of the proposed architecture is fully parameterisable in terms of: the arithmetic precision for data, the spreading code, and the thresholding module operation. The VHDL model was synthesized with Xilinx ISE Software targeted for Virtex4 (XC4VLX15) device and simulated with Modelsim. The use of the FPGA technology was chosen because of it provides some important advantages over general purpose processors and application specific integrated circuits (ASICs) [6] such as: i) FPGAs provide massive parallel structures and high density logic arithmetic with short design cycles compared to ASICs, ii) In FPGA devices, tasks are implemented by spatially composing primitive operators rather than temporality, iii) In FPGAs, it is possible to control operations at bit level to build specialized data-paths, iv) FPGA technology can offer potentially two orders of magnitude more raw computational power per unit of area than conventional processors, and v) FPGA technology is well suited for

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implementing parallel architectures such as pipelined and systolic processors.

3.1 Configurable CFAR architecture The main core of the architecture for the configurable adaptive acquisition is depicted in Fig. 4 The architecture composed of the match filter and the CFAR processor. The CFAR processor composed of two parts which are: reasult_3_adder and decision processor, the reasult_3_adder is a pipeline which add 3 (L=3) consecutive samples of data and sent serially to the decision processor. The operation of decision process is exactly shown in Fig. 1(b) which we choose M=8 and T=0.426. Table 1 summarizes the FPGA hardware resource utilization and timing performance of adaptive acquisition.

Fig. 5. The configurable DDLL hardware

TABLE 2: IMPLEMENTATION RESULT OF DDLL Synthesis summary for the Tracking_Block targeted for a Virtex4 (XC4VLX15) device Number of Slices 359 (5%) Number of 4-input LUTs 559 (4%) Number of flip-flops 268 (2%) Number of bonded IOBs 43 (17%) Number of GCLKs 2 (6%) Number of DSP48s 17(53%) Maximum clock frequency 250 MHz

Fig. 4. The configurable Adaptive acquisition hardware

TABLE 1: IMPLEMENTATION RESULT OF ADAPTIVE MATCH FILTER Synthesis summary for the MF_I_Q targeted for a Virtex4 (XC4VLX15) device Number of Slices 331 (21%) Number of 4-input LUTs 177 (5%) Number of flip-flops 540 (17%) Number of bonded IOBs 177(73%) Number of GCLKs 1(3%) Number of DSP48s 4(12%) Maximum clock frequency 250 MHz

3.2 Digital Delay locked loop(DDLL) The DDLL hardware composed of three parts: tracking error process (TEP), numerical control oscillator (NCO) and comparator which are depicted in Fig.5. The function of TEP is shown in Fig. 2. We use farrow [7] structure for implementation of linear interpolator and in Hb we put a=0.858. NCO use for adapt feedback sensitivity and comparator use for comparing output error with constant threshold, if error was upper than threshold, enable of tracking module go low and enable of acquisition go high. Table 2 summarizes the FPGA hardware resource utilization and timing performance of DDLL.

3.3 Final Architecture Now we can make the full hardware of adaptive synchronizer of digital DSSS receiver. The hardware architecture of this block is shown in Fig. 6. As shown this block has four units that are: adaptive match filter, DDLL, control processing unit and pipe data delay. We are familiar with two recent units, the main function control processing is to control the operation of final procedure and manage the control signals in blocks. Pipe data delay is the pipeline which generate the necessary latency for correct operation. The latency period is directly proportional to the number of cell in CFAR algorithm around the cell under test. The latency arises at the start of processing since the pipeline or shift register must be full in order to output result. Table 3 summarizes the FPGA hardware resource utilization and timing performance.

4

CONCLUSIONS

In this work an efficient hardware implementation of a class of CFAR processors and DDLL for adaptive signal processing was presented. The high performance of the proposed architecture was feasible since the employment of a parallel processing model and the arithmetic digital logic and parallel structures provided by FPGAs. The proposed architecture efficiently implements a CFAR algorithm and of course a simple and efficient algorithm for DDLL. This architecture exploits the parallel nature in signal processing and can be extended to more complex algorithms.

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TABLE 3: IMPLEMENTATION RESULT OF FINAL PROJECT

Number of GCLKs Number of DSP48s Maximum clock frequency

3 (9%) 30(93%) 250 MHz

Synthesis summary for the Final Project targeted for a Virtex4 (XC4VLX15) device Number of Slices 1947 (31%) Number of 4-input LUTs 3601 (29%) Number of flip-flops 1380 (11%) Number of bonded IOBs 96(40%)

Fig.6: The configurable final project hardware

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Spread-Spectrum Signals,” IEEE Trans. on Comun., vol. 41, no. 11, pp. 1760-1769, 1993. [5] S. Sjoholm, L. Lindh, “VHDL for Designers,” Prentice Hall, First Edition, 1997. [6] A. DeHon, “The Density Advantage of Reconfigurable Computing,” IEEE Computer, vol. 33, no. 4, pp. 41-49, 2000. [7] C.W. Farrow, “A continuously variable digital delay element,” IEEE Int. Symp. on Circuits & Syst., Espoo, Finland, pp. 2641-2645, 1988.