A

B

C

D

B

A6A

A6

1. Changed R46, R47,R48 to 0 ohms. 2. Changed R45 to 22 Ohms. Change was made due to production failures on some boards due to differences in impedances.

A5C

5

4

THERE IS NO WARRANTY FOR THIS DESIGN , TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE DESIGN “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE DESIGN IS WITH YOU. SHOULD THE DESIGN PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.

This schematic is *NOT SUPPORTED* and DOES NOT constitute a reference design. Only “community” support is allowed via resources at BeagleBoard.org/discuss.

1.Changed the processor to the AM3358BZCZ100.

4. Made R8 installed and R9 not installed.

3. Changed C24 to a 2.2uF capacitor.

2. Changed C106 to a 1uF capacitor.

1. Added optional zero ohm resistor to tie GND_OSC1 to system ground.

1. Moved the enable for the VDD_3V3B regulator to VDD_3V3A rail. Change was made to reduce the delay between the ramp up of the 3.3V rails. 2. Added a AND gate to the SYS_RESETn circuitry. There is a small chance that on power up the nRESETOUT signal on the processor may go high, causing the SYS_RESETn signal to go HI before it should. This change reenforces the reset with the PORZn reset signal. 3. Added optional zero ohm resistor to tie GND_OSC0 to system ground.

1. Added 100K pulldown on J1 pin 4 to prevent crosstalk when serial cable is not connected into PCB layout. 2. Changed the LED resistors to 4.75K to lower the brightness.

6. Added Ferrite beads in series with LED power and 5V power rail of the USB host connector. Required to pass FCC/CE testing due to noise emissions on that pin. 7. Added power button to enable sleep, wakeup, power down and power up features on the system. 8. Added Modification to add 100K ohm resistor to ground to prvent crosstalk when serial cable is not plugged in.

5. Added access point for the battery function of the TPS65217C.

4. Changed a few footprints after PCB update for above changes.

3. Changed schematic revision to A5A.

2. Added 47pf capacitors C156-C173 to LCD data lines to ground.

1/20/2014

12/13/2013

7/25/2013

6/12/2013

5/21/2013

2/8/2013

1/2/2013

On the initial production release the processors were to be found incorrect as supplied by TI. Parts while marked AM3359 were actually AM3352. This revision uses the correct parts.

1. Deleted R29-R44 from the LCD lines.

11/19/2012

3

3

GC

GC

GC

GC

GC

GC

GC

GC

DATE BY

Initial production Release.

Description

4

A5B

A5A

A5

A4A

REV

5

1

2

BeagleBone Black Cover Page Document Number B

450-5500-001 Date: Tuesday, January 21, 2014

Size

Title

1

Sheet

1

of

11

Rev B

NOTE: PCB Revision for this board is Rev B6

HDMI FRAMER EXP CONN, uSD

10 11

10/100 ETHERNET

DDR3 MEMORY

7

9

LED, CONFIGURATION AND BUTTON

6

eMMC FLASH

PROCESSOR 3 OF 3

5

8

PROCESSOR 2 OF 3, UAB PORTS

4

PROCESSOR 1 OF 3, JTAG HEADER

POWER MANAGEMENT

2 3

COVER PAGE

SCHEMATIC PAGE

1

PAGE NO.

2

A

B

C

D

A

B

C

D

11 4,10,11 4,10,11

DGND

2.2uF,6.3V

C17

SYS_5V

MHOLE

MTG4

MHOLE

MTG3

MHOLE

MTG2

MHOLE

MTG1

2

3

1

DGND

5

DGND

VDD_3V3A

PWR_BUT I2C0_SCL I2C0_SDA

4 PMIC_POWR_EN

PJ-200A

2

3

1

2 1 5 7

VDD_3V3A

OUT ADJ GND3 GND4

500mA

TL5209

3 4 6 8

3

1 4

DGND

470K,1%

DGND

R10

P_BYPASS

P_INT_LDO

4

C19 470pF,6.3V

DGND

C20 0.1uf,6.3V

VDD_3V3B 280K,1% R11

10uF,10V

SYS_5V

10uF,10V

10uF,10V

10uF,10V

SYS_5V

0.1uf,6.3V 10uF,10V

DGND

C13

C10

C8

C7

4

C1 10uF,10V

S3 KMR231GLFS 2

DGND

C4

DGND C3

POWER BUTTON

DGND

DGND

DGND

USB_DC C2 10uF,10V

VDD_5V

DGND

IN EN GND1 GND2

U4

R4

1.5K,1%

P1

R3

1.5K,1%

5

2

42

39

32

22

21

35

36

9 44 25 28 27

14

47

48

17 15

12

10

U2

TPS65217C

VINLDO

LDO4_IN

LDO3_IN

VIN_DCDC3

VIN_DCDC2

VIN_DCDC1

ISET1

ISET2

PWR_EN RESET PB_IN SCL SDA

MUX_IN

BYPASS

INT_LDO

NC1 NC

USB

AC

AGND 41

SYS1 SYS2

DGND

VLDO2

VLDO1

LDO4

LDO3

VDCDC3

L3

VDCDC2

L2

VDCDC1

L1

L4

FB_WLED

ISINK1 ISINK2

VIO PGOOD LDO_PGOOD WAKEUP INT

MUX_OUT

BAT1 BAT2 BAT_SENSE TS

PGND 30

PPAD 49

VDCDC2 P_L3 VDCDC3

24 31 29

1

3

43

3

R8

R5

R7

1

1

0

C16

C18

R9

1.5V

DGND

10uF,10V

DGND

10uF,10V

C11

VDD_CORE

2

B

1

Document Number

1

Sheet

TP1

2

of

DGND

TESTPT1

BeagleBone Black Power Management

DGND

450-5500-001 Date: Tuesday, January 21, 2014

Size

Title

R12

4.75K,5%

10uF,10V

C9

VDDS_DDR

10uF,10V

C12

PWR_LEDR LTST-C191TBKT

D1

3 3 4 3

VDD_MPU

PMIC_PGOOD LDO_PGOOD WAKEUP PMIC_INT

POWER LED

DGND

10uF,10V

C15

C14

VDD_1V8 0,1%,DNI

0,1%

VDD_3V3A

DGND

2.2uF,6.3V

DGND

2.2uF,6.3V

0,1%

0,1%

VIO

VRTC

2 LQM2HPN2R2MG0L

R6

2

Battery access pins. Pins are randomly placed to fit them in, but will be able to tie into them either with a cape or wires. Pins will not be populated.

100K,1%

R1

VDD_3V3A

VDDS

TESTPT1 TESTPT1 TESTPT1

TP6 TP7 TP8

2 LQM2HPN2R2MG0L

L3

L2

TESTPT1

TP5

2 LQM2HPN2R2MG0L

L1

VDD_3V3AUX

VLDO1

P_L2

23

40

VDCDC1

19

1

DGND

P_L1

VIO

SYS_5V

20

37

38

34 33

18 26 46 13 45

16

4 5 6 11

7 8

3

11

Rev B

A

B

C

D

A

B

C

GND_OSC0

R29

18pF,50V

C25

Y2

2

1

7

7

7

0,1%

DGND

R17 1M,1%

0,1%

7 7

7 7

DDR_D[15..0]

DDR_BA[2..0]

DDR_A[15..0]

C26 18pF,50V

OSC0_OUT1

24MHz

R30

OSC1_OUT1

DDR_BA[2..0]

DDR_DQM0 DDR_DQS0 DDR_DQSN0 DDR_DQM1 DDR_DQS1 DDR_DQSN1

DDR_ODT DDR_RESETn

7

7 7

DDR_VREF

DDR_CLK DDR_CLKn DDR_CKE DDR_CSn DDR_CASn DDR_RASn DDR_WEn

DDR_D[15..0]

5

41

OSC1_OUT GND_OSC1

OSC1_IN

OSC0_OUT GND_OSC0

OSC0_IN

DGND

DGND

0.1uf,6.3V

C28

DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 DDR_A15 DDR_BA0 DDR_BA1 DDR_BA2

32.768KHz MC-306

7 7 7 7 7 7 7

7

Y1

DDR_A[15..0]

18pF,50V

C22

18pF,50V

C21

2

3

GND_OSC0

DDR_VTP

J4

G1 G2 J3

M2 P1 P2 J2 L1 L2

D2 D1 G3 H2 F1 G4 B2

M3 M4 N1 N2 N3 N4 P3 P4 J1 K1 K2 K3 K4 L3 L4 M1

F3 H1 E4 C3 C2 B1 D5 E2 D4 C1 F4 F2 E3 H3 H4 D3 C4 E1 B3

A4 A5

A6

U11 V11

V10

AM3358BZCZ100

VREFSSTL

DDR_ODT DDR_RESETN DDR_VTP

DDR_DQM0 DDR_DQS0 DDR_DQSN0 DDR_DQM1 DDR_DQS1 DDR_DQSN1

DDR_CK DDR_NCK DDR_CKE DDR_CSN0 DDR_CASN DDR_RASN DDR_WEn

DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 DDR_A15 DDR_BA0 DDR_BA1 DDR_BA2

OSC1_OUT VSS_RTC

OSC1_IN

OSC0_OUT VSS_OSC0

OSC0_IN

U5A

1.8V

Y

4

DGND

3.3V PORZn NRESET_INOUT

1.8V RTC_PORZn

1.8V

SN74LVC1G07DCK

NTRST TMS TDI TCK TDO EMU0/GPIO3_7 EMU1/GPIO3_8

NNMI EVENT_INTR0/TIMER4/CLKOUT1/SPI1_CS1/PR1PRU1R31_16/EMU2/GPIO0_19 EVENT_INTR1/TCLKIN/CLKOUT2/TIMER7/PR1PRU0_PRUR31_16/EMU3/GPIO0_20

LDO_PGOOD

2 PMIC_PGOOD

A

4

JTAG_TDO JTAG_TCK

JTAG_TMS JTAG_TDI

DGND

0.1uf,6.3V

C30

MMC0_CD

DGND

TRSTn TDIS NC GND1 GND2 GND3 EMU1 GND4 EMU3 GND5

CTI JTAG,DNI

TMS TDI TVDD TDO TCKRTN TCK EMU0 SRST EMU2 EMU4

P2

0.1uf,6.3V

C29

1 3 5 7 9 11 13 15 17 19

VDD_3V3B

JTAG_EMU0 SYS_RESETn XDMA_EVENT_INTR0 4,11

4.75K,1%

R23

VDD_3V3B 2 4 6 8 10 12 14 16 18 20

DGND

DGND JTAG_EMU1

3

R25 4.75K,1%

DGND

JTAG_TRSTn

CLKOUT2

R24 4.75K,1%

VDD_3V3B

3,11

MMC0_CLK/GPMC_A24/UART3_CTSN/UART2_RXD/DCAN1_TX/PR1_PRU0_PRU_R30_12/PR1_PRU0_PRU_R31_12/GPIO2_30 MMC0_CMD/GPMC_A25/UART3_RTSN/UART2_TXD/DCAN1_RX/PR1_PRU0_PRU_R30_13/PR1_PRU0_PRU_R31_13/GPIO2_31 MMC0_DAT0/GPMC_A23/UART5_RTSN/UART3_TXD/UART1_RIN/PR1_PRU0_PRU_R30_11/PR1_PRU0_PRU_R31_11/GPIO2_29 MMC0_DAT1/GPMC_A22/UART5_CTSN/UART3_RXD/UART1_DTRN/PR1_PRU0_PRU_R30_10/PR1_PRU0_PRU_R31_10/GPIO2_28 MMC0_DAT2/GPMC_A21/UART4_RTSN/TIMER6/UART1_DSRN/PR1_PRU0_PRU_R30_9/PR1_PRU0_PRU_R31_9/GPIO2_27 MMC0_DAT3/GPMC_A20/UART4_CTSN/TIMER5/UART1_DCDN/PR1_PRU0_PRU_R30_8/PR1_PRU0_PRU_R31_8/GPIO2_26

GPMC_A0/GMII2_TXEN/RGMII2_TCTL/RMII2_TXEN/GPMC_A16/PR1_MII_MT1_CLK/EHRPWM1_TRIPZONE_INPUT/GPIO1_16 GPMC_A1/GMII2_RXDV/RGMII2_RCTL/MMC2_DAT0/GPMC_A17/PR1_MII1_TXD3/EHRPWM1_SYNCI_O/GPIO1_17 GPMC_A2/GMII2_TXD3/RGMII2_TD3/MMC2_DAT1/GPMC_A18/PR1_MII1_TXD2/EHRPWM1A/GPIO1_18 GPMC_A3/GMII2_TXD2/RGMII2_TD2/MMC2_DAT2/GPMC_A19/PR1_MII1_TXD1/EHRPWM1B/GPIO1_19 GPMC_A4/GMII2_TXD1/RGMII2_TD1/RMII2_TXD1/GPMC_A20/PR1_MII1_TXD0/EQEP1A_IN/GPIO1_20 GPMC_A5/GMII2_TXD0/RGMII2_TD0/RMII2_TXD0/GPMC_A21/PR1_MII1_RXD3/EQEP1B_IN/GPIO1_21 GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/PR1_MII1_RXD2/EQEP1_INDEX/GPIO1_22 GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/PR1_MII1_RXD1/EQEP1_STROBE/GPIO1_23 GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/PR1_MII1_RXD0/MCASP0_ACLKX/GPIO1_24 GPMC_A9/GMII2_RXD2/RGMII2_RD2/MMC2_DAT7/GPMC_A25/PR1_MII_MR1_CLK/MCASP0_FSX/GPIO1_25 GPMC_A10/GMII2_RXD1/RGMII2_RD1/RMII2_RXD1/GPMC_A26/PR1_MII1_CRS/MCASP0_AXR0/GPIO1_26 GPMC_A11/GMII2_RXD0/RGMII2_RD0/RMII2_RXD0/GPMC_A27/PR1_MII1_RXER/MCASP0_AXR1/GPIO1_27

GPMC_AD0/MMC1_DAT0//////GPIO1_0 GPMC_AD1/MMC1_DAT1//////GPIO1_1 GPMC_AD2/MMC1_DAT2//////GPIO1_2 GPMC_AD3/MMC1_DAT3//////GPIO1_3 GPMC_AD4/MMC1_DAT4//////GPIO1_4 GPMC_AD5/MMC1_DAT5//////GPIO1_5 GPMC_AD6/MMC1_DAT6//////GPIO1_6 GPMC_AD7/MMC1_DAT7//////GPIO1_7 GPMC_AD8/LCD_DATA23/MMC1_DAT0/MMC2_DAT4/EHRPWM2A/PR1_MII_MT0_CLK//GPIO0_22 GPMC_AD9/LCD_DATA22/MMC1_DAT1/MMC2_DAT5/EHRPWM2B/PR1_MII0_CRS//GPIO0_23 GPMC_AD10/LCD_DATA21/MMC1_DAT2/MMC2_DAT6/EHRPWM2_TRIPZONE_INPUT/PR1_MII0_TXEN//GPIO0_26 GPMC_AD11/LCD_DATA20/MMC1_DAT3/MMC2_DAT7/EHRPWM2_SYNCI_O/PR1_MII0_TXD3//GPIO0_27 GPMC_AD12/LCD_DATA19/MMC1_DAT4/MMC2_DAT0/EQEP2A_IN/PR1_MII0_TXD2/PR1_PRU0_PRU_R30_14/GPIO1_12 GPMC_AD13/LCD_DATA18/MMC1_DAT5/MMC2_DAT1/EQEP2B_IN/PR1_MII0_TXD1/PR1_PRU0_PRU_R30_15/GPIO1_13 GPMC_AD14/LCD_DATA17/MMC1_DAT6/MMC2_DAT2/EQEP2_INDEX/PR1_MII0_TXD0/PR1_PRU0_PRU_R31_14/GPIO1_14 GPMC_AD15/LCD_DATA16/MMC1_DAT7/MMC2_DAT3/EQEP2_STROBE/PR1_ECAP0_ECAP_CAPIN_APWM_O/PR1_PRU0_PRU_R31_15/GPIO1_15

GPMC_CLK/LCD_MEM_CLK/GPMC_WAIT1/MMC2_CLK/PRT1_MII1_TXEN/MCASP0_FSR/GPIO2_1 GPMC_CSN0/GPIO1_29 GPMC_CSN1/GPMC_CLK/MMC1_CLK/PRT1EDIO_DATA_IN6/PRT1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_12/PR1_PRU1_PRU_R31_12/GPIO1_30 GPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31 GPMC_CSN3/MMC2_CMD/PR1_MDIO_DATA/GPIO2_0 GPMC_WEN/TIMER6/GPIO2_4 GPMC_OEN_REN/TIMER7/EMU4/GPIO2_3 GPMC_ADVN_ALE/TIMER4/GPIO2_2 GPMC_BE0N_CLE/TIMER5/GPIO2_5 GPMC_BE1N/GMII2_COL/GPMC_CSN6/MMC2_DAT3/GPMC_DIR/PR1_MII1_RXLINK/MCASP0_ACLKR/GPIO1_28 GPMC_WAIT0/GM112_CRS/GPMC_CSN4/RMII2_CRS_DV/MMC1_SDCD/PR1_MII1_RXDV/UART4_RXD/GPIO0_30 GPMC_WPN/GMII2_RXERR/GPMC_CSN5/RMII2_RXERR/MMC2_SDCD/PR1_MDIO_MDCLK/UART4_TXD/GPIO0_31

15mm x 15mm Package

SubArctic AM335x

2

2

U16

VIO

5

3

NC 1

VCC GND 3

D

R22

49.9,1%

4

G17 G18 G16 G15 F18 F17

R13 V14 U14 T14 R14 V15 U15 T15 V16 U16 T16 V17

U7 V7 R8 T8 U8 V8 R9 T9 U10 T10 T11 U12 T12 R12 V13 U13

V12 V6 U9 V9 T13 U6 T7 R7 T6 U18 T17 U17

B10 C11 B11 A12 A11 C14 B14

B18 A15 D14

B15 A10 B5

H

R18

U5_R13

U5_T13

JTAG_TRSTn JTAG_TMS JTAG_TDI JTAG_TCK JTAG_TDO JTAG_EMU0 JTAG_EMU1

PROC_A15

DGND

2

2

A

U3

DGND

CLK

VCC

0.1uf,6.3V

R162

DGND

0.1uf,6.3V

C159

R167

VDD_3V3A

33

2

4

3,11

12MHZ

GPIO3_21

External clock to the McASP0 interface.

0,1%

eMMC_RSTn

Oscillator can be disabled via SW for power down modes or if GPIO3_21 needs to be used.

33

10

GPIO1_16

CEC Clock for HDMI Framer

R21

GPIO3_20

CLKOUT2

1

8

4,11

11

Document Number

1

Sheet

3

of

BeagleBone Black Processor 1 of 3 and JTAG

DGND

3

4

DGND

0.1uf,6.3V

C27

0,1%

9,11 PMIC_INT

SYS_RESETn

450-5500-001 Date: Tuesday, January 21, 2014

C

Size

Title

R20

VDD_3V3A

24.576MHZ

GND

OE

Y4

C158

2

1

0,1%

0,1%

8 7 6 5

SN74LVC1G06DCK

4

VDD_3V3A

DGND

R160

Y

CLK VCC D PRE Q CLR GND Q

U6

0,1%

SN74AUC1G74

1 2 3 4

R161

DGND

12M_LOOP

HDMICLK_DISn

11 11 11 11 11 11

6 6 6 6 10 4 USR0 USR1 USR2 USR3 HDMI_INT USB1_OCn

MMC0_CLKO MMC0_CMD MMC0_DAT0 MMC0_DAT1 MMC0_DAT2 MMC0_DAT3

11 11 11

8,11 8,11 8,11 8,11 8,11 8,11 8,11 8,11 11 11 11 11 11 11 11 11 GPIO1_17 EHRPWM1A EHRPWM1B

MMC1_DAT0 MMC1_DAT1 MMC1_DAT2 MMC1_DAT3 MMC1_DAT4 MMC1_DAT5 MMC1_DAT6 MMC1_DAT7 EHRPWM2A EHRPWM2B GPIO0_26 GPIO0_27 GPIO1_12 GPIO1_13 GPIO1_14 GPIO1_15

11 11 11 11 11 11 11

TIMER6 TIMER7 TIMER4 TIMER5 GPIO1_28 UART4_RXD UART4_TXD

R19

C24 2.2uF,10V

R14 10K,1%

VDD_3V3A

XDMA_EVENT_INTR0 CLKOUT_SRC

11 11 8,11 8,11

33

RESET

4

S1 KMR231GLFS 2

GPIO2_1 GPIO1_29 MMC1_CLK MMC1_CMD

DGND

3

1

3.3V

2

5 VCC

5

NC 1

GND 3

11

Rev B

A

B

C

D

A

B

C

1 2 3 4 5 6

+

DGND

100uF,6.3V

C34

SYS_5V

0.1uf,6.3V

DGND

DGND

DGND

U8

11 11 11 11 11 11 11

VCC 2OE 1Y 2A

U15

C155

UART1_TXD

I2C2_SCL

11

5

8 7 6 5 9

R50

R52

10K,1%

DGND

R49

3

2

1

0,1%

0,1% USB1_DP USB1_DM

USB0_ID

USB0_DP USB0_DM

GND

NC

TPD4S012

ID

D-

VBUS

4

5

6

DGND

15mm x 15mm Package

SubArctic AM335X

3

GMII1_RXCLK/UART2_TXD/RGMII1_RCLK/MMC0_DAT6/MMC1_DAT1/UART1_DSRN/MCASP0_FSX/GPIO3_10 GMII1_RXD0/RMII1_RXD0/RGMII1_RD0/MCASP1_AHCLKX/MCASP1_AHCLKR/MCASP1_ACLKR/MCASP0_AXR3/GPIO2_21 GMII1_RXD1/RMII1_RXD1/RGMII1_RD1/MCASP1_AXR3/MCASP1_FSR/EQEP0_STROBE/MMC2_CLK/GPIO2_20 GMII1_RXD2/UART3_TXD/RGMII1_RD2/MMC0_DAT4/MMC1_DAT3/UART1_RIN/MCASP0_AXR1/GPIO2_19 GMII1_RXD3/UART3_RXD/RGMII1_RD3/MMC0_DAT5/MMC1_DAT2/UART1_DTRN/MCASP0_AXR0/GPIO2_18 GMII1_RXERR/RMII1_RXERR/SPI1_D1/I2C1_SCL/MCASP1_FSX/UART5_RTSN/UART2_TXD/GPIO3_2 GMII1_RXDV/LCD_MEMORY_CLK/RGMII1_RCTL/UART5_TXD/MCASP1_ACLKX/MMC2_DAT0/MCASP0_ACLKR/GPIO3_4

GMII1_TXCLK/UART2_RXD/RGMII1_TCLK/MMC0_DAT7/MMC1_DAT0/UART1_DCDN/MCASP0_ACLKX/GPIO3_9 GMII1_TXD0/RMII1_TXD0/RGMII1_TD0/MCASP1_AXR2/MCASP1_ACLKR/EQEP0B_IN/MMC1_CLK/GPIO0_28 GMII1_TXD1/RMII1_TXD1/RGMII1_TD1/MCASP1_FSR/MCASP1_AXR1/EQEP0A_IN/MMC1_CMD/GPIO0_21 GMII1_TXD2/DCAN0_RX/RGMII1_TD2/UART4_TXD/MCASP1_AXR0/MMC2_DAT2/MCASP0_AHCLKX/GPIO0_17 GMII1_TXD3/DCAN0_TX/RGMII1_TD3/UART4_RXD/MCASP1_FSX/MMC2_DAT1/MCASP0_FSR/GPIO0_16 GMII1_TXEN/RMII1_TXEN/RGMII1_TCTL/TIMER4/MCASP1_AXR0/EQEP0_INDEX/MMC2_CMD/GPIO3_3 GMII1_CRS/RMII1_CRS_DV/SPI1_D0/I2C1_SDA/MCASP1_ACLKX/UART5_CTSN/UART2_RXD/GPIO3_1 GMII1_COL/RMII2_REFCLK/SPI1_SCLK/UART5_RXD/MCASP1_AXR2/MMC2_DAT3/MCASP0_AXR2/GPIO3_0

2

4

AM3358BZCZ100

FB7

USB1_OCn

DGND

1 2 VBUS 150OHM800mA

3

1 VBUS 2 D3 D+ 4 GND SHIELD

SHIELD

P3 87520-0010BLF

6

5

3

3

2

1

GND

NC

VBUS

TPD4S012

ID

D-

D+

U10

4

5

6

USB0_ID USB0_DP USB0_DM

DGND

0.1uf,6.3V

C36

USB_DC

DGND

5 4 3 2 1

P4

G1 ID D+ DVB

2

USB PC CONNECTOR

USB5MINI

LCDPCLK LCDVSYNC LCDVHYNC LCDDE

R45 R46 R47 R48

R28

22 0 0 0

33

1

3,11 10,11 10,11 11 10,11 11 3 GPIO3_19 GPIO3_20

10,11 10,11 10,11 10,11

6,10,11 6,10,11 6,10,11 6,10,11 6,10,11 6,10,11 6,10,11 6,10,11 6,10,11 6,10,11 6,10,11 6,10,11 6,10,11 6,10,11 6,10,11 6,10,11

9 9 9

9 9 9 9 9 9 9

9 9 9 9 9 9 9 9

GPIO3_21 SPI1_SCLK SPI1_D0 SPI1_D1 SPI1_CS0

LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_DE

LCD_DATA0 LCD_DATA1 LCD_DATA2 LCD_DATA3 LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7 LCD_DATA8 LCD_DATA9 LCD_DATA10 LCD_DATA11 LCD_DATA12 LCD_DATA13 LCD_DATA14 LCD_DATA15

MII1_REFCLK MDIO_CLK MDIO_DATA

MII1_RXCLK MII1_RXD0 MII1_RXD1 MII1_RXD2 MII1_RXD3 MII1_RXERR MII1_RXDV

MII1_TXCLK MII1_TXD0 MII1_TXD1 MII1_TXD2 MII1_TXD3 MII1_TXEN MII1_CRS_DV MII1_COL

Document Number

1

Sheet

4

of

11

Rev B

BeagleBone Black Processor 2 of 3, USB, and Serial

A14 A13 B13 D12 C12 B12 C13 D13

V5 U5 R5 R6

R1 R2 R3 R4 T1 T2 T3 T4 U1 U2 U3 U4 V2 V3 V4 T5

H18 U5_H18 M18 M17

L18 M16 L15 L16 L17 J15 J17

K18 K17 K16 K15 J18 J16 H17 H16

450-5500-001 Date: Tuesday, January 21, 2014

C

Size

Title

MCASP0_AHCLKX/EQEP0_STROBE/MCASP0_AXR3/MCASP1_AXR1/EMU4/PR1_PRU0_PRU_R30_7/PR1_PRU0_PRU_R31_7/GPIO3_21 MCASP0_ACLKX/EHRPWM0A//SPI1_SCLK/MMC0_SDCD/PR1_PRU0_PRU_R30_0/PR1_PRU0_PRU_R31_0/GPIO3_14 MCASP0_FSX/EHRPWM0B//SPI1_D0/MMC1_SDCD/PR1_PRU0_PRU_R30_1/PR1_PRU0_PRU_R31_1/GPIO3_15 MCASP0_AXR0/EHRPWM0_TRIPZONE_INPUT//SPI1_D1/MMC2_SDCD/PR1_PRU0_PRU_R30_2/PR1_PRU0_PRU_R31_2/GPIO3_16 MCASP0_AHCLKR/EHRPWM0_SYNCI_O/MCASP0_AXR2/SPI1_CS0/ECAP2_IN_PWM2_OUT/PR1_PRU0_PRU_R30_3/PR1_PRU0_PRU_R31_3/GPIO3_17 MCASP0_ACLKR/EQEP0A_IN/MCASP0_AXR2/MCASP1_ACLKX/MMC0_SDWP/PR1_PRU0_PRU_R30_4/PR1_PRU0_PRU_R31_4/GPIO3_18 MCASP0_FSR/EQEP0B_IN/MCASP0_AXR3/MCASP1_FSX/EMU2/PR1_PRU0_PRU_R30_5/PR1_PRU0_PRU_R31_5/GPIO3_19 MCASP0_AXR1/EQEP0_INDEX//MCASP1_AXR0/EMU3/PR1_PRU0_PRU_R30_6/PR1_PRU0_PRU_R31_6/GPIO3_20

LCD_PCLK/GPMC_A10//PR1_EDIO_DATA_IN4/PR1_EDIO_DATA_OUT4/PR1_PRU1_PRU_R30_10/PR1_PRU1_PRU_R31_10/GPIO2_24 LCD_VSYNC/GPMC_A8//PR1_EDIO_DATA_IN2/PR1_EDIO_DATA_OUT2/PR1_PRU1_PRU_R30_8/PR1_PRU1_PRU_R31_8/GPIO2_22 LCD_HSYNC/GPMC_A9//PR1_EDIO_DATA_IN3/PR1_EDIO_DATA_OUT3/PR1_PRU1_PRU_R30_9/PR1_PRU1_PRU_R31_9/GPIO2_23 LCD_AC_BIAS_EN/GPMC_A11//PR1_EDIO_DATA_IN5/PR1_EDIO_DATA_OUT5/PR1_PRU1_PRU_R30_11/PR1_PRU1_PRU_R31_11/GPIO2_25

ECAP0_IN_PWM0_OUT/UART3_TXD/SPI1_CS1/PR1_ECAP0_ECAP_CAPIN_APWM_O/SPI1_SCLK/MMC0_SDWP/XDMA_EVENT_INTR2/GPIO0_7

USB1_DP USB1_DM USB1_CE USB1_ID USB1_DRVVBUS/GPIO3_13 USB1_VBUS

USB0_DP USB0_DM USB0_CE USB0_ID USB0_DRVVBUS/GPIO0_18 USB0_VBUS

SPI0_SCLK/UART2_RXD/I2C2_SDA/EHRPWM0A/PR1_UART0_CTS_N/PR1_EDIO_SOF/EMU2/GPIO0_2 RMII1_REFCLK/XDMA_EVENT_INTR2/SPI1_CS0/UART5_TXD/MCASP1_AXR3/MMC0_POW/MCASP1_AHCLKX/GPIO0_29 SPI0_D0/UART2_TXD/I2C2_SCL/EHRPWM0B/PR1_UART0_RTS_N/PR1_EDIO_LATCH_IN/EMU3/GPIO0_3 MDIO_CLK/TIMER5/UART5_TXD/UART3_RTSN/MMC0_SDWP/MMC1_CLK/MMC2_CLK/GPIO0_1 SPI0_D1/MMC1_SDWP/I2C1_SDA/EHRPWM0_TRIPZONE_INPUT/PR1_UART0_RXD/PR1_EDIO_DATA_IN0/PR1_EDIO_DATA_OUT0/GPIO0_4 MDIO_DATA/TIMER6/UART5_RXD/UART3_CTSN/MMC0_SDCD/MMC1_CMD/MMC2_CMD/GPIO0_0 SPI0_CS0/MMC2_SDWP/I2C1_SCL/EHRPWM0_SYNCI_O/PR1_UART0_TXD/PR1_EDIO_DATA_IN1/PR1_EDIO_DATA_OUT1/GPIO0_5 SPI0_CS1/UART3_RXD/ECAP1_IN_PWM1_OUT/MMC0_POW/XDMA_EVENT_INTR2/MMC0_SDCD/EMU4/GPIO0_6 LCD_DATA0/GPMC_A0//EHRPWM2A//PR1_PRU1_PRU_R30_0/PR1_PRU1_PRU_R31_0/GPIO2_6 UART0_TXD/SPI1_CS1/DCAN0_RX/I2C2_SCL/ECAP1_IN_PWM1_OUT/PR1_PRU1_PRU_R30_15/PR1_PRU1_PRU_R31_15/GPIO1_11 LCD_DATA1/GPMC_A1//EHRPWM2B//PR1_PRU1_PRU_R30_1/PR1_PRU1_PRU_R31_1/GPIO2_7 UART0_RXD/SPI1_CS0/DCAN0_TX/I2C2_SDA/ECAP2_IN_PWM2_OUT/PR1_PRU1_PRU_R30_14/PR1_PRU1_PRU_R31_14/GPIO1_10 LCD_DATA2/GPMC_A2//EHRPWM2_TRIPZONE_INPUT//PR1_PRU1_PRU_R30_2/PR1_PRU1_PRU_R31_2/GPIO2_8 UART0_CTSN/UART4_RXD/DCAN1_TX/I2C1_SDA/SPI1_D0/TIMER7/PR1_EDC_SYNC0_OUT/GPIO1_8 LCD_DATA3/GPMC_A3//EHRPWM2_SYNCI_O//PR1_PRU1_PRU_R30_3/PR1_PRU1_PRU_R31_3/GPIO2_9 UART0_RTSN/UART4_TXD/DCAN1_RX/I2C1_SCL/SPI1_D1/SPI1_CS0/PR1_EDC_SYNC1_OUT/GPIO1_9 LCD_DATA4/GPMC_A4//EQEP2A_IN//PR1_PRU1_PRU_R30_4/PR1_PRU1_PRU_R31_4/GPIO2_10 LCD_DATA5/GPMC_A5//EQEP2B_IN//PR1_PRU1_PRU_R30_5/PR1_PRU1_PRU_R31_5/GPIO2_11 LCD_DATA6/GPMC_A6/PR1_EDIO_DATA_IN6/EQEP2_INDEX/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_6/PR1_PRU1_PRU_R31_6/GPIO2_12 LCD_DATA7/GPMC_A7/PR1_EDIO_DATA_IN7/EQEP2_STROBE/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_7/PR1_PRU1_PRU_R31_7/GPIO2_13 LCD_DATA8/GPMC_A12/EHRPWM1_TRIPZONE_INPUT/MCASP0_ACLKX/UART5_TXD/PR1_MII0_RXD3/UART2_CTSN/GPIO2_14 UART1_TXD/MMC2_SDWP/DCAN1_RX/I2C1_SCL//PR1_UART0_TXD/PR1_PRU0_PRU_R31_16/GPIO0_15 LCD_DATA9/GPMC_A13/EHRPWM1_SYNCI_O/MCASP0_FSX/UART5_RXD/PR1_MII0_RXD2/UART2_RTSN/GPIO2_15 UART1_RXD/MMC1_SDWP/DCAN1_TX/I2C1_SDA//PR1_UART0_RXD/PR1_PRU1_PRU_R31_16/GPIO0_14 LCD_DATA10/GPMC_A14/EHRPWM1A/MCASP0_AXR0//PR1_MII0_RXD1/UART3_CTSN/GPIO2_16 UART1_CTSN/TIMER6/DCAN0_TX/I2C2_SDA/SPI1_CS0/PR1_UART0_CTS_N/PR1_EDC_LATCH0_IN/GPIO0_12 LCD_DATA11/GPMC_A15/EHRPWM1B/MCASP0_AHCLKR/MCASP0_AXR2/PR1_MII0_RXD0/UART3_RTSN/GPIO2_17 UART1_RTSN/TIMER5/DCAN0_RX/I2C2_SCL/SPI1_CS1/PR1_UART0_RTS_N/PR1_EDC_LATCH1_IN/GPIO0_13 LCD_DATA12/GPMC_A16/EQEP1A_IN/MCASP0_ACLKR/MCASP0_AXR2/PR1_MII0_RXLINK/UART4_CTSN/GPIO0_8 LCD_DATA13/GPMC_A17/EQEP1B_IN/MCASP0_FSR/MCASP0_AXR3/PR1_MII0_RXER/UART4_RTSN/GPIO0_9 I2C0_SCL/TIMER7/UART2_RTSN/ECAP1_IN_PWM1_OUT////GPIO3_6 LCD_DATA14/GPMC_A18/EQEP1_INDEX/MCASP0_AXR1/UART5_RXD/PR1_MII_MR0_CLK/UART5_CTSN/GPIO0_10 I2C0_SDA/TIMER4/UART2_CTSN/ECAP2_IN_PWM2_OUT////GPIO3_5 LCD_DATA15/GPMC_A19/EQEP1_STROBE/MCASP0_AHCLKX/MCASP0_AXR3/PR1_MII0_RXDV/UART5_RTSN/GPIO0_11

VREFP VREFN

AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7

0.1uf,6.3V

C35

4

PMIC_POWER_EN 1.8V EXT_WAKEUP 1.8V

U5B

FB8 1 2 0.1 Ohm,0805

GPIO3_18

USB1_PWR USB1_DM USB1_DP

D+

U9

R17 R18 P18 P17 F15 T18

N17 N18 M15 P16 F16 P15

C16 C17

D15 D16 D18 D17

E16 E15 E18 E17

A17 B17 B16 A16 C15

B9 A9

B6 C7 B7 A7 C8 B8 A8 C9

C6 C5

GPIO0_7SRC C18

0,1% USB1_ID USB1_DRVVBUS USB1_VBUS

0,1%

I2C0_SCL I2C0_SDA

VDD_3V3A

R51

DGND

USB_DC

2,10,11 2,10,11

TP9 TESTPT1

UART0_TX UART0_RX

R26 4.75K,1%

VRTC

R159

VDD_3V3B

UART2_RXD UART2_TXD I2C1_SDA I2C1_SCL MMC0_CD

11

8 7 6 5

11 11 11 11 3,11

AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6

2 PMIC_POWR_EN 2 WAKEUP

VREFP_ADC VREFN_ADC

SN74LVC2G241

1OE 1A 2Y GND

TPS2051 (DGN)

IN1 OUT1 IN2 OUT2 EN OUT3 GND OC PAD

USB HOST

R53 10K,1%

2 3 4 1

GPIO0_7

USB1_DRVVBUS

11

1 2 3 4

0.1uf,6.3V

DGND

R164 4.75K,1%

AIN7

R163 4.75K,1%

VDD_3V3B

11 UART1_RXD POWERDOWN ISOLATION DGND 11 I2C2_SDA

DGND

B_UART0_RX B_UART0_TX

GNDA_ADC

C32

UART0 Serial Port USB to TTL Serial Cable 3.3V

HEADER 6

Mark pin 1 clearly

J1

0.001uf,50V

GNDA_ADC

0.1uf,6.3V

C31

C33

R27 0,1%

VDD_ADC

R165

100K,1%

D

5

9 G4

8 G5 G2 7

G3 6

A

B

C

D

C41

0.1uf,6.3V

C40

10uF,10V

C78 0.1uf,6.3V

C101 0.1uf,6.3V

4

E5 F5 G5 H5 J5 K5 L5

E7

0.1uf,6.3V

C103

DGND

C102 0.1uf,6.3V

DGND

0.1uf,6.3V

DGND

N14

R15 R16

M14

N15 N16

D10 D11 C10 E9

D9 H15

F10 F11 F12 F13 G13 H13 J13 A2

VDDS_DDR1 VDDS_DDR2 VDDS_DDR3 VDDS_DDR4 VDDS_DDR5 VDDS_DDR6 VDDS_DDR7

VDDS_PLL_DDR

VSSA_USB1

VDDA3P3V_USB1 VDDA1P8V_USB1

VSSA_USB2

VDDA3P3V_USB0 VDDA1P8V_USB0

VDDS_SRAM_MPU_BB CAP_VDD_SRAM_MPU CAP_VBB_MPU VDDS_SRAM_CORE_BG

CAP_VDD_SRAM_CORE VDDS_PLL_MPU

VDD_MPU1 VDD_MPU2 VDD_MPU3 VDD_MPU4 VDD_MPU5 VDD_MPU6 VDD_MPU7 VDD_MPU_MON

VDD_CORE1 VDD_CORE2 VDD_CORE3 VDD_CORE4 VDD_CORE5 VDD_CORE6 VDD_CORE7 VDD_CORE8 VDD_CORE9 VDD_CORE10 VDD_CORE11 VDD_CORE12 VDD_CORE13 VDD_CORE14 VDD_CORE15 VDD_CORE16 VDD_CORE17 VDD_CORE18 VDD_CORE19 VDD_CORE20

15mm x 15mm Package

SubArctic AM335X

DGND

3

AM3358BZCZ100

TESTOUT

VDDS_OSC

VDDS_RTC CAP_VDD_RTC ENZ_KALDO_1P8V

VPP VDDS_PLL_CORE_LCD

VSSA_ADC

VDDA_ADC

VDDS1 VDDS2 VDDS3 VDDS4 VDDS5 VDDS6 VDDS7

VDDSHV61 VDDSHV62 VDDSHV63 VDDSHV64 VDDSHV65 VDDSHV66 VDDSHV67 VDDSHV68 VDDSHV69

VDDSHV51 VDDSHV52

VDDSHV41 VDDSHV42

VDDSHV31 VDDSHV32

VDDSHV21 VDDSHV22

VDDSHV11 VDDSHV12

A3

R11

D7 D6 B4

M5 R10

E8

D8

E6 E14 F9 K13 N6 P9 P14

E10 E11 E12 E13 F14 G14 N5 P5 P6

K14 L14

H14 J14

P12 P13

P10 P11

P7 P8

TESTPT1

TP3 TESTOUT

DGND

2

C60 0.1uf,6.3V

C58 0.1uf,6.3V

C56 0.1uf,6.3V

C37 0.1uf,6.3V

C61 0.1uf,6.3V

C59 0.1uf,6.3V

DGND

1uF,10V

C106

GNDA_ADC

FB2 2

VDD_PLL

GNDA_ADC

DGND

DGND

FB3 2

BeagleBone Black Processr 3 of 3

VDD_PLL

Title

DGND

C94 0.1uf,6.3V

1

150OHM800mA

1

VDD_3V3A

C77 C76 0.1uf,6.3V10uF,10V

0.1uf,6.3V

C85

VDD_1V8

0.1uf,6.3V

C84

150OHM800mA

1

0.1uf,6.3V

C83

C93 0.1uf,6.3V

0.1uf,6.3V

C82

VDDS

C75 0.1uf,6.3V

DGND

DGND

C57 0.1uf,6.3V

C38 0.1uf,6.3V

C71 C72 C73 C74 0.1uf,6.3V0.1uf,6.3V0.1uf,6.3V0.1uf,6.3V

0.1uf,6.3V

C104 C105 1uF,10V 10K,1%

R54

VRTC

0.1uf,6.3V

0.1uf,6.3V

DGND

VDD_RTC ENZ_KALDO_1P8V

VDD_ADC

C81

C80

C70 0.1uf,6.3V

0.1uf,6.3V

C69 0.1uf,6.3V

0.1uf,6.3V

C68 0.1uf,6.3V

C67

C66

2

5

of

11

Rev B

C

D

Document Number

450-5500-001 Date: Tuesday, January 21, 2014

C

Size

1

Sheet

A

C100 0.1uf,6.3V

VDD_PLL C92

CAP_VDD_SRAM_MPU CAP_VBB_MPU

VDD_MPUON TESTPT1 CAP_VDD_SRAM_CORE

VDD_MPU

F6 F7 G6 G7 G10 H11 J12 K6 K8 K12 L6 L7 L8 L9 M11 M13 N8 N9 N12 N13

U5C

3

A

C99 0.1uf,6.3V

DGND

0.1uf,6.3V

C88

TP2

0.1uf,6.3V

DGND

0.1uf,6.3V

C87 0.1uf,6.3V

C98 0.1uf,6.3V

0.1uf,6.3V

C86

VDD_1V8

C97 0.1uf,6.3V

VDD_PLL

0.1uf,6.3V

VDD_CORE

4

B

10uF,10V

VDDS_DDR

10uF,10V

5

C62

10uF,10V

VDD_3V3A VDD_1V8

C96

DGND

C95

DGND

150OHM800mA

C79 0.1uf,6.3V

C42

0.1uf,6.3V

B

C

VDD_1V8

C43

0.1uf,6.3V

FB1 2

C44

0.1uf,6.3V

1

C45

0.1uf,6.3V

C65

C46

0.1uf,6.3V

C64

C47

0.1uf,6.3V

C63

C48

0.1uf,6.3V

VDD_MPU

C49

0.1uf,6.3V

DGND

C50

0.1uf,6.3V

C89 1uF,10V

10uF,10V

C51 0.1uf,6.3V

C90 1uF,10V

D

C55

C54

C53

C52 0.1uf,6.3V

C91 1uF,10V

C39 0.1uf,6.3V

VDD_CORE

10uF,10V

0.1uf,6.3V

5

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 A1 A18 F8 G8 G9 G11 G12 H6 H7 H8 H9 H10 H12 J6 J7 J8 J9 J10 J11 K7 K9 K10 K11 L10 L11 L12 L13 M6 M7 M8 M9 M10 M12 N7 N10 N11 V1 V18

4

DGND

3

3 3 3

3

USR1 USR2 USR3

USR0

DGND

R76 100K,1%

2

User LED's

DGND

DMC56404

Q1A

5

R77 100K,1%

DGND

LTST-C191TBKT

USR0

D2

2

Title

R78 100K,1%

2

LTST-C191TBKT

DMC56404

Q2A

USR2

D4

R79 100K,1%

5

DGND DGND

LTST-C191TBKT

DGND

DMC56404

Q2B

USR3

D5

R71 4.75K,5%

BeagleBone Black LED, Configuration, and Reset

DMC56404

DGND

LTST-C191TBKT

USR1

Q1B

DGND

D3

R74 4.75K,5%

Rev B

C

D

Document Number B

450-5500-001 Date: Tuesday, January 21, 2014

Size

1

Sheet

6

of

11

A

5

4

uSD BOOT

R73 4.75K,5%

1

A

3

2

B

4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11

R72 4.75K,5%

SYS_5V

B

DGND

LCD_DATA0 LCD_DATA1 LCD_DATA2 LCD_DATA3 LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7 LCD_DATA8 LCD_DATA9 LCD_DATA10 LCD_DATA11 LCD_DATA12 LCD_DATA13 LCD_DATA14 LCD_DATA15

100,1%

S2 KMR231GLFS 1 2

3

47k

Boot Configuration

SYS_BOOT0 SYS_BOOT1 SYS_BOOT2 SYS_BOOT3 SYS_BOOT4 SYS_BOOT5 SYS_BOOT6 SYS_BOOT7 SYS_BOOT8 SYS_BOOT9 SYS_BOOT10 SYS_BOOT11 SYS_BOOT12 SYS_BOOT13 SYS_BOOT14 SYS_BOOT15

R75

4

10k

C

D

VDD_3V3A

100K,1%,DNI 100K,1% 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1% 100K,1% 100K,1% 100K,1% 100K,1%,DNI 100K,1%,DNI

R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70

5

LEDAA LEDAC

6

LEDBA LEDBC

3

47k

R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95

10k

100K,1% 100K,1%,DNI 100K,1% 100K,1% 100K,1% 100K,1% 100K,1% 100K,1% 100K,1% 100K,1% 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1% 100K,1%

10k

4

LEDCA LEDCC

47k 1

6

LEDDA LEDDC

4

3

47k

1

10k

A

B

C

5

VDDS_DDR

DDR_DQS0 DDR_DQSN0

3 3

0.001uf,50V

4

R100 10K,1%

DGND

0.1uf,6.3V

C124

VDDS_DDR

DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15

DDR_VREF

DGND

10K,1%

C123

R98

DDR_DQM1 DDR_DQM0

DDR_DQS1 DDR_DQSN1

3 3

DDR_CLK DDR_CLKn DDR_CKE DDR_CSn DDR_RASn DDR_CASn DDR_WEn DDR_D[15..0]

3 3 3 3 3 3 3

3 3

3

DDR_RESETn

3

H1

M8

J1 J9 L1 L9

A1 A8 C1 C9 D2 E9 F1 H2 H9

D3 E7

F3 G3

C7 B7

E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3

J7 K7 K9 L2 J3 K3 L3

T2

ODT

4Gb DDR3

ZQ

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

MT41K256M16HA -125:E

VREF_DQ

VREF_CA

NC1 NC2 NC3 NC4

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ7 VDDQ8 VDDQ9 VDDQ10

UDM LDM

LDQS LDQSn

UDQS UDQSn

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

CK CKn CKE CSn RASn CASn WEn

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BA0 BA1 BA2

3

L8

B1 B9 D1 D8 E2 E8 F9 G1 G9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B2 G7 R9 K2 K8 N1 N9 R1 D9

K1

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M2 N8 M3

DDR3L SDRAM

RESET#

U12

ZQ

R99 240

DGND

VDDS_DDR

DDR_ODT

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 DDR_A15 DDR_BA0 DDR_BA1 DDR_BA2

DGND

2

B

C117

Document Number

1

Sheet

BeagleBone Black DDR3 Memory

DGND

C122

C121

C120

C119

1

C118

VDDS_DDR

C116

C115

C114

450-5500-001 Date: Tuesday, January 21, 2014

Size

Title

DGND

C113

C112

C111

VDDS_DDR

C110

3

C109

3

C108

3

DDR_BA[2..0]

DDR_A[15..0]

C107

DDR_ODT

DDR_BA[2..0]

DDR_A[15..0]

0.1uf,6.3V

10K,1%

0.1uf,6.3V

1.5K,1%

0.1uf,6.3V

R97

0.1uf,6.3V

DGND

0.1uf,6.3V

VDDS_DDR

2

0.1uf,6.3V

3

0.1uf,6.3V 10uF,10V

R96

0.1uf,6.3V 0.1uf,6.3V

4

0.1uf,6.3V

0.1uf,6.3V

D

5

0.1uf,6.3V

0.1uf,6.3V

0.1uf,6.3V

10uF,10V

7

of

11

Rev B

A

B

C

D

A

B

C

5

3,11 3,11 3,11 3,11 3,11 3,11 3,11 3,11 3,11 3,11 3

MMC1_DAT0 MMC1_DAT1 MMC1_DAT2 MMC1_DAT3 MMC1_DAT4 MMC1_DAT5 MMC1_DAT6 MMC1_DAT7 MMC1_CMD MMC1_CLK eMMC_RSTn

R101 R102 R103 R104 R105 R106 R107 R108 R109 R110 R111 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 10K,1%

NC123 NC122 NC121 NC120 NC119 NC118 NC117 NC116 NC115 NC114 NC113 NC112 NC111 NC110 NC109 NC108 NC107 NC106 NC105 NC104 NC103 NC102 NC101 NC100 NC99 NC98 NC97 NC96 NC95 NC94 NC93 NC92 NC91 NC90 NC89 NC88 NC87 NC86 NC85 NC84 NC83 NC82

DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 CMD CLK RST

4

MEM_MNAND_2GB

K6 N6 E5 N9 N8 N7 J12 P14 N3 P10 N1 M14 M13 M12 M11 M10 M9 M8 M7 P11 P12 P13 M3 M2 M1 L14 L13 L12 A10 A11 A12 A13 A14 B1 B7 G1 L3 L2 L1 K14 K13 K12

A3 A4 A5 B2 B3 B4 B5 B6 M5 M6 K5

U13

VDD_3V3B

J10 K9 F5 E6 P3 P5 N4 C6 M4 VCC0 VCC1 VCC2 VCC3 VCCQ1 VCCQ2 VCCQ3 VCCQ4 VCCQ5

VDD_3V3B

4

DGND

N2 P6 P4 C4 G5 E7 H10 K8 N5 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSS1 VSS2 VSS3 VSS4 VSS5

D

5

3

C2 VCCI

NC81 NC80 NC79 NC78 NC77 NC76 NC75 NC74 NC73 NC72 NC71 NC70 NC69 NC68 NC67 NC66 NC65 NC64 NC63 NC62 NC61 NC60 NC59 NC58 NC57 NC56 NC55 3

G2 K10 G3 G10 K7 N11 N10 B8 K3 K2 K1 J14 J13 N12 N13 N14 P1 P2 P7 P9 P8 J5 J3 J2 J1 H14 H13

NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36 NC37 NC38 NC39 NC40 NC41 NC42 NC43 NC44 NC45 NC46 NC47 NC48 NC49 NC50 NC51 NC52 NC53 NC54

C125

E1 E2 E3 A2 A6 A7 A8 E8 E9 E10 A1 E12 E13 E14 F1 F2 F3 A9 B14 C14 C13 C12 C11 F10 C10 F12 F13 F14 C9 C8 C7 C5 C3 C1 D14 D13 D12 D4 D3 G12 G13 G14 H1 H2 H3 D2 H5 D1 B13 B12 B11 B10 B9 H12

DGND

2.2uF,6.3V

eMMC_VCCI

2

0.1uf,6.3V

C130

Document Number B

450-5500-001 Date: Tuesday, January 21, 2014

Size

0.1uf,6.3V

C129

Beagle BoneBlack 2G eMMC

0.1uf,6.3V

C128

Title

0.1uf,6.3V

10uF,10V

DGND

C127

C126

VDD_3V3B

2

1

Sheet

1

8

of

11

Rev B

A

B

C

D

A

B

C

4 4 4 4 4 4 4 4

4

4 4 4 4 4 4 4

4

3,11

4

5

30pF,50V

C142

PHYX

R143 10,1%

DGND

SYS_RESETn

MII1_TXCLK MII1_TXEN MII1_TXD0 MII1_TXD1 MII1_TXD2 MII1_TXD3 MII1_COL MII1_CRS_DV

MDIO_DATA MDIO_CLK MII1_RXD3 MII1_RXD2 MII1_RXD1 MII1_RXD0 MII1_RXDV MII1_RXCLK MII1_RXERR

MII1_REFCLK

Y3

1

30pF,50V

C143

R142

R140

10,1%,DNI

DGND

PHY_XTAL1 1M,1%,DNI PHY_XTAL2

25.000MHz XTAL150SMD_125X196

2

R141

100,1% 100,1%

100,1%

R134

R138 R139

100,1% 100,1% 100,1% 100,1% 100,1% 100,1% 100,1%

R125 R126 R127 R128 R129 R131 R133

R124

DGND

C135 0.1uf,6.3V

VDD_3V3B

R119 0,1%

0,1%,DNI

MODE2 CRS

TXCLK

19

20 21 22 23 24 25 15 14

16 17 8 9 10 11 26 7 13

4

5 RCLKIN

RXD3/PHYAD2 RXD2/RMIISEL RXD1/MODE1 RXD0/MODE0 RXDV REFCLKO RXER/PHYAD0

1.5K,1%

1 150OHM800mA

4

XTAL2

XTAL1/CLKIN

nRST

DGND

RBIAS

nINT/TXER/TXD4

LED1/REGOFF LED2/nINTSEL

RXP RXN

32

18

15pF,DNI

15pF,DNI

RBIAS

DGND

3

R144 12.1K,1%

DGND

15pF,DNI

C139

DGND

15pF,DNI

C140

DGND

R145 10K,1%

ACTIVE WHEN LINK PRESENT. BLINKS OFF DURING ACTIVITY. ACTIVE WHEN AT 100MB

DGND

C138

C137

ETH_TXD4

RXP RXN

31 30

3 2

TXP TXN

29 28

DGND

1uF,10V

470pF,6.3V

DGND

C134

C133 10uF,10V

C136

DGND

C132 0.1uf,6.3V

DGND

TXP TXN

PHY_VDDCR

DGND

C131 0.1uf,6.3V

QFN32_5X5MM_EP3P3MM

U14 TXCLK TXEN LAN8710A TXD0 TXD1 TXD2 TXD3 COL/CRS_DV/MODE2 CRS

MDIO MDC RXD3/PHYAD2 RXD2/RMIISEL RXD1/MODE1 RXD0/MODE0 RXDV RXCLK/PHYAD1 RXER/RXD4/PHYAD0

2 FB4

VDD_PHYA

VDD_PHYA

RXER/PHYAD0

DGND

DGND

R135 10K,1%

2

R137 0,1%

LPJ0011BBNL

BeagleBone Black Ethernet Document Number B

NC GND

7

13 14

8

1

Sheet

YELC SHD1 YELA SHD2 GRNC GRNA

TCT TD+ TDRD+ RDRCT

450-5500-001 Date: Tuesday, January 21, 2014

Size

Title

DGND

VDD_PHYA

TCT_RCT

11 12 10 9

5 3 6 1 2 4

P5

RXD0/MODE0

RXD1/MODE1

MODE2

VDD_3V3B

1

1.5K,1% R113

9

ETHERNET CONNECTOR

YEL_C YELA GRN_C GRNA

0.022uF,10V

C141

470,5%

470,5%

R132

R130

DGND

R115 10K,1%

RXD3/PHYAD2

R116 10K,1%

RXD2/RMIISEL

2

DGND

of

DGND

.1,0805

11

Rev B

ESD_RING

R136

R114 1.5K,1%

REFCLKO

R120 49.9,1%

3

R121 49.9,1%

4

R122 49.9,1%

R117 10K,1%

R118 10K,1%

D

5

12 VDDIO

6 VDDCR

1 27 VDD2A VDD1A GND_EP 33

R123 49.9,1%

R112 1.5K,1%

A

B

C

D

A

B

3

4,6,10,11 LCD_DATA5 4,6,10,11 LCD_DATA6 4,6,10,11 LCD_DATA7 4,6,10,11 LCD_DATA8 4,6,10,11 LCD_DATA9 4,6,10,11 LCD_DATA10

4,6,10,11 LCD_DATA11 4,6,10,11 LCD_DATA12 4,6,10,11 LCD_DATA13 4,6,10,11 LCD_DATA14 4,6,10,11 LCD_DATA15

5

10K,1%

McASP0_AXR2 (Pin C12 Mode 2) McASP0_FSX (Pin B13 Mode 0)

McASP0_ACLKX (Pin A13 Mode 0)

R158

4,6,10,11 LCD_DATA0 4,6,10,11 LCD_DATA1 4,6,10,11 LCD_DATA2 4,6,10,11 LCD_DATA3 4,6,10,11 LCD_DATA4

12MHZ

SPI1_CS0 SPI1_D0

4,11 4,11

3

SPI1_SCLK

VDD_3V3B HDMI_INT

I2C0_SDA I2C0_SCL

4,11

2,4,11 2,4,11

DGND

27

23 28 26 25 24

51 52 53 54 50

OSC_IN

ACLK AP3 AP2 AP1 AP0

CSDA CSCL A0_I2C A1_I2C INT

VDDA0(1.8V)

TDA19988

VDDIOA(1.8V) VDDIOB(1.8V) TEST VPP PAD

VDDDC0(1.8V) VDDDC1(1.8V)

VDDA1(TX)(1.8V) VDDA2(TX)(1.8V) VDDA3(TX)(1.8V)

0,1%

R149

14 55 49 19 65

5 29

36 41 46

35

47 48

DGND 4

C156

47pf,6.3V

C

38 37

34

C157

47pf,6.3V

4,6,10,11 LCD_DATA0 4,6,10,11 LCD_DATA1 4,6,10,11 LCD_DATA2 4,6,10,11 LCD_DATA3 4,6,10,11 LCD_DATA4 4,11 LCD_VSYNC 4,11 LCD_HSYNC 4,11 LCD_DE 4,11 LCD_PCLK

C160

47pf,6.3V

BLUE

39 40

31 30

C161

47pf,6.3V

4,6,10,11 LCD_DATA5 4,6,10,11 LCD_DATA6 4,6,10,11 LCD_DATA7 4,6,10,11 LCD_DATA8 4,6,10,11 LCD_DATA9 4,6,10,11 LCD_DATA10

C162

47pf,6.3V

GREEN

42 43

33 32

C163

47pf,6.3V

4,6,10,11 LCD_DATA11 4,6,10,11 LCD_DATA12 4,6,10,11 LCD_DATA13 4,6,10,11 LCD_DATA14 4,6,10,11 LCD_DATA15

C164

47pf,6.3V

RED

C165 47pf,6.3V

D

C166 47pf,6.3V

DGND

HDMI_SWING

HDMI_HPD HDMI_CEC

HDMI_DSCL HDMI_DSDA

DVI_+5V

R148

10K,1% DGND HDMI_TXC+ HDMI_TXC-

3

R166

VDD_1V8

VDD_3V3B 27K,1%

FB5 1 2 150OHM800mA

HDMI_1V8

HDMI_CEC_D

HDMI_TX0HDMI_TX0+

RB751V40,115

D8

HDMI_TX1HDMI_TX1+

HDMI_TX2HDMI_TX2+

3

C144 2.2uF,6.3V

44 45

C167 47pf,6.3V

C145 0.1uf,6.3V

U11

C168 47pf,6.3V

C146 2.2uF,6.3V

VPA0 R0 TX2VPA1 TX2+ VPA2 VPA3 DSCL VPA4 DSDA VPA5 VPA6 VPA7 R7 VPB0 G0 TX1VPB1 TX1+ VPB2 VPB3 HPD VPB4 CEC VPB5 VPB6 G7 VPB7 VPC0 B0 TX0VPC1 TX0+ VPC2 VPC3 VPC4 EXT_SWING VPC5 VPC6 B7 TXC+ VPC7 TXCVSYNC/VREF HSYNC/VREF DE/VREF PCLK VDDA(PLL0)(1.8V) VDDA(PLL1)(1.8V)

C169 47pf,6.3V

C147 0.1uf,6.3V

63 62 61 60 59 58 57 56 9 8 7 6 3 2 1 64 18 17 16 15 13 12 11 10 21 22 20 4

C170 47pf,6.3V

C148 2.2uF,6.3V

4

C172 47pf,6.3V

C149 0.1uf,6.3V

RED

C171 47pf,6.3V

R146

C150 0.1uf,6.3V

GRN

BLUE

C173 47pf,6.3V

R147 1.5K1%

1.5K,1%

C151 2.2uF,6.3V

5

D6 1 IP4283CZ10-TT

2

8

DGND

3

4

2

2

1

2

8

DGND

3

4

5

D7

HDMI_CEC

HDMI_HPD

HDMI_DSCL HDMI_DSDA

DVI_+5V PTC_RXEF010

Document Number B

1

DGND

15 13 12 14

19 16 1 11 9 10

8 6 7

5 3 4 17 18

1

Sheet

BeagleBone Black HDMI Interface

IP4283CZ10-TT

450-5500-001 Date: Tuesday, January 21, 2014

Size

Title

5

RT1

SYS_5V

t

P6

NC

2

23

22

21

20

10 of 11

10118241-001RLF

CEC CLK_S CLK+ CLK-

+5V MTG4 DDC/CEC GND HPLG DAT0DAT0+ DAT0_S

MTG2 DAT1DAT1+ DAT1_S MTG3

DAT2DAT2+ DAT2_S SCL SDA MTG1

Rev B

A

B

C

D

A

B

5

3 3

3 3

3,4

3

3

DGND

MMC0_CD

MMC0_DAT0 MMC0_DAT1

MMC0_CLKO

MMC0_DAT2 MMC0_DAT3 MMC0_CMD

R150 10K,1%

4

R151 10K,1%

VDD_3V3B

DGND

P10

SCHA5B0200

DAT2 GND CD/DAT3 CD CMD GND3 VDD GND4 CLOCK GND5 VSS GND6 DAT0 GND7 microSD DAT1 GND8

9 10 11 12 13 14 15 16

3,8 3,8 3,8

3,8 3,8

DGND

uSD CONNECTOR

1 2 3 4 5 6 7 8

0.1uf,6.3V

10uF,10V

DGND

C154

MMC1_DAT7 MMC1_DAT3 3 TIMER7 3 TIMER6 3 GPIO1_12 3 GPIO0_26 3 GPIO1_14 3 GPIO2_1 MMC1_CMD MMC1_DAT5 MMC1_DAT1 GPIO1_29 3 4,10 LCD_PCLK 4,10 LCD_DE 4,6,10 LCD_DATA15 4,6,10 LCD_DATA11 4,6,10 LCD_DATA10 4,6,10 LCD_DATA9 4,6,10 LCD_DATA7 4,6,10 LCD_DATA5 4,6,10 LCD_DATA3 4,6,10 LCD_DATA1

C153

EXPANSION HEADER

DGND

FEMALE HEADER 2x23

R152 10K,1%

C

3,8 3,8 3,8

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46

R153 10K,1%

D

MMC1_DAT6 MMC1_DAT2 3 TIMER4 3 TIMER5 3 GPIO1_13 3 EHRPWM2B 3 GPIO1_15 3 GPIO0_27 3 EHRPWM2A MMC1_CLK MMC1_DAT4 MMC1_DAT0 4,10 LCD_VSYNC 4,10 LCD_HSYNC 4,6,10 LCD_DATA14 4,6,10 LCD_DATA13 4,6,10 LCD_DATA12 4,6,10 LCD_DATA8 4,6,10 LCD_DATA6 4,6,10 LCD_DATA4 4,6,10 LCD_DATA2 4,6,10 LCD_DATA0

P8

R154 10K,1%

3,8 3,8

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45

4

R155 10K,1%

CAUTION: USED ON BOARD

5

CAUTION: USED ON BOARD 3

3

2 3 3 3 4 4 4 3 3,4 4 4,10 4,10 4 4 4 4 3

R157

P9

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46

FEMALE HEADER 2x23

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45

10K,1%

VDD_3V3B

2,4,10 2,4,10

2

I2C0_SCL I2C0_SDA

1 3

256KX8

24LC32A

WP

VSS

VCC

5

2

4

WP R156

4 4 4 4

10K,1%

3,9 3 3 3 4 4 4 4 4 4,10 4

TP4 TESTPT1

Board ID SCL SDA

U7

AIN5 AIN3 AIN1 GPIO0_7

SYS_RESETn GPIO1_28 EHRPWM1A EHRPWM1B I2C1_SDA I2C2_SDA UART2_RXD UART1_TXD UART1_RXD SPI1_CS0 SPI1_D1 VDD_ADC

DGND

0.1uf,6.3V

C152

VDD_3V3A

1

B

Document Number

450-5500-001 Date: Tuesday, January 21, 2014

Size

1

Sheet

11 of 11

Rev B

BeagleBone Black Expansion Headers, uSD.and EEPROM

Title

DGND

GNDA_ADC

DGND VDD_3V3B VDD_5V SYS_5V

EXPANSION HEADER

DGND

DGND VDD_3V3B VDD_5V SYS_5V PWR_BUT UART4_RXD UART4_TXD GPIO1_16 I2C1_SCL I2C2_SCL UART2_TXD GPIO1_17 GPIO3_21 GPIO3_19 SPI1_D0 SPI1_SCLK AIN4 AIN6 AIN2 AIN0 CLKOUT2

2

A

B

C

D