USO0RE41244E
(19) United States (12) Reissued Patent
(10) Patent Number: US (45) Date of Reissued Patent:
Tanaka et a]. (54)
MULTI-STATE EEPROM HAVING WRITE
5,168,465 A 5,172,338 A 5,218,569 A
VERIFY CONTROL CIRCUIT
RE41,244 E Apr. 20, 2010
12/1992 Harari 12/1992 Mehrotra et al. 6/1993 Banks
(75) Inventors: Tomoharu Tanaka, Yokohama (JP); Gertj an Hemink, Kawasaki (JP)
(Continued) FOREIGN PATENT DOCUMENTS
(73) Assignee: Kabushiki Kaisha Toshiba, KaWasaki-shi (JP)
DE
4232025
DE
42 32 025
OTHER PUBLICATIONS
Jun. 13, 2006 F.
Related US. Patent Documents
Masuoka,
KabushikiiKaisha
Science Forum. pp.
1864190, “Flash Memory Technology Handbook” Aug. 15,
Reissue of:
(64) Patent No.:
4/1993
4/1993
(Continued)
(21) App1.No.: 11/451,585 (22) Filed:
*
1 993.
5,570,315
Issued:
Oct. 29, 1996
Appl. No.: Filed:
08/308,534 Sep. 21, 1994
Primary ExamineriAndrew Q Tran (74) Attorney, Agent, or FirmAObIon, Spivak, McClelland, Maier & Neustadt, L.L.P.
US. Applications:
(57)
(62)
An EEPROM having a memory cell array in Which electri cally programmable memory cells are arranged in a matrix and each of the memory cells has three storage states,
Division of application No. 09/134,897, ?led on Aug. 17, 1998.
(30)
Foreign Application Priority Data
Sep. 21, 1993
(JP) ........................................... .. 5-234767
Dec. 13, 1993
(JP) ........................................... .. 5-311732
(51)
Int. Cl. G11C 16/04
(2006.01)
(52)
US. Cl. ........................... .. 365/185.22; 365/185.21;
(58)
Field of Classi?cation Search ........... .. 365/185.03,
365/185.18; 365/185.03; 365/185.12; 365/185.17
365/185.17, 185.22, 185.23,185.12, 185.18, 365/18521
ABSTRACT
includes a plurality of data circuits for temporarily storing data for controlling Write operation states of the plurality of memory cells, a Write circuit for performing a Write opera tion in accordance With the contents of the data circuits
respectively corresponding to the memory cells, a Write verify circuit for con?rming states of the memory cells set upon the Write operation, and a data updating circuit for updating the contents of the data circuits such that a reWrite operation is performed to only a memory cell, in Which data is not suf?ciently Written, on the basis of the contents of the data circuits and the states of the memory cells set upon the
See application ?le for complete search history.
Write operation. A Write operation, a Write verify operation,
References Cited
and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined Written states.
(56)
U.S. PATENT DOCUMENTS 4,279,024 A
1 Claim, 29 Drawing Sheets
7/1981 Schrenk
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US RE41,244 E Page 2
US. PATENT DOCUMENTS 5,321,655 A
*
5,321,699 A 5,394,362 A 5,521,865 A 5,650,966 A
5,652,719 5,781,478 5,920,507 6,069,823 6,147,911
*
A A A A A
JP
1-46949
JP
2-232900
9/1990
6/1994 Iwahashi et a1. ..... .. 365/18521
JP
2_260298
10/1990
6/1994 Endoh et 31. 2/1995 Banks 5/1996 Ohuchi et 31.
JP JP JP
3_59886 3_237692 3_286497
3/1991 10/1991 12/1991
7/1997 Cleveland et a1. ...... .. 365/1853
7/1997 7/1998 7/1999 5/2000 11/2000
2007/0183244 A1 *
8/2007
10/1989
JP
4_88671
3/1992
Tanaka et a1. Takeuchi et 31. Takeuchi et 211. Takeuchi et 31. Takeuchi et 211.
JP JP JP JP JP
4_119594 4_254994 4_507320 5_6681 5_144277
4/1992 9/1992 12/1992 1/1993 6/1993
Lee ....................... .. 365/2257
JP
5482476
7/1993
JP
5-60199
9/1993
JP
2007484102
70007
JP
2007-184103
7/2007
FOREIGN PATENT DOCUMENTS JP JP
58_86777 62-257699
5/1983 11/1987
JP
1-23878
5/1989
* cited by examiner
US. Patent
Apr. 20, 2010
Sheet 1 0f 29
WRITE CONTROL SIGNAL
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US RE41,244 E
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US RE41,244 E
START OF DATA WRITE OPERATION I
LOAD DATA
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