USO0RE41969E
(19) United States (12) Reissued Patent
(10) Patent Number:
Tanaka et a]. (54)
(75)
(45) Date of Reissued Patent:
MULTI-STATE EEPROM HAVING
5,218,569 A
6/1993 Banks
5,321,699 A 5,394,362 A
6/1994 EIIdOh et 31 2/1995 Banks
Inventors: Tomoharu . Tanaka, . Yokohama - (JP);
,
Assignee: Kabushiki Kaisha Toshiba,
,
i
ghugklili an eett a.
5,781,478 A
7/1998 Takeuchietal.
5’920’507 A
7/1999 Takeuchlet al'
KaWasaki-shi (JP)
(Continued)
(21) APPI' NO‘: 11/451,592 (22)
Filed:
FOREIGN PATENT DOCUMENTS
Jun. 13, 2006
DE
42 32 025
4/1993
(Continued)
Related US. Patent Documents
Reissue of,
(64)
Nov. 30, 2010
WRITE-VERIFY CONTROL CIRCUIT
Germ“ Hemlnk’KaWaSak1(JP) (73)
US RE41,969 E
OTHER PUBLICATIONS
Patent NO‘:
5’570’3 15
F. Masuoka, KabushikiiKaisha Science Forum, pp.
Issued: Appl. No.: Filed:
Oct‘ 29’ 1996 08/308,534 Sep. 21, 1994
1864190, “Flash Memory Technology Handbook” Aug. 15, 1993_
US. Applications:
Primary ExamineriAndrew Q Tran (74) Attorney, Agent, or Fl'I’m4OblOI1, Spivak, McClelland,
(62)
Maier & Neustadt, L.L.P.
Division of application No. 09/134,897, ?led on Aug. 17, 1998.
(30)
(57)
Foreign Application Priority Data
Sep. 21, 1993
(JP)
........................................... .. 5-234767
Dec. 13, 1993
(JP)
........................................... .. 5311732
(51)
(52)
(2006.01) (2006.01)
memory cells, a Write circuit for performing a Write opera tion in accordance With the contents of the data circuits
See application ?le for complete search history.
respectively corresponding to the memory cells, a Write verify circuit for con?rming states of the memory cells set upon the Write operation, and a data updating circuit for updating the contents of the data circuits such that a reWrite operation is performed to only a memory cell, in Which data is not suf?ciently Written, on the basis of the contents of the
References Cited
Write operation. A Write operation, a Write verify operation,
U.S. PATENT DOCUMENTS
and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined Written states.
US. Cl. ........................... .. 365/185.22; 365/185.03;
365/185.12; 365/185.17; 365/185.21; 365/185.18 (58)
An EEPROM having a memory cell array in Which electri cally programmable memory cells are arranged in a matrix and each of the memory cells has three storage states,
includes a plurality of data circuits for temporarily storing data for controlling Write operation states of the plurality of
Int. Cl. G11C 16/34 G11C 16/24
ABSTRACT
Field of Classi?cation Search ........... .. 365/185.03,
365/185.17, 185.22, 185.28,185.12, 185.18, 365/18521
data circuits and the states of the memory cells set upon the
(56)
4,279,024 A 5,168,465 A 5,172,338 A
7/1981 Schrenk 12/1992 Harari 12/1992 Mehrotra et a1.
2 Claims, 29 Drawing Sheets W E caunwL Slum. GENERATION cmwl‘l ‘'
EVERI
CONTRG. SIGNAL
-
US RE41,969 E Page 2
US. PATENT DOCUMENTS 6,038,180 A
*
6,069,823 A 6,147,911 A 7,394,695 B2 *
3/2000
HOShi ....................... .. 365/201
5/2000 Takeuchi et 31. 11/2000 Takeuchi et 31. 7/2008 Takeuchi et a1. ..... .. 365/185.17
FOREIGN PATENT DOCUMENTS JP JP JP JP JP
58-86777 62-257699 143878 1'46949 2-232900
5/1983 11/1987 5/1989 10/1989 9/1990
JP
2-260298
10/1990
JP
3-59886
3/1991
JP
3-237692
10/1991
JP
3_286497
12/1991
JP JP
4_gg671 4419594
3/1992 4/1992
JP
4_254994
9/1992
JP JP JP JP JP JP JP
4-507320 5-6681 5-144277 5482476 560199 2007-184102 2007-184103
12/1992 1/ 1993 6/1993 M993 9/l993 7/2007 7/2007
* cited by examiner
US. Patent
Nov. 30, 2010
Sheet 1 0f 29
WRITE CONTROL SIGNAL
US RE41,969 E
A
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Nov. 30, 2010
Sheet 2 0f 29
US RE41,969 E
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US. Patent
Nov. 30, 2010
Sheet 7 0f 29
US RE41,969 E
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Nov. 30, 2010
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Nov. 30, 2010
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Sheet 15 0f 29
US RE41,969 E
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Nov. 30, 2010
US RE41,969 E
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