USO0RE41456E

(19) United States (12) Reissued Patent

(10) Patent Number: US RE41,456 E (45) Date of Reissued Patent: Jul. 27, 2010

Tanaka et a1. (54)

6,069,823 A 6,147,911 A

2/1995 5/1996 7/1997 7/ 1998 7/ 1999 5/2000 11/2000

7,366,033 B2 * 2005/0038953 A1 *

4/2008 2/2005

MULTI-STATE EEPROM HAVING WRITE

5,394,362 5,521,865 5,652,719 5,781,478 5,920,507

VERIFY CONTROL CIRCUIT

(75) Inventors: Tomoharu Tanaka, Yokohama (JP); Gertj an Hemink, Kawasaki (JP) (73) Assignee: Kabushiki Kaisha Toshiba, KaWasaki-shi (JP)

(21) App1.No.: 11/451,593 (22) Filed:

Jun. 13, 2006

A A A A A

Banks Ohuchi et a1. Tanaka et a1. Takeuchi et a1. Takeuchi et a1. Takeuchi et a1. Takeuchi et a1. Park et a1. ............ .. 365/189.05 Chang ......................... .. 711/5

FOREIGN PATENT DOCUMENTS

Related US. Patent Documents

DE

4/1993

42 32 025

Reissue of:

(64) Patent No.:

Oct. 29, 1996

Appl. No.: Filed: US. Applications: (62)

(Continued)

5,570,315

Issued:

OTHER PUBLICATIONS

08/308,534 Sep. 21, 1994

F. Masuoka, KabushikiiKaisha Science Forum, pp.

186*190, “Flash Memory Technology Handbook” Aug. 15,

Division of application No. 09/134,897, ?led on Aug. 17,

Primary ExamineriAndrew Q Tran (74) Attorney, Agent, or FirmAObIon, Spivak, McClelland,

1998, now abandoned.

(30)

Foreign Application Priority Data

Maier & Neustadt, L.L.P.

Sep. 21, 1993

(JP)

Dec. 13, 1993

(JP) ........................................... .. 5-311732

(51)

(52)

5-234767

(57)

ABSTRACT

(2006.01)

An EEPROM having a memory cell array in Which electri cally programmable memory cells are arranged in a matrix and each of the memory cells has three storage states,

US. Cl. ........................... .. 365/185.22; 365/185.16;

includes a plurality of data circuits for temporarily storing data for controlling Write operation states of the plurality of

Int. Cl. G11C 16/34

365/185.17; 365/185.23; 365/185.03; 365/185.12; 365/185.21 (58)

1 993.

Field of Classi?cation Search ........... .. 365/185.24,

memory cells, a Write circuit for performing a Write opera tion in accordance With the contents of the data circuits

References Cited

respectively corresponding to the memory cells, a Write verify circuit for con?rming states of the memory cells set upon the Write operation, and a data updating circuit for updating the contents of the data circuits such that a reWrite operation is performed to only a memory cell, in Which data is not suf?ciently Written, on the basis of the contents of the

U.S. PATENT DOCUMENTS

Write operation. A Write operation, a Write verify operation,

365/185.03, 185.22, 185.23,185.17, 185.18, 365/185.12, 185.21 See application ?le for complete search history. (56)

data circuits and the states of the memory cells set upon the 4,279,024 5,168,465 5,172,338 5,218,569 5,321,699

A A A A A

7/1981 12/1992 12/1992 6/1993 6/1994

and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined Written states.

Schrenk Harari Mehrotra et a1. Banks Endoh et al.

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5 Claims, 29 Drawing Sheets

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US RE41,456 E Page 2

FOREIGN PATENT DOCUMENTS

JP

4-88671

3/1992

4-119594 4-254994 4-507320 5-6681 5-144277 5-182476 5-60199 2007-184102 2007-184103

4/1992 9/1992 12/1992 1/1993 6/1993 7/1993 9/1993 7/2007 7/2007

JP JP JP JP JP JP JP JP

58-86777 62-257699 1-23878 1-46949 2-232900 2-260298 359886 3437692

5/1983 11/1987 5/1989 10/1989 9/1990 10/1990 3/1991 10/1991

JP JP JP JP JP JP JP JP JP

JP

3-286497

12/1991

* cited by examiner

US. Patent

Jul. 27, 2010

Sheet 1 0f 29

US RE41,456 E

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Jul. 27, 2010

Sheet 7 0f 29

US RE41,456 E

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Sheet 9 0f 29

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US. Patent

Jul. 27, 2010

Sheet 15 0f 29

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US. Patent

Jul. 27, 2010

Sheet 16 0f 29

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US. Patent

Jul. 27, 2010

Sheet 18 0f 29

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