2010 28th IEEE VLSI Test Symposium

Modeling Yield, Cost, and Quality of an NoC with Uniformly and Non-Uniformly Distributed Redundancy Saeed Shamshiri and Kwang-Ting Cheng Electrical and Computer Engineering Department University of California, Santa Barbara, CA 93106 {saeedshamshiri, timcheng}@ece.ucsb.edu communication infrastructure: a core is either connected to or disconnected from the other cores. However, quality analysis of the connection (e.g. the average number of links that data have to travel from the source core to the destination core) gives us an in-depth understanding of the communication system. We have also analyzed how much each link of a mesh contributes to the overall reliability of the NoC. Our analysis reveals that the links in the center of the network have more significant impacts on the overall reliability of the mesh than the links closer to the edges. Based on the results of this analysis, we propose a sparing strategy that has a nonuniform distribution of spare wires throughout the mesh. We compare the reliability and the cost of this new approach with those based on a uniformly distributed spare scheme. We show that a non-uniform distribution is in general more effective. The unique contributions of the paper include: (1) defining and validating a quality metric for on-chip networks, (2) modeling the yield and cost of a multi-core chip subject to a given quality constraint, and (3) proposing a non-uniform spare-wire distribution according to the usage probability of the mesh links. The rest of the paper is organized as follows: In Section II, we define a quality metric and explain our simulation flow to measure the quality of the NoC. This is followed by the experimental results of our method for determining the yield and the cost of a spare-enhanced multi-core chip under a quality constraint. We propose a non-uniform distribution for spare wires in Section III and show that this option is in general better than the spare scheme following a uniform distribution. The paper concludes in Section IV.

Abstract—In this paper, we propose a quality metric for an NoC and model the yield and cost of a spare-enhanced multicore chip subject to a given quality constraint. Our experiments show that the overall quality of a mesh-based NoC depends more on the reliability of the inner links than the outer links; therefore, a non-uniform distribution of spare wires could be more effective and cost efficient than a uniform approach. Keywords-SoC; NoC; yield and cost modeling; quality analysis; non-uniform spare distributtion;

I. INTRODUCTION Multi-core processors and systems-on-a-chip (SoC) are quickly becoming the dominant architectures, driven by shrinking processes and diminishing returns from additional per-core complexity [1-4]. While the individual core complexity is tapering off, larger die sizes, increasing device counts, and higher defect rates are leading to lower yields [5,6]. A common approach to solving this yield problem has been the addition of redundancy [7]. This approach has become ubiquitous in memories, whose highly repetitive structures and high densities both enable and demand a high degree of defect tolerance [8, 9]. It has also been proposed for use in logic devices that have similarly repetitive structures, such as programmable logic arrays (PLAs) [7], field programmable gate arrays (FPGAs) [10], and systolic array processors [11]. More recently, it has been used in single-chip multiprocessors [12, 13]. In [13], a yield and cost analysis framework has been proposed for a multi-core processor that uses spare cores to recover from both manufacturing and in-field failures. This paper modeled the yield as well as the manufacturing and service costs with and without the burn-in process. Later, an analysis, as well as models, of defects on the mesh (i.e., wires and routers) was proposed in [14]. The analysis in [14] assumes that a multi-core chip with spares is shippable if a sufficient number of cores are fault-free, and each pair of fault-free cores is connected regardless of the quality of the connections. Not considering the connection quality limits the practical application of the analysis. In this paper, we first define a metric for the network quality. Based on the proposed metric, we then measure the quality of the mesh and investigate the yield and cost improvement of a spare-enhanced mesh when there is a quality constraint. Connectivity analysis offers just a blackand-white (i.e. pass/no pass) perspective of the

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II. QUALITY OF THE NETWORK The first step toward measuring the quality of a network is to define quality. A. Quality Definition For a group of cores connected in an NoC, we define the quality of their connections as the Average Minimum Distance (AMD) of every distinct pair of nodes. In an i-by-j mesh, there are totally 2x(ix(j-1)+jx(i-1)) links. For example, for a 3-by-3 mesh, as shown in Fig. 1.a, there are 24 links. In a fault-free mesh, all of these links are available; we call such a mesh a complete mesh. In a complete mesh, the minimum distance, in units of links, from node a to b, whose coordinates are (xa,xb) and (ya,yb) respectively, is |xa-xb|+|ya-yb|, which is also known as the

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Manhattan distance, between these two nodes. When some of the links are faulty, we consider them as if they don’t exist, and therefore, the mesh is not a complete mesh anymore, as shown in Fig. 1.b. For a non-complete mesh, the minimum distance can be computed using the Dijkstra algorithm [15]. For a non-weighted graph which is the case for our application here, the minimum distance can be obtained simply by using a Breadth First Search (BFS) algorithm that has a lower complexity than that of the Dijkstra algorithm. For a graph with V nodes and E edges, the time complexity of the Dijkstra and the BFS algorithms are O(E+VlogV) and O(E+V) respectively [15]. For the case of a 2-D mesh with n nodes where O(E)=O(V)=O(n), the time complexity would be O(nlogn) for the Dijkstra, and O(n) for the BFS. For a complete i-by-j mesh, the Average Minimum Distance (AMD) from every node a to every other node b, where a ≠ b , is (i+j)/3. For example, the AMD of a complete 3-by-4 mesh is 2.33. This claim can be easily proven by induction over i and j. We can also prove that, for a complete i-by-i mesh with n nodes (i.e., n=i2), the AMD is of O(i) = O ( n ) order. Similarly, the average latency of stochastic communication [16] in a mesh is O ( n ) . Based on this defined quality metric, we can now measure the quality of the connections in a multi-core chip.

Figure 2. A spare-enhanced system-on-a-chip.

B. Quality Measurement Fig. 2 shows how we divide a multi-core SoC into smaller components for analysis. There are several parameters associated with each component which include the raw yield, the defect density [17], the defect coverage of manufacturing test, the shape and scale parameters of the infield failure-rate curve [18], and the defect coverage of infield test for those faults that happen in the field. Fig. 3 shows the complete flow of the analysis and simulation described in this work. Using a bottom-up approach, we first analyze the yield of a block and a link based on the input parameters for the subcomponents. Also, using the model of the life cycle of a chip [18], we calculate the in-field failure rates for each component. Then, we use these analytical data along with other input values for Monte Carlo simulation. The outputs of the simulator are used by another set of equations in order to compute the manufacturing and service costs of the system. In this flow, we reused some of the formulas and equations developed in [13], [14], and [19] wherever they applied.

Fig. 4 shows the steps of our Monte Carlo simulation for NoC quality estimation. The simulator, injecting faults to components and wires accordingly to the analytical data derived for each subcomponent and link, counts the maximum number of connected fault-free cores, cnt, and checks if it meets the minimum requirement, m (i.e., Steps 15). After that, we measure the quality of the connections. Instead of measuring the connection quality among cnt connected cores, we need to measure the connection quality among those m cores out of cnt cores that have the strongest connections. Here, m is the required number of working processors for shipment. Steps 6 and 7 of the simulation find the most strongly connected m cores and report their associated AMD. To make a meaningful comparison of the AMDs for meshes of different sizes, we need to normalize this value. We define the normalized AMD as: Normalized AMD =

Ideal AMD (m) Measured AMD (m)

where Ideal-AMD(m) is the minimum of achievable AMDs for any arrangement of m cores, and MeasuredAMD(m) is the measured value of a specific instance through the simulation, which is always equal to or greater than the Ideal-AMD. Therefore, the Normalized AMD would be in the range of 0 and 1. The higher the Normalized AMD, the better the instance’s connection quality. For a given m, there is just one ideal AMD; however, there might be several arrangements of nodes to achieve that ideal AMD. Table I shows the ideal AMD values associated with a given m ≤ 20 . Fig. 5 shows some examples of core arrangements that may or may not achieve the ideal AMD. It

Figure 1. Minimum route and minimum distance between two nodes in a complete and a non-complete 2-D mesh.

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is interesting to observe that the best arrangement for 16 cores is not a 4-by-4 square; nor is 3-by-4 the best arrangement for 12 cores. Having defined the normalized AMD, we can now provide a more accurate definition for quality: For an m-outof-n chip (i.e., an n-core chip that can be shipped only if it has m fault-free connected cores after manufacturing testing), the quality is zero if the number of connected, fault-free cores is less than m (i.e., cnt
Monte Carlo Simulation 1. 2. 3. 4. 5. 6. 7.

Observed yield of a core [14], [17]:

yc′ = (1 + Defect Density Area Clustering Factor Defect Coverage of Manufac. Testing

λc × Ac × Ωc −α ) α

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Observed yield of the bus:

′ = ( y′w _ ctrl ) kctrl ( y′w _ parity ) k parity ybus Scale parameter Shape parameter Warranty time Infant mortality time Defect coverage of in-field testing

Figure 4. Monte Carlo simulation for quality analysis.

Bus

nw

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Start with n fault-free blocks connected in a 2-D mesh. With 1- y’block probability, inject fault in each block. With f’conn probability disconnect all links in a faulty block. Disconnect every link of the mesh with 1- y’link probability. Traverse the mesh and count the maximum number of fault-free blocks connected. Save this number as cnt. If cnt is greater than or equal to m, it is a connected mesh. If cnt is greater than m, find a group of m nodes out of these cnt nodes such that they have the strongest connections among all combinations of m out of cnt. In the selected group of m nodes, for every pair of nodes, measure the minimum distance using BFS and then calculate the Average Minimum Distance (AMD) for the whole group. Normalize AMD using the ideal AMD achievable for m nodes. If the normalized AMD is greater than a minimum requirement, q, the chip passes the manufacturing test; otherwise it is a failed chip, and simulation is complete. For a shipped chip, within the warranty time, inject a fault on every component and every wire based on the calculated probability of failure. Check to determine whether at least m fault-free connected cores exist in the field; if so, for the best m fault-free connected cores, calculate the normalized AMD (similar to steps 5-8). Otherwise, the chip has failed and the service cost applies. If the normalized in-field AMD becomes less than the in-field minimum quality requirement, q-in-field, the chip fails. (This constraint can be removed by setting q-in-field =0.) Repeat steps 1-12 for many times and return the average values for the quality of the mesh, manufacturing yield, and in-field system failure probability under the quality constraint.

Grace Period

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Figure 5. Some examples of the core arrangements that may or may not result in an ideal AMD.

Figure 3. Analysis and modeling flow.

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TABLE II INPUT VALUES USED IN THE EXPERIMENTS OF THIS SECTION

TABLE I IDEAL AMD VALUES ASSOCIATED WITH 1 ≤ m ≤ 20

Fig. 6 shows the quality improvement of a 9-out-of-n chip by using spare cores and spare wires. Depending on the location in the trend curve, the benefit of extra cores or extra wires for quality improvement can be quantitatively estimated and compared. For example, in this experiment, for a 9-out-of-9 system with one spare-wire per link (point A in Fig. 6), adding three more spare cores will improve the quality more than adding one more spare wire to every link. However, in a 9-out-of-12 system with one spare wire (point B in Fig. 6), the effect on quality of adding one more spare wire per link is more significant than adding four more spare cores. Table II shows the values of the input parameters we used for this experiment and all experiments of the next subsection.

1

Quality

2

3

Yield

4

III. NON-UNIFORM SPARE DISTRIBUTION Thus far, we have considered the effect of uniformly distributed spare wires on the reliability and quality of the mesh. This uniformly distributed spare scheme assumes that all links of the mesh are equally important to the system reliability. In the following, we intend to measure the contribution of each link to the overall reliability. This is

No. of Spare Wires per Link 1

3

D. Total Cost Under a Quality Constraint We model the cost of a chip as the sum of its manufacturing and service costs. Manufacturing cost is the average cost of manufacturing each shipped chip, so any improvement in the yield improves the manufacturing cost as well. Service cost is the product of the average cost incurred for a chip failed in the field and the probability of a chip failure within the warranty period (see the bottom part of Fig. 3). The manufacturing cost and the total cost of a chip increase as the quality constraint is set tighter which may require integration of more spare wires into the system. For a 9-out-of-12 chip, the trend of total cost versus the required quality is shown in Fig. 8. Table III shows the input values used in this experiment and the rest of the paper. In all experiments, cost is normalized based on the manufacturing cost of a chip without any spare or test mechanism, with a perfect yield.

A

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Notice that the quality of the connections also translates into the chip performance. A higher quality chip has less communication overhead among cores (in terms of time) and, so, it operates faster. In fact, quality is a mixture of the yield and performance metrics.

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Figure 7. Observed yield vs. number of spare wires for different quality requirements in a 9-out-of-12 system.

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C. Observed Yield Under a Quality Constraint Now that we can measure the quality, we can place a constraint on quality and require each chip to meet this quality requirement to qualify for shipment. So, a chip passes the test (and thus can be shipped) if the number of connected fault-free processors is no less than m (i.e., cnt ≥ m ) and the quality is no less than a given value q (i.e., quality ≥ q ). This results in the observed yield of the system, which is computed in Step 9 of the simulation (See Fig. 4). Fig. 7 shows the trends of the observed yield with respect to the number of spare wires and the minimum quality requirement. When the minimum quality requirement, q, increases, the yield becomes lower and more spare wires are required to achieve a high yield. This change becomes significant when we have a more strict constraint such as q=0.9; this constraint means that the measured AMD of the best fault-free connected cores should not be more than 10% greater than the ideal AMD. 0.9

q=0

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Figure 6. Chip quality improves significantly by integrating more spare cores and spare wires.

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equivalent to the probability that a link is being used in a random packet transmission, which depends on the routing algorithm. In the XY-routing (i.e., the routing is first made in the direction of x and, then, in the y direction), there is only one route from a source to a destination (e.g., Fig. 9.a), but for a min-route routing (routing through any route that has the minimum length), there are usually many routes from a source to a destination.

Fig. 9 shows an example of a route from a source to a destination which is three hops away in each direction. In this case, for a min-route, there are (3+3)!/(3!3!)=20 routes from the source to the destination. Fig. 9.b displays the number of routes that passes through each link. If we divide these numbers by the total number of routes (i.e., 20 in this example), we have the probability that each link is being used for a packet transmission from the source to the destination (Fig. 9.c). For example there are 6 routes passing through link AB, so there is a 30% chance that a min-route algorithm uses this link to send a packet from the source to the destination. For each link of the mesh, if we compute the usage probability of the link for every pair of source and destination nodes and average them, we will have the probability that a link is being used in packet transmission from a random source to a random destination. Fig. 10 shows the average usage probability for each link of a 4-by-4 and of a 5-by-5 mesh for a min-route algorithm. Due to the symmetric property of the problem, the values of the vertical edges are the same as the values of the corresponding horizontal edges. For example, there is an equal chance that a packet goes through link AB or CD. In this experiment, without loss of generality, we consider each link as a bidirectional link. Notice that, if we break each link into two unidirectional links, because of the symmetric property of the random packet transmission, the chance of using each of the two unidirectional links is equal to half of the usage probability of the bidirectional link. Fig. 11 shows the results of similar experiments on an 8by-8 mesh in a 3-D view. This figure simply plots the values on the horizontal links of the mesh, while the values of the vertical links can be obtained by the matrix transposition of the values of the horizontal links. Fig. 11.a shows an XYroute, and Fig. 11.b shows a min-route. As this figure illustrates, for the min-route approach, the closer a link is to the center of the mesh, the more important it is in a packet transmission, and so it deserves a better care. This motivates the idea of allocating more spares to the inner links than to the outer links. Fig. 12 shows two non-uniform spare-wire distribution patterns, named P-1-2 and P-2-3. In these patterns, we allocate one more spare wire to those links with a usage probability of greater than 0.1, based on the experimental data of Fig. 10. Fig. 13 compares the yield of the nonuniform patterns, such as P-1-2, with the yield of uniform patterns such as P-1 (i.e., allocating one spare wire per link). We observe that there are several remarkable jumps in the yield when we switch from a uniform pattern to the next non-uniform pattern, but there is also a cost associated with the extra spares that we have in the non-uniform patterns. Therefore, for a more meaningful comparison, we need to compare the total cost of the chips that use a uniform or nonuniform distribution. Fig. 14 shows this comparison and, as we can see, for many cases the cost is minimal for a nonuniform pattern.

14 12 10

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6 Quality Constraint

0. 5 0. 55 0. 6 0. 65 0. 7 0. 75 0. 8 0. 85 0. 9 0. 95

0 0. 05 0. 1 0. 15 0. 2 0. 25 0. 3 0. 35 0. 4 0. 45

4

Figure 8. Total cost vs. required quality for different numbers of spare wires in a 9-out-of-12 chip. TABLE III INPUT VALUES USED IN THE EXPERIMENTS OF THIS SECTION AND FOR THE REST OF THE PAPER

Figure 9. Number of routes passes through each link, and the probability of each link being used in a packet transmission from Src to Dest.

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IV.

In this paper, we define a quality metric for a mesh-based NoC and illustrates that the quality analysis reveals new information about the system beyond the connectivity analysis which can be used to guide the sparing strategy for yield improvement, quality enhancement and cost reduction. Information about the communication quality can also be used as a metric to price the chip in the market. We also propose to distribute the spare wires based on the contribution of each link to the overall quality of the network which leads to a non-uniform distribution of spare wires.

Figure 10. The average usage probability of links in a random packet transmission for a 4-by-4 and a 5-by-5 complete mesh. Usage Probability

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ACKNOWLEDGMENT The authors acknowledge the support of the Gigascale Systems Research Center (GSRC), one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program.

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REFERENCES 6

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[1]

b. Min-route

a. XY-route

Figure 11. The average usage probability of the links of an 8-by-8 mesh for the XY-route and the min-route approaches.

[2] [3] [4] [5] [6]

Figure 12. Two examples of non-uniform distributions of spare wires.

[7]

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[8] Yield

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[9]

q=0

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q=0.95 Spare Wires Pattern

0 P-0

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[12]

P-4

Figure 13. Yield associated with different spare-wire patterns under a quality constraint.

[13]

20

14

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16

[14]

min cost =15.98

18

[15]

q=0.5 q=0.6

[16]

q=0.7

12

q=0.8

10

q=0.9

min cost =2.99

8

[17]

min cost =4.78

6 4

[18]

min cost =2.67

2

min cost =2.66

0 P-1

P-1-2

P-2

P-2-3

P-3

CONCLUSION

Spare Wires Pattern P-3-4

[19]

P-4

Figure 14. Total cost associated with different spare-wire patterns subject to a quality constraint.

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