Modeling Current-Mode-Controlled Power Stages for Simulating Multiple-Module Inter-Connected Power Supply Systems Runxin Wang, Student Member, IEEE, Jinjun Liu, Member, IEEE, Hao Wang, Student Member, IEEE School of Electrical Engineering, Xi’an Jiaotong University, Xi’an, CHINA E-mail: [email protected] Abstract- This paper continues the efforts on behaviorally modeling multiple-module inter-connected power supply systems and presents detailed derivations of the lower-frequency power transfer models for non-isolated ûuk, SEPIC and Zeta power stages, which will make up a complete family of basic converter models together with those in the previously published paper.1The models play an important role in the simulation scheme proposed to predict and investigate large-signal subsystem interactions in a distributed power system.

uin dc ac

dc dc

EMI Filter

Load

Dc Bus

.

..

dc

EMI Filter

.

dc ..

Load

.

..

Index Terms- ûuk converter, SEPIC converter, Zeta converter, lower-frequency power transfer model, computer simulation EMI Filter

I.

INTRODUCTION

After inter-connecting different converter modules to form a complex power supply system, as illustrated in Fig. 1, the computer simulation to the enlarged system often encounters more challenges than that of a single stand-alone module at least due to the following three reasons: First, the scale of simulation circuit is significantly enlarged and much more devices need be handled during simulation; Second, the enlarged system may contain many closed control loops; Third, as each module usually work with its own frequency, switching moments may conflict each other during simulations. Therefore, in the occasions of simulating multiple-module inter-connected power supply systems, multi-level modeling and simulation approach must be employed in order to overcome the shortcomings of purely adopting detailed switching models in simulation or even just make the simulation run[1]. Paper [2] made contributions to the above-mentioned multilevel structure by proposing a methodology of establishing large-signal simulation models for the current-mode-controlled power supply modules. The power stage models, referred as the lower-frequency power transfer models hereafter in this paper, for the basic buck, boost and buck-boost converters were correctly derived, which were very necessary for introducing and explaining the proposed approach.

This work was supported by the National Nature Science Foundation of China (NSFC) under Grant Number 50677053. This work was also supported in part by ASTEC Custom Power (HK) Ltd. and in part by grants from the Power Electronics Science and Education Development Program of Delta Environmental & Educational Foundation.

1-4244-0655-2/07/$20.00©2007 IEEE

dc dc

Load

Figure 1 A typical multiple-module inter-connected power supply system.

This paper will continue efforts on the lower-frequency power transfer models of power stages. It’s targeted to present detailed derivations of the models for non-isolated ûuk, SEPIC and Zeta power stages, which will make up a complete family of basic converter models together with those in paper [2]. The rest of this paper is organized as follows. The principle of modeling approach proposed in paper [2] and some assumptions in modeling are briefly introduced in Section 2. The detailed derivation of the lower-frequency power transfer models for non-isolated ûuk, SEPIC and Zeta power stages in current-mode-controlled converters are presented in Section 3. Conclusion remarks are given in section 4. II. CONCEPT OF THE LOWER-FREQUENCY POWER TRANSFER MODEL The lower-frequency power transfer model of power stages is used in the simulation scheme proposed by paper [2], as shown in Fig. 2 and Fig. 3. In this scheme, the command signal for the controlled current (as vc in Fig. 2) is assumed to be followed ideally and the current-mode-controlled power stage including inner current loop that has a much faster dynamic responding speed than the external voltage loop, was treated as a two-port and replaced by an algebraic operation block. Any other components including startup and fault-handling components, especially the whole voltage loop compensator network, are kept to stay in the simulation circuit, as they did in a switching model, as closely as possible.

975

The algebraic operation block shown in Fig. 3 reflects the balance relation between average input power and average output power and no concrete circuits are involved in it. The simulation engine needs only to treat the analogy circuit and algebraic operation, so the simulation can be dramatically accelerated by removing the time-consuming switching actions. Algebraic operation block in Fig. 3 is based on the symbol shown in Fig. 4 that is built by several multipliers and dividers to implement the following function, u1 (˜) u i1 (˜) u2 (˜) u i2 (˜) (1)

Different to instantaneous relation in Eq. (1), Eq. (3) is valid only in frequency range that is much lower than the switching frequency. Moreover, the power balance relation of a real power stage is not as simple as that in Eq. (3) because the power changes in energy storage components inside the power stage, i.e. inductors and capacitors must be considered in any large-signal transient process simulation. Assume the converters started from zero initial condition at time t=0. From the energy relation

If all these four variables are replaced by averaged values of input voltage, input current, output voltage and output current respectively, i.e.LJuin Lj,LJiin Lj,LJuout LjandLJiout Lj, where LJxLjis the simplified denoting symbol for

(4)

x(t )

1 Ts

Ts

³

t Ts

t

x(W )dW

one can get

³

uout u iout

(3)

Sensor Gain

t

0

Wout  ¦ WL  ¦ WC

uin iin dW

1  ¦ L iL 2

(2)

Eq. (1) will become

uin u iin

Win

2

³

t

0

uout iout dW

1  ¦ C uC 2

(5)

2

which plays as the start-point to consider the energy variations in inductors and capacitors. Modifications to Eq. (3) according to Eq. (5) will lead to the final power stage model as shown in Fig. 5. The detailed derivation process will be shown in the next section.

Zf Zin

vc Current



Controlled Current

Loop

+

vout

Power Stage

D(t)

LOA D

Error Amp

Vref

Divider

C

E1

uin Figure 2 An ideal current-mode-controlled power system. Algebraic Operation Blocks

v in

Circuit Models

Vref ˇ

Voltage Compensator

vc

K

ictrl

iin

uout

Power Stage Model

ˉ

vo

iout

C

iout

Sensor Gain

[2]

Figure 3 Proposed modeling approach .

u1

i1

u2

u1i1 =u2i2

LOA D

Voltage Error

uin

iin

_

i1

E2

u2

u1i1 =u2i2

+

_

i2

uout

iout

Figure 5 Final form of the lower-frequency power transfer model.

Similar to paper [2], the following assumptions are made for the modeling derivations in next section: 1. The power stages under modeling are lossless; 2. No distinguishing the peak-current mode control and average-current mode control[3,4]; 3. The power stages are working in continuous conduction mode; 4. The input current is controlled. III. THE LOWER-FREQUENCY POWER TRANSFER MODELS FOR ûUK, SEPIC AND ZETA POWER STAGES

i2

Figure 4 Basic part of the algebraic operation block.

+

u1

A common feature among ûuk, SEPIC and Zeta power stages is that each of them has a capacitor C and two inductors, L1 and L2, inside the power stage. So all these three power stages have the same energy relation and power relation as follows:

976

Energy relation

³

t

0

During D’:

uin iin dW

1  L1 iL1 2

2

³

t

0

iC

uout iout dW

1  L2 iL2 2

2

1  C uC 2

2

 L1 iL1

dt

 L2 iL2

d iL2

(7)

uin iin

(8) (9)

C iC

Figure 6 Capacitor volt-ampere relation.

uout uin

E2

(10)

In a lower-frequency large-signal transient process, during which the system can be approximately regarded in steady or quasi-steady states, the duty ratio D(t), hereafter simplified to D, can be reversely derived by Eq. (10). For example, in ûuk power stage,

d iout dt

CurrentProbe1 Iin

 uC

d iin dt

1  D

(18)

iin  D iout



Dif f Probe Uc

CurrentProbe3 Ic

16m L1

16m

C

L2

CurrentProbe2 Iout

VOUT

D IDEAL

75 R_Load

47u Cout

(11)

V_driv e I_Switch CurrentProbe5

Id CurrentProbe4

Figure 7 The ûuk power stage. I_Sw itch Ic Id Iin

I_Switch / mA

(12)

Iout Uc VOUT

250 200 150 100 50 100

Ic / mA

50 -0 -50 -100 -150 250 Id / mA

Eq. (12) can be implemented in simulation circuits by easily detecting the input and output voltages and sending them to a divider, as illustrated in Fig. 5.

47u

Switch 15 Vin

200 150 100 50 0 110

Iin / mA

uout  uin

(17)

d iin 1  D t  1  D iin  D iout dW dt C ³0 (20) d iout D t L2  ³ 1  D iin  D iout dW dt C 0 X1

90

Iout / mA

D

iout

L1

Reversely deriving D and replacing instantaneous values by averaged values, one can get

uout

iL2

Considering Eq. (8) and (9), Eq. (18) can be rewritten to the canonical form as § d iin 1  D t · iin ¨ uin  L1  1  D iin  D iout dW ¸ ³ 0 dt C © ¹ (19)

E1

D  1 D

(16)

uout iout  L1 iin

 L2 iout

Another common feature among ûuk, SEPIC and Zeta power stages is

uout uin

iin

§ d iout · D t iout ¨ uout  L2  ³ 1  D iin  D iout dW ¸ 0 dt C © ¹ Thus the ûuk power stage is modeled into the final form as shown in Fig. 5 where

uC

D 1 D

iL1

Substitution Eq. (15), (16) and (17) into Eq. (7) leads to

For capacitor C, if defining the reference direction as shown in Fig. 6, the volt-ampere relations appear as:

M ( D)

(15)

In ûuk power stage,

dt

d uC C iC dt 1 t uC iC dW C ³0

iin  D iout

1  D

iC

uout iout  uC iC d iL1

(14)

Hence,

(6)

Derivative to time leads to power relation,

uin iin

iin

-110 -120

70 50 -90

A. ûuk Power Stage

-140 -150

Uc / V

24.14

977

24.02 23.98

VOUT / V

Let duty cycle be D. Consider the power stage shown in Fig. 7 and the steady-state simulation results in Fig. 8. During D: iC iout (13)

24.1 24.06

-9.065 -9.075 -9.085 -9.095 0 time/mSecs

0.2

0.4

0.6

0.8

1 200µSecs/div

Figure 8 Steady-state simulation results in the ûuk power stage.

B. SEPIC Power Stage

E1

Let duty cycle be D. Consider the power stage shown in Fig. 9 and the steady-state simulation results in Fig. 10. During D: iC iL2 (21)

iout

0

iout

iin iin  iL2

2

(23)

D 1 t§ D · iout ¸ dW ¨ iin  1  D C ³0 © 1 D ¹



CurrentProbe1 Iin

(26)

IDEAL

C

D

CurrentProbe2 Iout

VOUT

L2 9.75u 3.9 R_load

940u Cout V_Driv e I_Switch CurrentProbe5

(27)

[5]

Diff Probe Uc I_L2 I_Sw itch Ic Diff Probe Uc / V

iin

I_L2 CurrentProbe4

Figure 9 The SEPIC power stage .

(28)

(29)

Iin Iout VOUT

40 38 36 34 32 30

I_L2 / A

-3.6 -4 -4.4 -4.8 -5.2 -5.6 9 I_Switch / A

d iin uin iin uout iout  L1 iin dt § i · d ¨ iin  out ¸ 1 D ¹ § i ·  L2 ¨ iin  out ¸ © 1 D ¹ dt © D § ·  uC ¨ iin  iout ¸ 1 D © ¹

7 5 3 1

Ic / A

3 1 -1 -3 -5 4 Iin / A

3.6 3.2 2.8 2.4 2

Iout / A

8 6 4 2 0

(30)

VOUT / V

17.973 17.972 17.971 17.97 0

1

2

3

4

5

6

7

time/µSecs

8

9 1µSecs/div

Figure 10 Steady-state simulation results in the SEPIC power stage.

Considering Eq. (8) and (9), Eq. (30) can be rewritten to the canonical form as

§ d iin d iin L d iout  L2  2 ¨ uin  L1 dt dt 1  D dt ¨ ¨ 1 t§ D · ¨  C ³0 ¨ iin  1  D iout ¸ dW © ¹ ©

iout

300n

36 Vin

iout 1 D D  iout 1 D

d iout § L2 d iin L2  ¨ uout  2 1  D dt 1  D dt ¨ ¨ t ¨  D 1 §¨ iin  D iout ·¸ dW ¨ 1  D C ³0 1 D © ¹ ©

CurrentProbe3 Ic

9.75u

Switch

Substitution Eq.(27), (28)and (29) into Eq. (7) leads to

iin

Dif f Probe Uc

L1

In SEPIC power stage,

iL1

(32)

(25)

iin  iin

dt

L2 d iout 1  D dt



From Eq. (25) and (26), one can get

iC



(22)

X1

2

iL2

d iin

(24)

1  D iin  D iL 1  D iin  iL

iout

dt

 L2

D 1 § · iout ¸ dW ¨ iin  C ³0 © 1 D ¹ d iout L d iin L2 E2  2  2 1  D dt 1  D dt

Hence,

iC

d iin

t



During D’:

iC

L1

· ¸ ¸ ¸ ¸ ¹ (31)

C. Zeta Power Stage Let duty cycle be D. Consider the power stage shown in Fig. 11 and the steady-state simulation results in Fig. 12. During D: iin iL1  iC (33)

· ¸ ¸ ¸ ¸ ¸ ¹

iC

iout

(34)

iin iC

0 iL1

(35)

During D’:

Thus the SEPIC power stage is modeled into the final form as shown in Fig. 5 where

978

(36)

Hence,

iin



D iL1  iout



(37)

D iout  1  D iL1

iC

Dif f Probe Uc

X1

(38)

From Eq. (37) and (38), one can get

iL1 iC

iin  iout D 1 D iout  iin D

CurrentProbe1 Iin

Switch

IPROBE3 Ic

(39)

447n

30m

C

L2

I_L1 CurrentProbe3 300 Vin

CurrentProbe2 Iout

D IDEAL

V_Driv e

100 R_Load

447u Cout

L1 13.6m

(40)

VOUT

Id IPROBE2

In Zeta power stage,

iL

2

iout

(41)

[6]

Figure 11 The Zeta power stage .

Substitution Eq.(39), (40) and (41) into Eq. (7) leads to I_L1 / A

1.36

1.28

Id / A

Ic / A

1.24

Iout / A

Iin / A

(42)

2 1.5 1 0.5 0 -0.5 -1 3 2.5 2 1.5 1 0.5 0 3 2.5 2 1.5 1 0.5

1.99 1.98 1.96

Uc / V

1.94 -180 -185 -190 -195 -200 -205 -210

196.9173

196.91705 196.916950

Considering Eq. (8) and (9), Eq. (42) can be rewritten to the canonical form as § · L1 d iin L d iout  1 ¨ uin  2 ¸ D dt D dt ¸ iin ¨ ¨ 1 D 1 t § 1 D · ¸ ¨  D C ³0 ¨ iout  D iin ¸ dW ¸ (43) © ¹ ¹ © 1 t§ 1 D § · · ¨ uout  C ³0 ¨ iout  D iin ¸ dW ¸ © ¹ ¸ iout ¨ ¨ L1 d iin d iout d iout ¸  L1  L2 ¨ ¸ dt dt ¹ © D dt Thus the Zeta power stage is modeled into the final form as shown in Fig. 5 where

L1 d iin L d iout  1 2 D dt D dt t 1 D 1 § 1 D ·  iin ¸ dW ¨ iout  ³ 0 D C © D ¹ t 1 § 1 D · E2 iin ¸ dW ¨ iout  ³ 0 C © D ¹ d iout d iout L d iin  1  L1  L2 D dt dt dt

1.32

VOUT / V

d iin L uin iin  12 iin D dt d iout L 1 D  1 iin  uC iin D dt D d iin L uout iout  1 iout D dt d iout d iout  L1 iout  L2 iout  uC iout dt dt

20

30

40

50

60

70

80

90 10µSecs/div

Figure 12 Steady-state simulation results in the Zeta power stage.

ACKNOWLEDGMENT The authors thank Transim Technology Corporation for SIMPLIS software supports. REFERENCES [1]

[2]

E1

[3]

(44)

10

time/µSecs

[4] [5] [6]

IV. CONCLUSION The very detailed derivations of the lower-frequency power transfer models for non-isolated ûuk, SEPIC and Zeta power stages are presented in this paper. This paper serves as the most recent progress report and a supplement to publication [2].

979

Runxin Wang, Jinjun Liu, Hao Wang and Qinsan Hou, “Multi-level modeling of PFC rectifier and dc-dc converter modules in interconnected switching power supply systems,” IEEE APEC 2007, pp. 1475-1479. Runxin Wang, Jinjun Liu and Hao Wang, “Universal approach to modeling current mode controlled converters in distributed power systems for large-signal subsystem interactions investigation,” IEEE APEC 2007, pp. 442-448. L. Dixon, “Average current mode control of switching power supplies,” Unitrode Application Note, U-140. Venable Industries, New Techniques for Measuring Feedback Loop Transfer Functions in Current Mode Converters, available on the Venable Industries web site. at: http://www.venable.biz/ W.M. Moussa, “Modeling and performance evaluation of a DC/DC SEPIC converter,” IEEE APEC 1995, pp. 702-706. C. Sudhakarababu, M. Veerachary, “Zeta converter for power factor correction and voltage regulation,” IEEE TENCON 2004, pp. 61-64.

Modeling Current-Mode-Controlled Power Stages for ... - IEEE Xplore

Abstract- This paper continues the efforts on behaviorally modeling multiple-module inter-connected power supply systems and presents detailed derivations of ...

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