Model-based DRC for design and process integration Chi-Yuan Hung*a, Andrew M. Jost†b, Qingwei Liua a Semiconductor Manufacturing International Corp., 18 Zhangjiang Road, Shanghai, PRC 201203; b Mentor Graphics Corp., 8005 S.W. Boeckman Road, Wilsonville, OR, 97070-7777 ABSTRACT Accurately and efficiently verifying the device layout is a crucial step in semiconductor manufacturing. A single missed design violation carries the potential for a disastrous and avoidable yield loss. Typically, design rule checking (DRC) is accomplished by validating drawn layout geometries against pre-determined rules, the specifics of which are derived empirically or from lithographic first principles. These checks are intrinsically rigid, and, taken together, a set of DRC rules only approximate the manufacturable design space in the crudest manner. Process-specific effects are entirely neglected. But for leading-edge technologies, process variations significantly impact the manufacturability of a design, so traditional DRC becomes increasingly difficult to implement, or worse, speciously inaccurate. Fortunately, the rise of Optical Proximity Correction (OPC) has given manufacturers a means to accurately model optical and process effects, and, therefore, an opportunity to introduce this information into the layout validation flow. We demonstrate an enhanced, full-chip DRC technique, which utilizes process models to locate marginal or bad design features and classify them according to severity. Keywords: Design Rule Check (DRC), Model-Based DRC, Optical Proximity Correction (OPC), Litho-Friendly Design (LFD), PV-band, Calibre. 1. Introduction Layout verification is a crucial step in the IC design flow. Both the electrical performance and manufacturability of a design must be evaluated, the latter of which is normally accomplished through Design Rule Checking (DRC). Principally owing to its speed and ease-of-development, “traditional” DRC has enjoyed widespread acceptance in the IC industry, though it has important limitations. For example, traditional DRC does not capture the effects of OPC or assist features, nor does it account for optical interactions, which strongly affect manufacturability. Process models, which are used for OPC and other Resolution Enhancement Techniques (RETs), are so essential that every critical layer in a modern process is sure to be associated with an accurate model. These models carry far more information than do a set of empirically-derived design rules, so utilizing them in the design verification flow makes sense. Surprisingly, many of the tools needed to combine model-based simulation with DRC are already under development, if only with another purpose in mind. With the recent advancement of lithography-aware design tools, such as Mentor Graphics’ Litho-Friendly Design (LFD) tool, designers now have the means to evaluate a design’s manufacturability at several process conditions, while properly accounting for the effects of OPC and assist features. This tool leverages Calibre’s unique ability to quickly and accurately simulate multiple process conditions concurrently. There is no fundamental difference between the information a designer would hope to get from the LFD tool and the information an IC manufacturer would hope to get from a process-aware DRC tool, only that the latter tool must be capable of rapidly processing a full design while the former need not. In theory, chip makers could use the LFD tool to augment DRC in validating a full layout before initiating the tapeout flow, but that approach would be computationally expensive – more so than OPC itself. Our challenge is to improve on traditional DRC, utilizing process information to accurately identify more potential failures and classify them according to severity, without greatly increasing the computational requirements. 2. Performing model-based DRC * †

[email protected]; phone +86 21 5080-2000 ext.19556; fax +86 21 5080-4010 [email protected]; phone 503 685-8039; fax 503 685-7085 25th Annual BACUS Symposium on Photomask Technology, edited by J. Tracy Weed, Patrick M. Martin, Proc. of SPIE Vol. 5992, 59923M, (2005) · 0277-786X/05/$15 · doi: 10.1117/12.631505

Proc. of SPIE Vol. 5992 59923M-1

The goal of DRC is to identify features that are likely to cause manufacturing failures. Model-based DRC (MB-DRC) goes beyond traditional DRC in that it uses simulation to determine what constitutes a failure. Furthermore, if simulations are performed at several process conditions, MB-DRC can identify failures that degrade yield without abolishing it, a capability that forms the basis of error classification. An approach to MB-DRC using Mentor Graphics tools consists of the following steps: Step 1 – apply OPCa Step 2 – generate PV-bands to characterize the feature’s response through process conditions Step 3 – identify and classify errors Not coincidentally, this is the same process the LFD tool employs to verify a design1, meaning that the actual implementation of MB-DRC can be simplified by borrowing functionality from LFD. Steps 2 and 3 will be discussed in turn. 2.1. Generating PV-bands Process variability bands (PV-bands) are objects created by Calibre to help quantify how a specific feature will respond to changing process conditions. PV-bands can be used to study the variations of simulation contours through changes in focus, dose, mask size, or relative mask shift (for double exposure)2. PV-bands define a region of variable printability (Fig. 1). Area contained by the inner edge of the PV-band is sure to print, area outside the outer edge of the PV-band is sure not to print, but the area within the PV-band sometimes prints within the given process window. To put it another way, the simulated contour of a given feature at any point in the process window should lie completely inside the PVband for that feature.

Fig. 1 PV-band Drawn feature PV-band Area that will print Area that will not print

PV-bands are used to perform unique checks that would be impossible with only the drawn layout or a single simulated contour. A single check operating on PV-band input can yield information about how a feature behaves through many process conditions. For example, by measuring the thickness of a PV-band, we gain information about the variation in edge placement for that region, which in turn can be used to quantify CD variability. Thin PV-bands correlate to small CD variability; thick PV-bands correlate to large CD variability. PV-bands offer fundamentally different information than drawn geometry, so checks based on PV-bands are fundamentally different than typical DRC checks.

a

This includes the generation of assist features and the application of any pre-OPC logical operations that are required. In other words, every operation that would be applied to the design, all the way through OPC.

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2.2. Identifying and classifying errors PV-bands can be used to determine the likelihood of failure. The LFD tool provides checks for several types of errors – including pinching, bridging, overlap, and gate CD uniformity – that can accept PV-bands as input. These checks are used not only to identify errors, but also to classify them by severity. A simple example is a bridging check, where the minimum space between two PV-bands is measured. The smaller the space, the greater the potential for bridging. The perceptive reader will note that a DRC check can also be written to classify errors in this way, but far more information is gained when PV-bands are used. That’s because, no direct relationship exists between the magnitude of a DRC error and the likelihood for failure. Although a more severe DRC error would tend to result in a greater likelihood for failure, the trend is general. A relatively large DRC violation in an innocuous context may be far less dangerous than a smaller DRC violation occurring in a context that exacerbates the problem. The fact that PV-bands are based on simulated contours, which properly account for context, makes a classification system based on PV-band checks valid. 2.3. Limits of MB-DRC MB-DRC has the potential to improve the identification and classification of several failure classes, but it is not suitable for all types of failure. The particular strength of MB-DRC relative to traditional DRC comes from the added lithographic information, so improved checks for lithographic defects such as pinching, bridging, or CD uniformity can be written employing MB-DRC. Enhanced checks, however, for non-lithographic failure classes (metal slotting rules, for example) cannot be written with MB-DRC. 3. Types of MB-DRC There are several ways to implement MB-DRC. Three will be considered here: full-chip dense simulation, full-chip sparse simulation, and hybrid. 3.1. Full-chip dense simulation MB-DRC In full-chip dense simulation MB-DRC, the entire layout is simulated using dense sampling (after OPC is applied) to generate PV-bands. The PV-bands are used in subsequent failure checks, meaning that every part of the design is checked, even where no geometry is drawn. This type of DRC maximizes coverage. In addition to identifying pinching, bridging, CD uniformity, and other problems associated with drawn polygons, dense simulation has the ability to catch other phenomena such as side lobes or printing assist features that may not be associated with design geometry. Dense simulation can identify every failure class that other methods would find and more. But the price for superior coverage is high, as dense simulation is computationally very expensive. Although many are working to improve the speed of dense simulation, the computing resources required are still enormous, making dense full-chip sampling unsuitable for MB-DRC. 3.2. Full-chip sparse simulation MB-DRC In full-chip sparse simulation, the entire layout is fragmented and simulation sites, which are associated only with fragments, are defined. Simulation is performed only at the simulation sites (after OPC is applied) to construct PVbands. Sparse-simulation MB-DRC is faster than dense-simulation and can identify almost as many problems. The performance boost occurs because fewer intensity calculations are required. But the positioning of simulation sites depends on a fragmentation script, which adds a level of complexity (and risk) to the implementation. Additionally, since the simulation sites are associated with design edges, sparse simulation is only good at identifying problems that are associated with design geometry. Other failure classes (that dense simulation might report) cannot be detected using sparse simulation. Although sparse simulation is less computationally intensive than dense simulation, it is still much slower than traditional DRC. In fact, the most common OPC applications today use sparse simulation to perform OPC and OPC verification, so any MB-DRC technique with full-chip sampling would require as many (or more) computing resources

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as those applications. Such approaches are not suitable for MB-DRC, as most IC manufacturers would balk at a DRC flow that surpasses OPC in its hunger for computing power. 3.3. Hybrid MB-DRC A hybrid MB-DRC technique consists of two sequential steps, 1) filtering , and 2) analysis. It uses traditional DRC to identify potential problems areas (filtering), then relies on model-based simulation to examine and classify these potential errors (analysis). As compared to either of the full-chip simulation methods discussed above, a hybrid approach will always be faster, but with inferior coverage. The analysis step can use either dense or sparse simulation, but since traditional DRC is used to filter the layout, the dense simulation loses its ability to find “floating” errors. On the other hand, the dense simulation is easier to configure and more reliable because no fragmentation occurs. If the filtering step sufficiently limits the number of potential errors (i.e. the total run time is dominated by filtering) then dense simulation analysis is preferred. A hybrid MB-DRC implementation can be configured to identify the same errors that traditional DRC would find, plus additional ones that traditional DRC would miss. This is because the filtering can identify potential design problems that are not DRC errors. If such an error turns out to be innocuous, the analysis step will discard it. But if the analysis confirms the feature is an error, then the method has succeeded in identifying an error that traditional DRC would have missed. In addition, DRC errors that would normally be reported in pass/fail fashion can be classified according to severity. Thus, a hybrid MB-DRC approach could be the foundation of an automated DRC waiver system. Hybrid MB-DRC offers many advantages over traditional DRC without the enormous outlay of computational resources that other MB-DRC strategies would require. 3.4. Removing duplicate errors The performance of a hybrid MB-DRC approach is dependent on the number of potential failures identified in the initial filtering step. Thus, the actual run time cannot be predicted. Additionally, errors that occur deep in the hierarchy may be repeated an enormous number of times. To reduce the number of redundant simulations, a robust MB-DRC implementation should be able to identify and eliminate duplicate potential failures before simulation begins. Calibre provides the DBclassify function to perform this data reduction. It allows users to reduce a large set of errors (containing duplicates) into the smallest set possible of unique errors. The DBclassify tool eliminates duplicate errors based on the actual geometry present, including nearby features, so it can remove all duplicates no matter how they are arranged hierarchically. DBclassify was not used in this study, but is mentioned for completeness. 4. Using process window models to improve accuracy Any time we need to simulate the response of a feature to changes in process conditions, we must worry about the accuracy of the model. One advantage of the Mentor Graphics approach to modeling – namely that optical and nonoptical effects are modeled separately – is that it is easy to perform simulations at arbitrary dose and defocus. But a model that is tuned to a single set of process conditions rapidly loses accuracy as the actual conditions deviate from nominal, and exactly how much accuracy is lost for a given deviation can only be determined experimentally. For that reason, it is generally unsafe to use such a model to perform simulations at non-nominal conditions. With Calibre, it is possible to create models that make accurately predictions through process window. These models – aptly called process window models, or PW-models – are generated using data from several process settings. Fig. 2 compares the accuracy of a standard model and a PW-model across a window of ±4% dose, and ±0.160 µm defocus. At nominal conditions the two models are almost equally accurate, but as the process conditions move away from nominal (particularly to negative defocus) the PW-model is far superior. In no case is the PW-model inferior to the standard model. An additional point worth noting is that PW-models do not impact the time required to perform simulations. The price for using a PW-model is simply the up-front cost in engineer time of taking additional measurements through dose and focus. But to use MB-DRC it is necessary to characterize the model accuracy through process window anyway, so the additional cost of collecting modeling data at these conditions is minimal. By using PW-models (rather than standard

Proc. of SPIE Vol. 5992 59923M-4

models) in conjunction with MB-DRC, we can more accurately calculate PV-bands without degrading performance and, therefore, more effectively identify features that pose a manufacturing risk. Fig. 2 Process window model accuracy DOSE +4%

A: 10.08 / 13.79 B: 1.79 / 3.58

1D / 2D A: 1.10 / 3.48 B: 1.28 / 3.64

nom

-4%

LEGEND: A: standard model B: PW model

A: 11.83 / 17.30 B: 2.33 / 3.24 -0.16 µm

A: 1.89 / 4.75 B: 1.52 / 4.55 nom

+0.16 µm

DEFOCUS Fig. 2 The residual rms EPE error (in nm) for a standard model, A, and a process window model, B, through several process conditions. A 90 nm poly process was used for the experiment. In each case the upper pair of numbers relates to the standard model and the lower pair relates to the PW model. The values are reported for 1D and 2D features, with the 1D features listed first.

5. Full-chip MB-DRC experiments To test the MB-DRC concept we selected a DRC-clean 6 mm by 3 mm database containing both random logic and memory, then introduced potential failure points on the poly, metal 1, and metal 2 layers. The layout was then run through a standard DRC flow and through a hybrid MB-DRC flow that used dense simulation (20 nm sample point spacing) for analysis. The goals were to test the identification and classification capabilities of MB-DRC and to compare the performance of each method. 5.1. Failure classes Several types of potential failures were introduced into the test layout (Table 1). All, except for notched metal posts, qualify as DRC errors. The LFD tool provides several built-in checks that utilize PV-bands to evaluate the robustness of a design. The name of the LFD check associated with each failure class is listed in Table 1. Some simple failure classes (for example, minimum linewidth) were intentionally omitted from the experiment because they are easily identified by traditional DRC and generally would not be waived. The goal was to focus on features that are either difficult to identify using traditional DRC or that may result in a DRC violation where there is no risk of failure.

Proc. of SPIE Vol. 5992 59923M-5

Table 1 Failure classes and checks used for MB-DRC experiments Failure Class Applies to Check for LFD Check Name LE-to-LE spacing violation poly / metal bridging MinSpaceCheck LE-to-edge spacing violation poly / metal bridging MinSpaceCheck Corner-to-corner spacing violation metal bridging MinSpaceCheck Zig-zag* linewidth violation metal pinching MinWidthCheck Poly extension past active poly CD uniformity MaxAreaVariabilityCheck Extension past contact / via poly / metal overlap MinAreaOverlapCheck Notched metal post metal bridging MinSpaceCheck *See Fig 4 (frames E-G) for an illustration

5.2. Extracting and processing analysis zones As previously mentioned, hybrid MB-DRC is a two-step process. The filter step was configured to capture all DRC errors, plus notches occurring in metal posts. The latter is a special case that does not constitute a DRC error, but has the potential to ruin OPC. It illustrates a failure that MB-DRC can identify, but that traditional DRC would miss (see section 6). Each potential error identified in the filtering step is captured in an analysis zone, consisting of three portions (Fig. 3). The innermost section is the region of the actual violation. The middle section is a simulation window created around the failure point. The outermost context window provides the proximity information required for accurate simulation. The distance from the outer edge of the simulation window to the edge of the context window is greater than the optical influence radius, as determined from pitch data. Fig. 3 A MB-DRC analysis zone

Failure Point Simulation Window Context Window

After the filtering step, PV-bands were calculated in each analysis zone and the LFD checks were executed. The analysis zones are processed individually, so the scaling of the analysis step is expected to be approximately linear (see section 5.6). Thus, scaling to a large number of analysis zones is possible. 5.3. Checks for bridging Fig. 4 (frames A-D) shows a bridging point induced in the poly layer. Frame A shows a feature drawn at the minimum dimensions allowed by design rule. Frames B-D contain design rule violations of increasing severity. The LFD tool, in

Proc. of SPIE Vol. 5992 59923M-6

conjunction with a tuned PW-model, was used to generate PV-bands in a window of ±10% energy dose and ±0.160 µm defocus. Bridging errors were classified according to the minimum space measured between the PV-bands using the following rules: if the space is >= 85% of the minimum allowed space (that is, the minimum design rule space), the feature is classified as “not bridging”. Features with a space of 85%-65% of the minimum allowed space are classified as “bridging,” and those below 65% are classified as “severe bridging”. Features A and B are classified as “not bridging,” C is “bridging,” and D is “severe bridging”. Note that B is a DRC violation, but simulation shows the feature does not bridge – it illustrates a waivable DRC error that is indistinguishable from a true failure using traditional DRC, but that is distinguishable from a true failure using MB-DRC.

A

H

Fig. 4 Pinching and bridging errors Frames A-D show a bridging point induced in the poly layer. A is drawn at the minimum dimensions allowed by design rule. B-D are design rule violations of increasing severity. PV-bands were generated with a tuned PW-model in a window of ±10% energy dose and ±0.160 µm defocus. Frames E-G show a pinching point induced in a metal layer. E is drawn at the minimum dimensions allowed by design rule. F-G show design rule violations of increasing severity. PV-bands were generated in a window of ±10% energy dose and ±0.200 µm defocus.

B

C

D

IIIIII

E

F

G

5.4. Checks for pinching Fig. 4 (frames E-G) shows a pinching point induced in a metal layer. Frame E shows a feature drawn at the minimum dimensions allowed by design rule. Frames F-G contain design rule violations of increasing severity. The LFD tool, in conjunction with a tuned PW-model, was used to generate PV-bands in a window of ±10% energy dose and ±0.200 µm defocus. Pinching errors were classified according to the minimum space measured between the PV-bands using the same rules outlined above for the bridging checks (>=85%, “not pinching”; 85%-65%, “pinching”; <65%, “severe pinching”). Feature E is classified as “not pinching,” F is “pinching,” and G is “severe pinching”. 5.5. Checks for overlap and gate CD uniformity

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The LFD tool also includes checks for PV-band overlap and gate CD uniformity. MB-DRC was able to identify and classify errors that resulted in poor metal-via overlap, poor poly-contact overlap, and poor poly CD uniformity across the gate region (data not shown). 5.6. Performance The performance of MB-DRC relative to traditional DRC is a primary concern. The goal is to take advantage of the most important features of MB-DRC while incurring the smallest possible performance penalty. An analysis of the fullchip MB-DRC experiments is shown in Table 2. Table 2 Performance of DRC and MB-DRC DRC MB-DRC

Number of Analysis Zones NA 1 16 64

Total Run Time (1 CPU) 1299 s 1410 s 1423 s 1464 s

Scaling NA NA 0.87 s / region 0.85 s / region

There is a significant cost associated with simply invoking the MB-DRC run because additional commands are executed to capture the analysis zones. But beyond this, the time required to process additional analysis zones is comparatively small. The data indicate that several hundred or more analysis zones could be examined without dramatically degrading the performance relative to traditional DRC. 6. Finding “hidden” failures Certain types of high-risk features cannot be reliably identified by traditional DRC. For example, small jogs and notches do not pose a direct lithographic risk, but they can nevertheless result in failures by causing OPC to fail. Most OPC algorithms include some level of jog/notch clean-up, but generally not all features can be cleaned and no rule can be written in advance to identify all the features that will cause OPC to fail. If a “hidden” failure is fatal to the OPC result, it is often noticed only after the entire chip has been processed through the OPC and OPC verification steps. This Fig. 5 A catastrophic failure resulting from tiny jogs. Two 1 nm jogs were introduced into opposing edges in a series of metal 2 posts (frame A). Frame B shows the impact on fragmentation and site placement. The PVbands after OPC, calculated in a window of ± 10% energy dose and ± 0.200 µm defocus, show catastrophic bridging where the jogs were introduced (frame C).

A

IL I n PCi

B

GO

C

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represents an extremely expensive method for locating errors. A fast layout verification technique to identify hidden failures would greatly improve the situation. MB-DRC can be used to identify hidden failures and classify them according to the risk they pose. This requires a rule to identify potential hidden errors. Although it is not possible to write a rule to unequivocally identify hidden errors, it is possible to identify features that might cause a failure. Fig. 5 shows an example of a feature that could cause a catastrophic failure – a series of metal 2 posts with 1 nm jogs introduced into a pair of edges (frame A). Note that this design is DRC-clean. Frame B shows the feature after fragmentation and site placement. The small jogs interfere with site placement, so the sites are improperly located for this type of feature. Not surprisingly, the location of the simulation sites causes OPC to overcorrect, leading to the bridging evidenced by the PV-bands (frame C). A good OPC algorithm will attempt to locate and fix jogs and notches, but it is impossible to prove that a given algorithm – no matter how carefully developed – will completely obviate hidden failures. What counts is not whether some hypothetical OPC algorithm could avoid this problem, but whether the actual OPC algorithm used in production will avoid the problem. We propose that MB-DRC is an efficient way to improve reliability by identifying hidden failures early in the tapeout flow. 7. Conclusions The predictive capabilities of process modeling can be effectively pushed into the layout verification flow by using MBDRC. The most important advantages of MB-DRC relative to traditional DRC are the abilities to identify additional errors and classify results according to severity. MB-DRC is able to waive some errors that traditional DRC would report, and report some errors that traditional DRC would miss. To realize these advantages, we considered three approaches to MB-DRC (dense, sparse, hybrid). Each was outlined and contrasted with the goal of achieving the most important advantages of MB-DRC with a minimum of computational expense. Of these options, a hybrid approach was chosen for our experiments as the best overall option. A hybrid MBDRC implementation was demonstrated at full-chip scale, which was able to identify bridging, pinching, overlap, and gate CD uniformity problems. The LFD tool provided an efficient platform upon which the MB-DRC implementation could be rapidly developed. Performance data indicated that a large number of potential failures could be analyzed by this approach without a massive performance degradation. Finally, certain types of “hidden” failures cannot be identified with traditional DRC. A superset of these failures, however, can be identified. By using MB-DRC to classify the potential failures according to severity, it is possible to improve reliability. Acknowledgments The authors wish to thank Andres Torres and Jean-Marie Brunet for their help understanding and using the LFD tool. Also, thanks to Recoo Zhang and Gen-Sheng Gao for their efforts collecting process window data, and to Andres for tuning the PW-models. Special thanks to Mark Simmons for helping to conceptualize and proof the work.

REFERENCES 1 2

Calibre LFD User Manual, “Chapter 1: Introduction to Litho-Friendly Design: How LFD Works”, pg 1-3. Calibre OPCverify User Manual, pg 2-8.

Proc. of SPIE Vol. 5992 59923M-9

Model-based DRC for design and process integration

Model-based DRC for design and process integration. Chi-Yuan Hung*a, .... provides the DBclassify function to perform this data reduction. It allows users to ...

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