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MICRO PROCESSOR and MICRO CONTROLLER

UNIT –VIII Topics in the unit :Advanced Microcontrollers: MCS – 96 Microcontrollers: Important Features, Pin Diagram, Internal Architecture, Memory Map, Addressing Modes, Instruction set. ARM Microcontrollers: ARM Core Architecture, Versions of ARM, Important Features.

Micro-Controller - 80C196 Features The 80c196 is an 16-bit microcontroller made by Intel using CHMOS technology. The 80c196 integrates on a single chip all interface elements which are generally in the close environment of a microprocessor. The 80c196 provide : 232 internal byte registers A register-to-register architecture Dynamically configurable 8-bit or 16-bit buswidth DMA capability A 16x16-bit 2.3 microsecond multiply (at 12MHz) A 32/16-bit 4.0 microsecond divide (at 12MHz) 28 interrupt sources with 16 vectors 6 16-bit timers, up/down counters or software timers A high speed I/O subsystem A serial port A 10-bit digital-to-analog converter with sample-and-hold 5 8-bit I/O ports A 16-bit watchdog timer Powerdown and idle modes Additional 256 bytes of on-chip RAM (KC only)

80c196 architecture Block diagram The 80c196 is mainly based on : A CPU which is turn composed of a 16-bit ALU with temporary registers, a 256-byte RAM used as 24 special registers and 232 general registers, and a microprogrammed sequencer. A memory controller with a 4-byte FIFO queue to prefetch instructions and data from the program memory. A set of I/O interfaces.

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The CPU gets his information only through the memory controller and the special registers also called Special Function Registers (SFRs). The ALU, is associated to a set of temporary registers (with shifter, counter, constants) and thus called RALU (Register ALU). The RALU doesn't use an accumulator but instead is ablt to directly work with any of the 256 special or general registers All I/O operations are controlled through the SFRs.

80c196 block diagram

Memory controller All of the program memory and external data memory are transferred to the CPU through the memory controller. The memory controller consists of a slave program counter, an instruction queue and a bus controller. The slave program counter keeps track of the instructions fetched from the program memory. Instructions fetched by the memory controller are stored in the queue. The slave program counter may be up to four bytes ahead of the main program counter (which is located in the RALU), because it is pre-fetching the instructions. The bus controller accesses program memory (on-chip EPROM) and external data memory and arbitrates between instruction fetches and data reads and writes. The bus controller supports both 8-bit and 16-bit external bus modes. Memory access requests to the bus controller can come from either the RALU or the queue, with priority given to the queue accesses. If the address sequence changes because of a jump, interrupt, call or return, the slave PC is loaded with a new value, and the queue is flushed. Reloading the slave PC, flushing the queue and fetching the the first byte of

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MICRO PROCESSOR and MICRO CONTROLLER the new instruction stream takes 4 state times. This is reflected in the conditional jump taken/not-taken execution times. The CPU The CPU is controlled by a microcode sequencer and can perform operations on any byte, word or doubleword in the 256-byte register space. Instructions to the CPU are taken from the pre-fetch queue and temporarily stored in the instruction register. The sequencer decodes the instruction and generates the correct sequence of events to have the RALU perform the desired operation. The RALU Most calculations performed by the 80c196 take place in the RALU. The RALU contains a 17-bit ALU Arithmetic and Logic Unit, the flag register also called PSW - Program Status Word, the main PC - Program Counter, a loop counter and three temporary registers. All registers are 16-bits or 17-bits wide.

The Register Arithmetic and Logic Unit The PC has a separate incrementor as to access operands. However, PC changes due to jumps, interrupts, calls and returns are handled through the ALU. Two of the temporary registers have their own shift logic. These registers are used for the instructions which require logical shifts, including Normalize, Multiply and Divide. The upper word and lower word registers are used together for the 32-bit instructions and as temporary registers for many other instuctions. Repetitive shifts are counted by the 6-bit loop counter. A third temporary register stores the second operand of two-operand instructions. To perform subtractions the output of this register can be complemented before being placed into the input of the ALU. The RALU also stores several constants such as 0,1 and 2 to speed up certain operations like getting a 2's complement, incrementing or decrementing

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2.4 Instruction set 2.4.1 Initializations CLR - Clear Word CLRB - Clear Byte CLRC - Clear Carry Flag CLRVT - Clear Overflow Trap SETC - Set Carry Flag

2.4.2 Data transfer BMOVE - Block Move (80c196KB only) LD - Load Word LDB - Load Byte LDBSE - Load Integer with Short-Integer LDBZE - Load Word with Byte ST - Store Word STB - Store Byte

2.4.3 Stack operations POP - Pop Word POPA - Pop All (80c196KB only) POPF - Pop Flags PUSH - Push Word PUSHA - Push All (80c196KB only) PUSHF - Push Flags

2.4.4 Arithmetic operations ADD - Add Words ADDB - Add Bytes

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MICRO PROCESSOR and MICRO CONTROLLER ADDC - Add Words with Carry ADDCB - Add Bytes with Carry DEC - Decrement Word DECB - Decrement Byte DIV - Divide Integers (signed) DIVB - Divide Short Integers (signed) DIVU - Divide Words (unsigned) DIVUB - Divide Bytes (unsigned) EXT - Sign Extend Integer into Long-Integer EXTB - Sign Extend Short-Integer into Integer INC - Increment Word INCB - Increment Byte MUL - Multiply Integers (signed) MULB - Multiply Short Integers (signed) MULU - Multiply Words (unsigned MULUB - Multiply Bytes (unsigned NEG - Negate Integer NEGB - Negate Short-Integer SUB - Subtract Words SUBB - Subtract Bytes SUBC - Subtract Words With Borrow SUBCB - Subtract Words With Borrow

2.4.5 Logical operations AND - Bitwise Logical AND Words ANDB - Bitwise Logical AND Bytes NOT - Complement Word NOTB - Complement Byte OR - Bitwise Logical OR Words

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MICRO PROCESSOR and MICRO CONTROLLER ORB - Bitwise Logical OR Bytes XOR - Bitwise Logical XOR Words

2.4.6 Shifts SHL - Left Shift Word SHLB - Left Shift Byte SHLL - Left Shift Double-Word SHR - Logical Right Shift Word SHRA - Arithmetic Right Shift Word SHRAB - Arithmetic Right Shift Byte SHRAL - Arithmetic Right Shift Double-Word SHRB - Logical Right Shift Byte SHRL - Logical Right Shift Double-Word

2.4.7 Comparisons CMP - Compare Words CMPB - Compare Bytes CMPL - Compare Long (80c196KB only)

2.4.8 Jumps and calls BR - Branch Indirect LCALL - Long Call LJMP - Long Jump RET - Return from Subroutine SCALL - Short Call SJMP - Short Jump

2.4.9 Conditional jumps DJNZ - Decrement and Jump if not Zero

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MICRO PROCESSOR and MICRO CONTROLLER DJNZW - Decrement and Jump if Not Zero Word (80c196KB only) JBC - Jump if Bit Clear JBS - Jump if Bit Set JC - Jump if Carry JE - Jump if Equal JGE - Jump if Greater or Equal (signed) JGT - Jump if Greater than (signed) JH - Jump if Higher (unsigned) JLE - Jump if Less or Equal (signed) JLT - Jump if Less than (signed) JNC - Jump if No Carry JNE - Jump if Not Equal JNH - Jump if Not Higher (unsigned) JST - Jump if Sticky bit JV - Jump if Overflow JVT - Jump if Overflow Trap

CONTROL INSTRUCTIONS DI - Disable Interrupts EI - Enable Interrupts IDLPD - Idle / Powerdown (80c196KB only) NOP - No Operation RST - Reset System SKIP - Two-byte NOP TRAP - Software Trap

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Addressing modes Operands are accessed within the address space of the 80c196 with one of 6 basic addressing modes. Some of the details of how these addressing modes work are hidden by the assembler language. AX, BX, CX, DX are 16-bit registers AL, AH are the lower byte and the higher byte of AX respectively BL, BH are the lower byte and the higher byte of BX respectively CL, CH are the lower byte and the higher byte of CX respectively DL, DH are the lower byte and the higher byte of DX respectively These are the same as the names for the general data registers used in the 8086. It is important to understand that in the 80c196 these are not dedicated registers, but merely the symbolic name assigned by the programmer to four words within the on-chip 232 general registers. Direct addressing The register-direct mode is used to directly access a register, selected by an 8-bit field within the instruction. The register address must conform to the operand's type alignment rules. Examples ADD INCB

AX,BX,CX CL

; (AX)16 <-- (BX)16 + (CX)16 ; (CL)8 <-- (CL)8 + 1

Important note : An instruction can contain only one non-direct operand reference. All other operands of the instruction must be register-direct references.

Indirect addressing The indirect mode is used to access an operand having its address in a word register. The indirect address may point anywhere into the address space, but must conform to the operand's type alignment rules. The register which contains the indirect address is selected by an 8-bit field within the instruction. Examples LD ADDB POP

BX,[AX] AL,BL,[CX] [AX]

; (BX)16 <-- ((AX)16)16 ; (AL)8 <-- (BL)8 + ((CX)16)8 ; ((AX)16)16 <-- ((SP)16)16 ; (SP)16 <-- (SP)16 + 2

Immediate addressing This addressing mode allows an operand to taken directly from a field in the instruction. For operations on bytes this field is 8-bit wide, for operations on words it is 16-bit wide.

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Examples ADD PUSH DIVB

AX,#340 #1234H AX,#10

; ; ; ;

; (AX)16 <-- (AX)16 + 340 (SP)16 <-- (SP)16 - 2 ((SP)16)16 <-- 1234H (AL)8 <-- (AX)16 / 10 (AH)8 <-- (AX)16 % 10

Short indexed addressing In this addressing mode an 8-bit field in the instruction selects a word register which contains an address. A second 8-bit field in the instruction stream (displacement) is sign-extended and summed with the register value to form the address of the operand. Since the displacement is sign-extended, the effective address can be up to 128 bytes before the address in the register, or up to 127 bytes after it. Examples LD MULB

AX,12[BX] AX,BL,3[CX]

; (AX)16 <-- ((BX)16 + 12)16 ; (AX)16 <-- (BL)8 * ((CX)16 + 3)8

Long indexed addressing This addressing mode is like short indexed addressing except that the displacement is a 16-bit field taken from the instruction stream to form the address of the operand. No sign extension is necessary. Examples AND (CX)16)16 ST (AX)16 ADDB (CX)16)8

AX,BX,TABLE[CX]

; (AX)16 <-- (BX)16 . (TABLE16 +

AX,TABLE[BX] ; (AX)16 <-- (TABLE16 + (BX)16)16 <-AL,BL,TABLE[CX]

; (AL)8 <-- (BL)8 + (TABLE16 +

These are the six basic address modes the 80c196 uses for accessing operands. However, several other useful addressing operations can be achieved by combining these basic modes with specific registers such as ZERO or the stack pointer : Memory direct addressing This mode of addressing is obtained by indexing SFR ZERO, located at address 0 which is fixed to value 0. In addition to providing a fixed source of the constant 0 for calculations and comparisons, this register can be used as the index in a long-indexed reference. This combination of register selection and address mode allows any location in memory to be addressed directly.

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Examples ADD POP

AX,1234[0] 5678[0]

; (AX)16 <-- (AX)16 + (1234)16 ; (5678)16 <-- ((SP)16)16 ; (SP)16 <-- (SP)16 + 2

Accessing the stack The system stack pointer is accessed as register 18H of the SFRs. In addition to providing for convenient manipulation of the stack pointer, this also facilitates accessing operands in the stack. The top of the stack, for example, can be accessed by using the stack pointer as the register in an indirect reference. In a similar fashion, the stack pointer can be used in the sort indexed mode to access data within te stack. Examples LD

AX,[SP]

PUSH

[SP]

LD

BX,2[SP]

; ; ; ; ;

; copy top of stack into AX (AX)16 <-- ((SP)16)16 duplicate top of stack (SP)16 <-- (SP)16 - 2 ((SP)16)16 <-- ((SP)16 + 2)16 <-copy next to last data on stack into

BX ; (BX)16 <--

((SP)16 + 2)16

Some of the details of these addressing modes are hidden by the assembler language, which simplifies the choice of the correct mode in several aspects : The assembler will automatically choose between register-direct addressing and long-indexed addressing with regster ZERO, depending on where the operand is located in memory. The programmer can simply refer to the operand by its symbolic name. If the operand is within the 256 registers a register-direct reference will be used, if the operand is elsewhere in memory a longindexed reference will be generated.

The assembler will choose between short and long indexing depending on the value of the displacement. If the value can be expressed in 8 bits then short indexing will be used, if cannot then long indexing will be generated.

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Pin diagram of 80196 :

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Memory space Addressable space The addressable memory space of the 80c196 consists of 64k bytes. However, not all these addresses are available to the user. Addresses 0000H through00FFH and 1FFEH through 207FH are reserved for special purposes. All other locations can be used for either program or data storage, or for memory-mapped I/O. FFFFH +-------------------------+ | | | External memory or I/O | | | 4000H +-------------------------+ | Internal ROM/EPROM or | | external memory or I/O | 2080H +-------------------------+ | Reserved | 2040H +-------------------------+ | 8 interrupt vectors | 2030H +-------------------------+ | ROM/EPROM security key | 2020H +-------------------------+ | Reserved | 2019H +-------------------------+ | Chip Configuration byte | 2018H +-------------------------+ | Reserved | 2014H +-------------------------+ | 10 interrupt vectors | 2000H +-------------------------+ | Port 3 and port 4 | 1FFEH +-------------------------+ | External memory or I/O | 0200H +-------------------------+ | 80c196KC internal RAM | 0100H +-------------------------+ | Registers and SFRs | 0000H +-------------------------+ 80c196 addressable space

Registers (internal RAM) Locations 00H through OFFH contain the 232 general registers and the 24 SFRs - Special Function Registers. The RALU can operate on any of these 256 internal register locations, but code cannot be executed from them. If attempt is made to execute instructions from locations 00H through OFFH, the instructions will be fetched from external memory. This section of external memory is generally used by the Intel development tools. Locations 018H through OFFH are the general registers. These locations can be accessed as byte, word ou double-word registers, and can be essentially considered as 232 accumulators. Locations 018H and O19H contain the stack pointer. Operations to the stack cause it to be built down and the stack pointer is pre-decremented, so the stack must be initialized by the user program to 2 bytes above the highest stack location. The stack pointer must point to a word (even) address.

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Special Function Registers (SFRs) Locations 00H through O17H are the I/O control registers or SFRs. All of the peripheral devices of the 80c196 except ports 3 and 4 are controlled through these registers. SFR functions are controlled through 3 windows. Switching between the windows is done using the WSR - Window Select Register located at address 014H. SFR windows other than WSR = 0 are out of the scope of this course. Some of the Special Funtion Registers have different meanings if read from or written to. Reserved memory locations Locations 1FFEH and O1FFFH are used for Ports 3 and 4 respectively. Many reserved and special locations are in the memory area between 2000H and 2080H. The 18 interrupt vectors, the chip configuration byte and the security key are located in this area. All the addresses marked Reserved in this area have to be programmed with value 0FFH. 2080H is the normal program start address. A reset interrupt restarts the program at address 2080H.

External memory There are several modes of system bus operation on the 80c196. The standard bus mode uses a 16bit multiplexed address/data bus. Other bus modes include an 8-bit mode and a mode in which the bus size can be dynamically switched between 8-bits and 16-bits. In addition, there are several options available on the type of bus control signals which make an external bus simple to design. In the standard mode, external memory is addressed through lines AD0-AD15 which form a 16-bit multiplexed bus. The idealized bus timings are represented below :

Standard mode idealized bus timings

The ALE - Address Latch Enable signal provides a strobe for flip-flops (e.g. 74x373s) to demultiplex the bus by latching the address. Demultiplexed address signals will be called MA0-MA15. The data returned from external memory must be on the bus and stable for a specified setup time before the rising edge of !RD (Read). The rising edge of !RDsignals the end of the sampling window. Writing to external memory is controlled with the !WR (Write) pin. Data is valid on AD0-15 on the rising edge of !WR. At this time data must be latched by the external system. In standard 16-bit mode, the external memory is composed of two parallel 8-bit memory banks. Since a given address selects one byte, the 16-bit data bus has to be reconstructed from the low-

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order byte located at the even address, and the high-order byte located at the odd address (see Figure). The !BHE signal is provided for 16-bit bus accesses. Together with MA0, this signal allows to select either the low-order byte, the high order-byte, or both bytes during a 16-bit bus access : Memory bank selection !BHE

A0

selected bank

0

0

high order + low order

0

1

high order only

1

0

low order only

Actually, when a block of memory is decoded for reads only, which is typically the case of EPROMS, the system does not have to decode !BHE and MA0 : the 80c196 will discard the byte it does not need. But for systems that write to external memory, separate write strobes must be generated for both the high and low bytes of memory.

16-bit system with external EPROM

The system above adds 8k-bytes of memory (e.g. a 2764) to a 87c196. This processor already has 8k of internal EPROM, seen at locations 2000H through3FFFH. The system above decodes MA14 to select the external memories, resulting in the microcontroller seeing them at locations 4000H through 7FFFH, just after the internal memory : 15 14 13 12 11 10 X 1 - - - -

9 -

8 -

7 -

6 -

5 -

4 -

3 -

2 -

1 -

0 -

To connect 27128 (16k-bytes) external memories the system should select them with A15 XOR A14 to place them at locations 4000H through 0BFFFH. To connect EPROM to a 80c196, without internal memory, the system is even simpler. The memory chips can be connected without decoding any address line. This means that an 8k-bytes chip will be

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seen at locations 0000H through 03FFFH. However, most of the locations from 0000H through 01FFFH are reserved for internal registers and RAM. This is half of the address space of the memories ! The trick consists in normally programming the upper half of the memories, and programming their lower half (addresses 0000H through 01FFFH) as corresponding to locations 4000H through 05FFFH. Since MA14 is not decoded, when the processor accesses the cells 4000H through 05FFFH the memories are actually selected with an address corresponding to their lower half !

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ARM Microcontroller ARM was developed at Acron Computers ltd of Cambridge, England between 1983 and 1985. RISC concept was introduced in 1980 at Stanford and Berkley. ARM ltd was found in 1990. ARM cores are licensed to partners so as to develop and fabricate new microcontrollersaround same processor cores. ARM Core Architecture Architecture of ARM is Enhanced RISC Architecture. It has large uniform Register file. Employs Load Store Architecture- Here operations operate on registers and not in memory locations. Architecture is of uniform and fixed length. 32 bit processor. It also has 16 bit variant i.e. it can be used as 32 bit and as 16 bit processor.

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Core Data path Architecture is characterized by Data path and control path. Data path is organized in such a way that, operands are not fetched directly from memory locations. Data items are placed in register files. No data processing takes place in memory locations. Instructions typically use 3 registers. 2 source registers and 1 destination register. Barrel Shifter preprocesses data, before it enters ALU. -

Barrel Shifter is basically a combinational logic circuit, which can shift data to left or right by arbitrary number of position in same cycle. Increment or Decrement logic can update register content for sequential access.

ARM Organization

Register Bank is connected to ALU via two data paths. A bus B bus B bus goes via Barrel Shifter. It preprocesses data from source register by shifting left or right or even rotating. The Program Counter is that part of register Bank , that generate address. Registers in register bank are symmetric i.e., they can have both data and address. Program counter generates address for next function. Address Incrementer block, increments or decrements register value independent of ALU. There is an Instruction Decode and control block that provides control signals. (Not in figure)

Pipeline In ARM 7, a 3 stage pipeline is used. A 3 stage pipeline is the simplest form of pipeline that does not suffer from the problems such as read before write. In a pipeline, when one instruction is executed, second instruction is decoded and third instruction will be fetched. This is executed in a single cycle.

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Register Bank ARM 7 uses load and store Architecture. Data has to be moved from memory location to a central set of registers. Data processing is done and is stored back into memory. Register bank contains, general purpose registers to hold either data or address. It is a bank of 16 user registers R0-R15 and 2 status registers. Each of these registers is 32 bit wide.

Data Registers- R0-R15 R0-R12 - General Purpose Registers R13-R15 - Special function registers of which, R13 - Stack Pointer, refers to entry pointer of Stack. R14 - Link Register, Return address is put to this when ever a subroutine is called. R15 - Program Counter Depending upon application R13 and R14 can also be used as GPR. But not commonly used.

In addition there are 2 status registers CPSR - Current program status register, status of current execution is stored. SPSR - Saved program Status register, includes status of program as well as processor.

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CPSR CPSR contains a number of flags which report and control the operation of ARM7 CPU.

Conditional Code Flags N - Negative Result from ALU Z - Zero result from ALU C - ALU operation carried out V - ALU operation overflowed

Interrupt Enable Bits I - IRQ, Interrupt Disable F - FIQ, Disable Fast Interrupt

T- Bit If T=0, Processor in ARM Mode. T=1, Processor in THUMB Mode

Mode Bits Specifies the processor Modes. Processor Modes will be discussed in the next part of this tutorial.

ARM features Barrel Shifter in data path that maximize the usage of hardware available on the chip. Auto increment and Auto decrement addressing modes to optimize program loop. This feature is not common in RISC architecture. Load and Store instruction to maximize data throughput. Conditional execution of instructions, to maximize execution throughput.

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ARM Versions Version 1 (1983-1985) 26 bit addressing No multiply operation No Co-processor Version 2 32 bit Includes result multiplication co-processor Version 3 32 bit addressing Version 4 Added signed and unsigned operations Version 4T (Thumb Mode) 16 bit thumb compressed mode of instruction introduced. Here given the same memory, if 16 bit instruction is used, additional instructions can be packed. Thus code density can be increased. Embedding a 16 bit variant in a 32 bit processor is called a THUMB. Version 5T Superset of 4T adding new instructions

Architecture

Family

Version 5TE Added DSP extension

Examples:-

ARMv1

ARM1

ARMv2

ARM2, ARM3

ARMv3

ARM6, ARM7

ARMv4

StrongARM, ARM7TDMI, ARM9TDMI

ARMv5

ARM7EJ, ARM9E, ARM10E, XScale

ARMv6

ARM11

ARMv7

Cortex

ARM 6- Version 3 ARM 7- Version 3 ARM 7 TDMI- Version 4T (LPC21XX Series of Philips) Strong ARM- Version 4 (intel) ARM 9E-S- Version 5TE

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