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USN

Logic Design Time: 3 hrs.

Max. Marks:100 o'l't

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Note: Answer FIVE fall questions, selecting at least TWO qaestions from each part.

i)

c.

f =; E

1Y

= p(q'+ s)

ii) N = (w'+ x)(y + z)

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(07 Marks)

Reduce the following Boolean function using K-map and realize the simplified expression using NAND gates.

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o PART-A € | a. Define combinational logic. Two motorr VtrarO Mr are controlled by three sensors Sr, Sz and Sl. One motor Mz is to run any time when all three sensors are on. Thggther motor (M1) E E is to run whenever sensors Sz or Sr but not both are on and S3,isl'oif.'' For all sensors combinations where M1 is on, M2 is to be off, except when all sensors are off and then both .H motors remain off. Construct the truth table and write the Boolean output equation. f; g (05 Marks) ., j b. The following Boolean proper function into their canonical decimal notation. form in \$ *'-

-

Simpli\$ the following tunctio, method and realize the simplified i 2 a. using .E gates. NOR ; P=f(w,x,y,z)=I*(2,9,12,13,,,,;14,15)+fa1+,tt; (12Marks) E*

b.

g; SG

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Simplify f(a,b,c,d)=lrn(0,4,s,6,13,14,15)+\d1z,l,g,v1 using MEV technique using basrc Dasrc

3 a.

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gates. gates.

(08 Marks)

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Design a combiuffii circuit to find the 9's complement of a single digit BCD nurnber. (0g Marks) ni."*s#!," r:r *.,r *,jL:r Realize the ci6cu[@sing suitable logic gates. tJof..lp.Sffiagram. 4line for 2 to decoder with an active low encoder enable and active ffiffio\$Ei*riia,,i P-,,.**?* *s'YffrB1tq*,n:te{'"t'ii'ii1;i}'i+e1:i datffifut. Construct a truth table and describe the circuit function with logic symbol .r\st o i ,; (741e?le 's) for the (06 Ntarks) Oesifffa'+ to 16 line decoder using 2 to 4 line decoder which has the active low outputs and H (d EE a.r'Jirh lnrv enahle innrrf Fvnlqin ifs nncrqfinn /o( ac{rye low enaDle E mput. .bxplam lts operatlon. (06 n,{dpr,6\ Marks) FO\s >r (H

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r &*\$ Design a binary full adder using only two input NAND gates. Write a truth table. Implement the following Boolean function using 4 : 1 multiplexer (MUX)

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Y=

C;)

r,

decoder.

. ,9futr c." ^':r(o,B,c.:Dl=fi(r,i;:I,'2,4,O,9r1'2,14) E_E

r

I(4, b,V,D) = Zm(U,

(06 Marks)

(06 Marks)

^'i,?,t2,t4) Define magnitude comparator. Design a two-bit binary comparator and implement with logic gates. (08 Marks)

:

"'u.suitable

5 a.

PART _ B Discuss the difference between a flip flop and latch. Explain the operation of gated SR latch

with a logic diagram, truth table and logic symbol. (06 Marks) Explain the working of Master Slave JK flip flops with functional table and timing diagram. Show how race around condition is overcome. (08 Marks) ,,Qt[ain the characteristic equation of JK and SR flipflops. 1ootvt1ft#*igry, :s 1''

b.

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10ES33

6 a. b.

Describe the block diagram of a MOD-7 twisted ring counter and explain its operation with the count sequence table and decoding logic used to identify the various states. (08Marks) Design a mod-6 synchronous counter using clocked JK flipflops, the count sequence being (l2Marks) 0,2,3,6,5,1,0,2.-.....

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7 a. With a suitable block diagranq explain the Mealy and Moore -od.i,L , J.;iffiJiri'm; analysis.

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b. Expiain 4 bit universal shift Register using 4 : 1 MUX with help of logic diagraprffWiite a mode control table. 6p|ht Marks) 4*r 8 a. Describe the following terms with respect to sequential machines: (ry (06 Marks) i) State ii) Present states iii) Next states. *&* in Fig. Q8 (b). b. A sequential circuit has one input one output. The state diagram 'iqhthwn W (14 Marks) Design a sequential circuit with T flip flops. ffi;

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## Logic Design Jan 2016 (2010 Scheme).pdf

E is to run whenever sensors Sz or Sr but not both are on and S3,isl'oif. ... Simplify f(a,b,c,d)=lrn(0,4,s,6,13,14,15)+\d1z,l,g,v1 using MEV technique using SG E t ...

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