Lei CHEN Analog and Mixed-Signal Center Department of Electrical Engineering Texas A&M University College Station, TX, 77843 E-mail: [email protected]

EDUCATION BACKGROUND Master of Science July 2002 – May 2004 Conferred Degree of Master of Science, by Electrical and Computer Engineering (ECE) Department, National University of Singapore (NUS), Singapore. Graduated with excellent results, converted cumulative average point (CAP) is 3.88 out of 4. B. of Eng with First Class Honor July 1997 – May 2001 Conferred Bachelor of Engineering (First Class Honor), by School of Electrical and Electronic Engineering (EEE), Nanyang Technological University (NTU), Singapore. Graduated as the best student in the circuit and system division in 2001.

WORKING EXPERIENCE Senior IC Design Engineer July 2004 – July 2007 I worked as a Senior IC Design Engineer in Avago Technologies (formerly “Agilent Technologies”) Singapore. I was responsible for designing various analog and mixed-signal integrated circuits (IC) for both industrial and consumer applications. I was also responsible for supervising layout engineers to ensure optimized physical implementation and error-free chip tapeout. Besides, I was involved in bench testing and debugging (if needed) of the designed ICs in laboratory environment. ICs successfully designed, fabricated and marketed include high current, high linearity power line driver, high-speed opto-coupler and high dynamic range logarithmic ambient light sensor. Circuit blocks successfully implemented and verified include Phase-Locked Loop (PLL). R&D Engineer June 2001 – July 2004 I worked as an R&D Engineer in Institute for Infocomm Research, Singapore. My research and development work on major analog and mixed-signal IC blocks are for wireless communication applications. ICs have been successfully design, fabricated and verified include high speed current steering Digital to Analog Converter (DAC), high speed Flash Analog to Digital Converter (ADC) and Gm-C filter. Industrial Attachment Jan 2000 – Jun 2000 Industrial attachment with the Port of Singapore Authority (PSA) Corporation, Singapore.

ACHIEVEMENTS Products • ACPL-0820 (Designed and Tested) Avago’s ACPL-0820 is a high current dual line-driver IC. With a 5 V single supply, it delivers up to 1 APP current. It is ideal for high current differential mode applications such as a Powerline modem. I was fully responsible for the design, bench testing and debugging of the Power Line Driver. The design is silicon proven and first time success. Patent application on the novel architecture of the high drivability, high linearity power line driver is in progress. • APDS-9007 (Designed and Tested) Avago’s APDS-9007 is an ambient light photo sensor with logarithmic current output IC. I was fully responsible for the design, bench testing and debugging of the ambient light photo sensor. The design was silicon proven and first time success. With as low as 2V supply voltage, the sensor achieves more than 5 decades of dynamic range. Stability issue of the Trans-Impedance Amplifier (TIA) with large input signal dynamic range was successfully addressed by a novel implementation. Patent applications on the TIA and the photo sensor architecture are in progress. • HCPL-800J (Tested and Debugged) The HCPL-800J is a galvanically isolated Powerline Data Access Arrangement IC. It provides the key features of isolation, Transmit line driver and Transmit amplifier as required in a powerline modem application. Project Highlights • High Speed Digital Opto-Coupler I was partially responsible for the design, and fully responsible for the layout, testing and debugging of the next generation high speed digital opto-coupler. • Training for Layout Engineers I have successfully trained four fresh layout engineers in Cadence environment. The high speed digital opto-coupler project was used as a training platform. The training includes basic layout techniques in Cadence, component matching, timing and parasitic awareness, DRC/LVS/extraction checks and the whole tape out flow. • Phase-Locked Loop (PLL) I was fully responsible for the design and testing of a very low jitter Phase-Locked Loop (PLL), which is for clock synthesization in a modern opto-coupler system. The design was silicon proven and first time success. Patent application on the modern opto-coupler system is in progress. • 1Gsample/Second 10-bit Current steering Digital to Analog Converter I was fully responsible for the complete DAC circuit design, simulation and layout. True Single Phase Clocked logic was used to meet the high speed, low power requirement, and to eliminate the CLKB signal.

• 2Gsample/Second 6-bit Flash Analog to Digital Converter I was responsible for Thermal-to-Binary code conversion circuit design, simulation and layout. Differential signal logic was used for the high-speed requirement. The design is silicon verified. • 10MHz –3dB Bandwidth 4th-order Gm-C Butterworth Low Pass Filter I was responsible for Transconductor(Gm) cell circuit design and LPF system design, simulation and layout. The design was fabricated, tested and debugged. Improvements were proposed. • 80Msample/Second 10-bit Current steering Digital to Analog Converter I was responsible for digital part and bandgap reference circuit design, simulation and layout. The design is silicon verified and first time success. • PCB Design for DAC, ADC, filter and Phase Locked Loop (PLL) Evaluation I have designed the printed circuit boards and tested the respective ICs.

AWARDS Matsushita Gold Medal 2000/2001 Highest aggregate mark in the four core subjects in final year. The four subjects are ‘E440 Digital Systems’, ‘E441 Electronic Circuit Design I’, ‘E443 Electronic Circuit Design II’ and ‘E444 VLSI Circuits & Systems’. Motorola Book Prize 2000/2001 Best student in the subject ‘E441 Electronic Circuit Design I’ in the final exam. Singapore Power Book Prize 1999/2000 Best student in the subject ‘E305 Power System & Machines’ in third year exam. Dean’s Letter 1999/2000, 2000/2001 Excellent performance in Electrical and Electronic Engineering during academic year1999/2000 and 2000/2001. MOE Scholarship 1997 – June 2001 Ministry of Education (MOE) Singapore scholarship for undergraduate study in Nanyang Technological University (NTU), Singapore.

TOOLS Cadence Schematic & Layout Environment: Hspice and Spectre: DIVA, Dracula, Assura & Calibre: Protel: ADS:

Experienced Experienced Experienced Familiar Familiar

PERSONAL PARTICULARS Languages English, Chinese: Fluent in speaking, writing. Japanese, French: Introductory level. Interests and Hobbies Basketball, swimming and jogging Electronics stuff Acquiring new knowledge in broad areas, such as photography and programming languages Strength A very fast learner Highly self-motivated, highly self-initiative Very open-minded A very responsible team player

REFERENCES Available upon request.