Integrated CMOS Transmit-Receive Switch Using On-Chip Spiral Inductors
A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
Niranjan Talwalkar December 2003
© Copyright by Niranjan A Talwalkar 2004 All Rights Reserved
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I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy.
Simon Wong (Principal Advisor)
I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy.
Thomas Lee
I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy.
G. Leonard Tyler
Approved for the University Committee on Graduate Studies:
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Abstract
The enormous potential of the wireless communications market, the low level of integration of current transceiver implementations, and the rapid advance of low-cost silicon processing technologies, have contributed to the renewed interest in radiofrequency (RF) circuit design in the last decade. RF transceiver designs have made significant progress in the level of integration achieved by implementing most passive components on-chip. Active silicon transistors have reached a sufficiently high level of performance so as to enable the viability of a ‘radio-on-a-chip’. There still remain challenges to achieving that goal. This thesis focusses on the transmit-receive (T/R) switch, which is one transceiver block which has defied integration so far. Modern RF transceiver architectures commonly use a T/R switch to share the use of resources such an antenna. Although Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) characteristics as a switch have dramatically improved over the years, its performance still falls short of the specifications needed in an RF transceiver. This thesis introduces an inductive substrate bias technique that enables the design of T/R switches in a standard silicon complementary metal-oxide-semiconductor (CMOS) process This thesis first describes and analyzes the inductive substrate bias technique which is critical to the performance of the T/R switch. The spiral inductor is a critical component of this
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technique and a new compact model is proposed and verified by simulation and experiment. The spiral inductor model is incorporated in a tool which allows quick synthesis and analysis of spiral inductors across a variety of geometries and substrate dopings. Using the optimized spiral inductors, a T/R switch is designed for 5-GHz applications in a 0.18-µm standard digital CMOS technology. Measurements of the prototype reveal that the switch does meet the targeted specifications. The power handling capability of the switch is 40X higher than other designs reported to date in a CMOS technology. Comparison with simulations suggest that the spiral inductor model developed is indeed accurate. The performance achieved by the switch can be further improved by using better technologies.
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Acknowledgments
Writing this part of the thesis is probably the hardest. Though the list of people to thank is long, making this list is not the hard part. The hard part is finding the words that convey the sincerity and magnitude of my gratitude. People unknown to me till a few years ago, have become a large part of my life, while people I already knew have remained pillars of support and encouragement through these long years. It is with all this help that I stand where I do. My advisor, Prof. Simon Wong, has been primarily responsible for the freedom and timely guidance which I enjoyed during my doctoral studies. I shall be sincerely indebted to him for this. Prof. Tom Lee, my associate advisor, has given me a lot of invaluable feedback on my research and I would like to thank him for that. Prof. L. Tyler has been a wonderful teacher and I am grateful to him for being a reader on my doctoral committee. Prof. Inan and Prof. Cox have ben very generous with their time on my orals committee and I am indeed very thankful for that. Prof. Saraswat has been exceptionally helpful in my stay here at Stanford, during which his door has always been open for me. Special thanks to National Semiconductor Corporation and the Center for Integrated Systems industrial sponsors for funding me and my research. I would like to thank my teachers
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from my previous schools. A special note of gratitude to Prof. R.K. Shevgaonkar whose undergraduate course in Electromagnetism sparked my interest in this field. The Stanford Nano-Fabrication facility staff deserve a lot of thanks for helping me: Jim McVittie, John Shott, Nancy, Mahnaz, Uli, Margaret, Len have all contributed in no small amount to this project. The support of all the CIS staff: Prof. Richard Dasher, Carmen Miraflor, Maureen Rochford, Kate Gibson, Ann Guerra, Rosanna Foster, Joe Little, and Jason Conroy is much appreciated. The largest part of my campus life was dominated by the students and people that I worked with and learned from. I will begin with Richard Chang, who was such a source of knowledge and companionship that one cannot really hope for any better. Pranav Kalavade, Rohit Shenoy, Lalit Nathawad and Shwe Verma have been wonderful friends on this journey. I would like to thank Patrick Yue as a friend and for all the time that he spent advising the Wong-group. I would like to thank my fellow Wong-group members: Haitao Gan, So Young Kim, Frank O’Mahony, Dae-Yong Kim, Chet Soorapanth, Bendik Kleveland, Alvin Loke. I am also grateful to other students and friends at Stanford: Ankur Mohan, Joel Dawson, Ki-Young Nam, Arjang Hassibi, Omer Oralkan, Jeff Hsieh, Caleb Kemere, Talal Al-Attar, Rafael Betancourt, Patrick Chiang, Junfeng Xu, Ting-Yen Chiang and Ken Crozier. I also enjoyed the company of a lot of friends outside Stanford: Srikar, Mohit, Rahul, Vipul, Amit Rao, Amit Jain, Shrinath, Sujat, Ashish, Ganesh who have provided great company for recreational activities. I am very thankful to my in-laws for treating me as their own son and for providing the much needed support. I would also like to thank Alpana who has been the sister I never had. I would like to thank my father, my mother, my brother and his wife who have been there throughout my life and loved me unconditionally despite all my failings. One really could not ask for more and I would like to let them know that I eternally indebted to them. Finally, I would like to say thanks to my wife; the one person to whom I owe this degree most to. I would like to thank her for her patience, her understanding, her encouragement, her kindness, and her love. Tanmay gets a special mention for being so lovable without having to try. viii
Table of Contents
Abstract ................................................................................................................................v Acknowledgments............................................................................................................. vii Table of Contents............................................................................................................... ix List of Tables ................................................................................................................... xiii List of Figures ....................................................................................................................xv List of Acronyms ............................................................................................................. xix Chapter 1 Introduction 1 1.1 Market Background ..............................................................................................1 1.2 Benefits of Integration...........................................................................................2 1.3 RF Switches ..........................................................................................................4 1.4 Dissertation Organization .....................................................................................7 Chapter 2 RF Switches 9 2.1 Introduction...........................................................................................................9 2.2 Switching Devices ..............................................................................................10 2.2.1 MESFET .................................................................................................10 2.2.2 Diode.......................................................................................................12 2.2.3 MOSFET.................................................................................................13 2.2.4 MOSFET with an Inductive Substrate Bias............................................14 2.3 Summary .............................................................................................................17
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Chapter 3 High-Frequency Spiral Inductor Model 19 3.1 Introduction.........................................................................................................19 3.2 Physical Phenomena and Circuit Model for Spirals ...........................................20 3.2.1 Fundamentals of Spiral Inductors ...........................................................20 3.2.2 High-frequency Issues ............................................................................23 3.2.2.1 Electric Field Induced Substrate Loss......................................23 3.2.2.2 Skin and Proximity Effects ......................................................24 3.2.2.3 Magnetic Field Induced Substrate Loss...................................25 3.2.2.4 High-Frequency Equivalent Circuit.........................................26 3.3 Shield Parasitics ..................................................................................................28 3.3.1 Parasitic Capacitance ..............................................................................28 3.3.2 Parasitic Resistance.................................................................................30 3.4 Skin and Proximity Effect...................................................................................32 3.4.1 Skin Effect: Previous Work.....................................................................32 3.4.2 Skin Effect: Modeling.............................................................................32 3.4.2.1 Vertical Skin Effect..................................................................35 3.4.2.2 Total Skin Effect ......................................................................37 3.4.3 Proximity Effect: Modeling ....................................................................41 3.4.3.1 Small Spacing or Large Spacing? ............................................43 3.4.4 Skin and Proximity Effect Summary ......................................................44 3.5 Eddy Current Substrate Loss ..............................................................................44 3.5.1 Modeling Assumptions ...........................................................................44 3.5.2 Substrate Effects in Coplanar Transmission Lines .................................46 3.5.2.1 Loss in Lines of Infinitessimal Cross-section..........................47 3.5.2.2 Width Dependence of Loss .....................................................49 3.5.2.3 Dependence of Loss on Distance from Substrate ....................51 3.5.2.4 Modeling Inductance ...............................................................51 3.5.2.5 Model Verification for Coplanar Lines....................................53 3.5.2.6 Eddy Current Loss in Spiral Inductors.....................................56 3.5.3 Eddy current loss summary.....................................................................57 3.6 Experimental Verification ...................................................................................57 3.6.1 Test Structure Fabrication .......................................................................58 3.6.2 Measurements and Results......................................................................58 3.7 COILS: A New Spiral Inductor Analysis Tool ...................................................63 3.7.1 Need for optimization .............................................................................66 3.8 Summary .............................................................................................................68
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Chapter 4 Transmit-Receive Switch using Inductive Substrate Bias 69 4.1 Introduction.........................................................................................................69 4.2 Integrated T/R Switch Requirements..................................................................71 4.2.1 Performance Metrics for T/R Switches...................................................72 4.2.2 Previous Work.........................................................................................73 4.2.3 Switch Specifications ..............................................................................75 4.3 Circuit Design .....................................................................................................75 4.3.1 Schematic................................................................................................75 4.3.2 Operation.................................................................................................77 4.3.2.1 Transmit Mode.........................................................................77 4.3.2.2 Receive Mode ..........................................................................78 4.3.2.3 ESD Considerations .................................................................80 4.3.3 Layout .....................................................................................................80 4.4 Switch Performance ............................................................................................82 4.4.1 Small-signal Measurements ....................................................................82 4.4.2 Power Handling Capability.....................................................................84 4.4.3 Reliability Testing...................................................................................86 4.4.4 Substrate Cross-talk Results ...................................................................87 4.4.5 Overall Performance Evaluation.............................................................87 4.5 Summary .............................................................................................................90 Chapter 5 Conclusions 91 5.1 Summary .............................................................................................................91 5.2 Future Work ........................................................................................................93 5.2.1 Improvements in T/R Switch Performance.............................................93 5.2.2 Other Applications for the Inductive Substrate Bias Technique.............93 5.2.3 Inductor and Transformer Modeling.......................................................94 5.2.4 Large Signal MOSFET Modeling at RF.................................................95
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Appendix A
97
Appendix B
101
Appendix C
105
Bibliography
109
xii
List of Tables
Table 3.1: Table 3.2: Table 4.1: Table 4.2: Table 4.3:
Spiral inductor test structure matrix. .......................................................58 Optimized geometries for a 3-nH spiral inductor in Epi and Bulk processes..................................................................................................67 Target specifications for the T/R switch. .................................................75 Comparison of simulation and measured results for the T/R switch.......89 Comparison of this work to commercially available board-level components..............................................................................................89
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List of Figures
Figure 1.1: Figure 1.2: Figure 1.3: Figure 1.4: Figure 2.1: Figure 2.2: Figure 2.3: Figure 2.4: Figure 2.5: Figure 2.6: Figure 3.1: Figure 3.2: Figure 3.3: Figure 3.4:
Worldwide penetration percentage for cellular telephones (2000). ......2 Simple RF transceiver architectures (a) Heterodyne or IF-based, and (b) Homodyne or direct downconversion. .............................................5 A highly integrated 5-GHz transceiver in 0.25-µm, 6-metal, Aluminium, standard CMOS. ................................................................6 Switching applications in RF circuits (a) switching capacitors (b) switching inductors. ...............................................................................7 Circuit to determine the quality of an RF switch. ...............................10 Simplified GaAs MESFET cross-section and physical origin of main RF equivalent circuit elements (after Sze [11], pp. 342) .....................11 Simplified MOSFET cross-section and physical origin of main RF small-signal equivalent circuit elements. .............................................14 MOSFETs with inductive substrate bias. ............................................15 Effect of inductive substrate bias on linearity of a pass-gate MOSFET with Rsource = Rload = 50 Ω. .................................................................16 On-resistance trade-off with off-state capacitance is better by about 30% for source-grounded MOSFETs with inductive substrate bias....16 Scanning electron micrographs of a 7-turn square spiral inductor. . ...20 Generation of a simple circuit model for the spiral inductor. .............22 Physical mechanism of electric field based substrate loss. .................24 Preventing electric field based substrate loss by terminating the electric field using a PGS..................................................................................24 xv
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Figure 3.5: Figure 3.6: Figure 3.7: Figure 3.8: Figure 3.9: Figure 3.10: Figure 3.11: Figure 3.12:
Figure 3.13: Figure 3.14: Figure 3.15: Figure 3.16: Figure 3.17: Figure 3.18: Figure 3.19: Figure 3.20: Figure 3.21: Figure 3.22: Figure 3.23: Figure 3.24: Figure 3.25: Figure 3.26: Figure 3.27: Figure 3.28:
Relevant high-frequency effects in spiral inductors and their relationship to the circuit model. .........................................................27 Equivalent circuit model for a spiral inductor with PGS with frequency dependent circuit parameters for the relevant high-frequency effects. 27 Geometric parameters of a square spiral inductor. ..............................28 Top view for PGS layout with polysilicon fingers and metal-1 straps.29 PGS parasitics. ....................................................................................31 Induced voltages on the shield are equal and opposite implying that the net mutual inductance between PGS and the spiral is very small........31 Field profiles for a plane wave normally incident on a metal surface. 34 Field profiles for a wave propagating along the z-direction in a parallel-plane waveguide with finite metal conductivity and finite lateral dimensions. ..........................................................................................34 Vertical and lateral current density non-uniformities in a current carrying conductor. ..............................................................................35 Cross-section for simulation and analysis of vertical skin effect. .......36 Comparison of models for vertical skin effect in copper. ...................36 Comparison of vertical skin effect model vs. simulation in copper for different thicknesses. ...........................................................................37 Cross-section for simulating total skin effect. .....................................38 Modeling lateral skin effect. ................................................................39 Comparison of total skin effect ac resistance model to 2-D simulation results for different thicknesses in copper. ..........................................40 Comparison of total skin effect ac resistance model to 2-D simulation results in copper for different widths. .................................................40 Different types of proximity effects in spiral inductors. ......................41 Cross-section for simulating proximity effect of two signal lines. ......42 Proximity effect model comparison to 2-D simulations in aluminum.42 Effect of turn-to-turn spacing on inductor performance in copper for two widths. .................................................................................................43 Ground return current flow for (a) Coaxial line and (b) signal line over substrate. .............................................................................................46 Substrate current flow for a coplanar transmission line for different frequencies. .........................................................................................49 Substrate currents for signal and ground lines of width W, where P-W > 2δsub. ........................................................................................50 Mutual coupling between signal/ground lines and the image eddy
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Figure 3.29: Figure 3.30: Figure 3.31: Figure 3.32: Figure 3.33: Figure 3.34: Figure 3.35: Figure 3.36: Figure 3.37: Figure 3.38: Figure 3.39: Figure 3.40: Figure 3.41: Figure 3.42: Figure 3.43: Figure 3.44:
Figure 3.45: Figure 4.1: Figure 4.2: Figure 4.3: Figure 4.4: Figure 4.5: Figure 4.6: Figure 4.7:
currents in the substrate. .....................................................................52 Effect of substrate doping on resistance and inductance of coplanar transmission lines. ...............................................................................54 Effect of separation on resistance and inductance of coplanar transmission lines.................................................................................54 Effect of separation from the substrate, h, on resistance and inductance of coplanar lines...................................................................................55 Effect of changing width of signal and ground lines on resistance and inductance. ...........................................................................................55 Decomposition of a single turn spiral inductor into two coplanar transmission lines.................................................................................56 Modeling the multi-turn spiral as a single turn inductor of effective 56 width Weff. Spiral inductor cross-section showing the various layers. ..................57 Effects of increasing substrate conductivity on Q. .............................60 Effect of substrate doping for a 10-nH inductor at lower frequencies.60 Model performance with respect to geometry for (a) Lightly doped sample, K2, and (b) Heavier doped sample, M2. ................................61 Effect of epi vs. non-epi substrate dopings on (a) Effective resistance, and (b) Effective inductance. ...............................................................62 Modeling error for peak-Q across all splits and geometries (145 samples). ..............................................................................................63 Web-based spiral inductor tool user interface......................................64 Main web page for spiral inductor synthesis/analysis tool. ................65 Bulk substrate web page for spiral inductor tool. ...............................66 Predicted performance of optimized 3-nH inductors in epi, ρsub1 = 10 Ω-cm, and bulk, ρsub2 = 0.01 Ω-cm, technologies differing only in substrate doping. ......................................................................67 Comparison of performance of two 3-nH inductors in an epi process.68 Sample RF superheterodyne architecture [4]. .....................................69 A radio front-end block diagram showing the integration of the T/R switch and matching networks. ...........................................................70 Simplified schematic of a T/R switch. .................................................71 Simplified schematic of a diode based T/R switch. ............................73 A ‘series-shunt’ T/R switch topology using FETs. .............................74 Schematic for the CMOS T/R switch operating at 5.2 GHz................76 Simplified small-signal equivalent circuit in transmit mode. ..............77 xvii
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Figure 4.8: Figure 4.9: Figure 4.10: Figure 4.11: Figure 4.12: Figure 4.13: Figure 4.14: Figure 4.15: Figure 4.16: Figure 4.17: Figure 4.18: Figure 5.1:
Simplified small-signal equivalent circuit during receive mode with a 50-Ω termination for the Tx port. ........................................................79 Proposed schematic for LNA input impedance less than 50 Ω............79 Die micrograph of CMOS T/R switch. ...............................................81 S-parameter measurement setup for IL, isolation and return loss in the Tx mode. ..............................................................................................82 Measured S-parameters and isolation in the transmit mode. ...............83 Measured S-parameters and isolation in the receive mode..................83 Linearity measurement setup in the Tx mode. ....................................84 Measured linearity of T/R switch in Tx and Rx modes. ......................85 Measured isolation under high input powers up to P1dB in Tx and Rx modes. .................................................................................................85 Simulated voltage waveforms for M1 in Tx mode with Pin = 27.5 dBm and Pout = 25.8 dBm. ...........................................................................86 Substrate crosstalk measurements. ......................................................88 VCO using switched capacitors, C1 and C2, to increase tuning range. Devices M3 and M4 can use the inductive substrate bias technique to enhance performance. ..........................................................................94
xviii
List of Acronyms
CMOS DUT ESD GaAs HBM IC IF IL ILD ISO ISS LNA MESFET MEMS MMIC MOSFET PA PEEC PCB PGS
Complementary-Metal-Oxide-Semiconductor Device Under Test Electrostatic Discharge Gallium-Arsenide Human Body Model Integrated Circuit Intermediate-Frequency Insertion Loss Inter Layer Dielectric Isolation Loss Impedance Standard Substrate Low-Noise Amplifier MEtal-Semiconductor-Field-Effect-Transistor Micro-Electro-Mechanical-System Monolithic-Microwave-Integrated-Circuit Metal-Oxide-Semiconductor-Field-Effect-Transistor Power Amplifier Partial-Element-Equivalent-Circuit Printed Circuit Board Patterned Ground Shield
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PIN RF RFC SAW SEM T/R VCO WLAN
P-type - Intrinsic - N-type Radio-Frequency Radio-Frequency Chokes Surface-Accoustic-Wave Scanning-Electron Micrograph Transmit-Receive Voltage-Controlled Oscillator Wireless-Local-Area-Networks
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Chapter
1
Introduction
The interest in low-cost, low-power, silicon-based transceiver designs for radio-frequency (RF) applications, such as cellphones and wireless networking, has prompted research in wireless circuit design techniques using complementary-metal-oxide-semiconductor (CMOS) technology. A critical limitation in obtaining fully integrated CMOS wireless systems is the lack of high quality switches. Consequently, new techniques are required to overcome this problem. This chapter presents the economic and technological motivation behind this drive for integrated CMOS switches. The chapter begins with an overview of the status and trends of wireless communications and technology. The role of switches in RF circuits is illustrated with examples. The impact of having ‘on-chip’ switch designs on the ultimate goal of wireless system-on-a-chip is discussed. Finally, the last section outlines the organization of the dissertation.
1.1 Market Background Cellular telephones and wireless-local-area-networks (WLAN) are the two major markets for wireless devices. Cellular telephones have enjoyed enormous growth in the last decade. The total number of cellphone users, in June 2002, is estimated to be over a billion according to the Global Mobile Subscriber database [1]. The Asia-Pacific market was the largest in 2002 with about 380M1 users. Western Europe and North America followed with 300M and 150M respectively. Figure 1.1 shows the worldwide penetration of the cellphones in mid 2001. The small worldwide average of penetration percentage for
1. M = Million
1
Chapter 1: Introduction
2
cellphones indicates that there is significant room for growth. As prices of cellphones continue to drop, these numbers, especially in Asia, will continue to rise. New standards, such as 2.5G and 3G, have been introduced to allow additional cell phone functionality such as internet access, and live video, etc. Wireless solutions are especially attractive for countries where the infrastructure associated with wired telephony is weak or expensive to
Penetration Percentage
modernise.
100 80 60 40 20 W. Europe
USA
Japan
China
Rest
Total
Figure 1.1: Worldwide penetration percentage for cellular telephones (2001).
In the last decade, optical fiber transmission capcity has increased by a factor of 200 [2]. Close on the heels of an enormous increase in wired data bandwidth, a similar increase in the wireless data bandwidth is expected. The WLAN market has picked up in the last couple of years with greater consumer demand for wireless connectivity. Standards such as 802.11 a, b, and g2 have been designed to permit large data rates for high speed internet access.
1.2 Benefits of Integration Both, the cellphone and the WLAN, markets, suffer from the lack of low-cost and low-power wireless access devices. Increasing the level of integration 3 is an effective
2. http://grouper.ieee.org/groups/802/11
Chapter 1: Introduction
3
solution to this problem. CMOS is the preferred technology as aggressive scaling of MOS devices has permitted progressively higher levels of integration. High-frequency (> 1 GHz) MOS device performance has improved to the point where an integrated RF transceiver composed of an RF front-end and baseband on the same piece of silicon can be envisioned. This was predicted by Meyer [3] and Larson [4] almost 8 and 5 years ago, respectively. The availability of low-cost CMOS technology through many foundries has also contributed to the popularity of integrated solutions. Integrating the RF front-end on the same piece of silicon has several other advantages: - The number of board-level passive components and ICs drops with increased integration. This reduces the overall cost of assembly and parts. - Significant power savings can be expected since signals need not travel long distances on and off the chip, and board-level parasitics such as IC packages and PCB traces need not be driven. - Form-factor reduction is key to hand-held portable electronics. - Single-chip solutions are potentially more reliable when compared to board-level solutions. The variability of performance also decreases across process corners and temperature since tolerances for integrated devices are typically tighter than the discretes. - Specific to RF blocks, an integrated solution does not need a matching impedance of 50 Ω between blocks. All the above benefits result in significant improvement in design, power, optimization, flexibility and performance metrics.
3. In the IC industry, ‘level of integration’ implies the number of system components integrated on a single piece of silicon.
Chapter 1: Introduction
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1.3 RF Switches A sample heterodyne RF transceiver front-end is shown in Figure 1.2(a). In this architecture, the received RF signals are first passed through a bandpass filter, and then switched to a low-noise amplifier (LNA). Due to its gain, the LNA essentially sets the signl-to-noise ratio for the receiver chain. The amplified signals are filtered for improved image-rejection and downconverted to an intermediate frequency (IF) with a mixer. The signals at IF are then filtered for channel-selection and shifted in frequency to baseband by a second mixer. The transmission process is complementary to the reception process. During transmission, the signals at baseband are upconverted to the RF carrier using an IF stage. A power amplifier (PA) is used to drive the antenna. A transmit-receive (T/R) switch is used to connect/disconnect the antenna for the transmit and receive processes. The direct downconversion or homodyne architectures mix the incoming RF signals with the carrier frequency to generate signals directly at baseband as shown in Figure 1.2(b). Similarly, the signals are directly upconverted to the RF carrier using only one mixing step during transmission. The IC-design industry is increasingly looking at direct downconversion architectures to facilitate further integration by reducing the number of components required. The die-photo of a heavily-integrated 802.11a transceiver IC [5] is shown in Figure 1.3. This architectures uses standard CMOS technology and includes a LNA and PA on the same piece of silicon. Highly-integrated transceiver solutions for the 802.11b,g standards have also been presented by Chien[6] and Kluge[7]. As indicated previously in Figure 1.2, several key blocks still cannot be integrated. Amongst these blocks, the T/R switch stands out as a candidate for on-chip integration because the MOSFET device is optimized to operate as a switch. Despite the improved switching performance of the MOSFET due to scaling, the performance of integrated CMOS T/R switches falls significantly short of the transceiver requirements. In general − to date − performance of MOSFETs as a RF switches is found to be unsatisfactory.
Chapter 1: Introduction
5
LNA Antenna
Rx T/R Switch
Band Pass Filter
RF Mixer
Image Reject Filter Frequency Synthesizer
Frequency Synthesizer
I Q
φ
o φ+90
Baseband I/Q Signals
ωLO = ωRF + ωIF LC Filter
Tx PA
Buffer
Typical off-chip blocks
Rx T/R Switch
Band
SSB Mixer
I IF Mixer Bank
Q
(a) LNA
Antenna
IF Mixer Bank SAW Filter
Mixer Bank
Image Reject Filter
I Q
Frequency Synthesizer
Pass Filter
φ
o φ+90
Baseband I/Q Signals
ωLO = ωRF I Tx PA
Figure 1.2:
Buffer
Mixer Bank
Q
(b)
Simple RF transceiver architectures (a) Heterodyne or IF-based, and (b) Homodyne or direct downconversion. The component count is significantly lower for homodyne systems (after B. Razavi [8]).
RF switches can be used in several places in RF front-ends. In a T/R switch, a two-pole single-throw arrangement of switches multiplexes the use of the antenna between the PA and the LNA. T/R switches must have a high linearity to ensure that the high power signals (~2 W) at the output of the PA are transmitted to the antenna with minimum distortion. This linearity requirement presents a serious challenge in integrating T/R switches into on-chip designs especially as the supply voltage in standard CMOS continues to decrease.
6
4.6 mm
Chapter 1: Introduction
Figure 1.3: A highly integrated 5-GHz transceiver in 0.25-µm, 6-metal, Aluminium, standard CMOS. The transceiver includes a low-noise amplifier and power amplifier but excludes the T/R switch. (D. Su [5])
In addition to the T/R switch application mentioned above, RF switches could be used to select capacitors, Figure 1.4(a), e.g., tuning of a voltage-controlled oscillator (VCO). In this application, the challenge is to obtain a low on-resistance and a low off-state capacitance. A similar problem is encountered while switching inductors, Figure 1.4(b), in and out of operation. The on-resistance must be low enough that the quality of inductor, when switched in, is not significantly degraded by the presence of a series resistance element. At the same time, the off-state capacitance must be low enough to ensure that the series resonance with the inductor, when it is switched out, does not affect the performance of the rest of the circuit. In a given technology, the on-resistance and off-state capacitance are inversely related to each other. Since the resistance-capacitance product in a modern CMOS technology is not as low as desired, a T/R switch designed using a MOSFET as a switching element results in inferior performance.
Chapter 1: Introduction
7
Cswitched
Parasitic drain capacitance
Lswitched
Parasitic drain capacitance
Switch device
(a)
Switch device
(b)
Figure 1.4: Switching applications in RF circuits (a) switching capacitors (b) switching inductors. For these applications, a switch with a low on-resistance and low off-state parasitic drain capacitance is desired.
1.4 Dissertation Organization This dissertation aims to understand the limitations of existing RF switches and to investigate new ways of designing RF switches − with improved performance − in conventional silicon IC technology. Chapter 2 presents the various types of switches used in RF circuits and discusses the detailed specifications that integrated switches need to meet to present if they are to present a serious alternative to the existing board-level switch designs which use gallium-arsenide metal-semiconductor-field-effect-transistors (GaAs MESFETs) or PIN diodes. Chapter 2 then proposes a narrowband alternative using a MOSFET whose substrate is biased using inductors. This technique is referred to as the ‘inductive substrate bias technique’. The focus of Chapter 3 is the modeling of inductors, which are critical components of the proposed narrowband switch. High-frequency phenomena that degrade inductor performance such as inductive and capacitive coupling,
Chapter 1: Introduction
8
skin depth issues, skin/proximity effects and eddy current effects in the substrate are modeled and characterized in detail using simulation and experiment. Using the optimized models, the design, fabrication and measurements of an integrated T/R switch is presented in Chapter 4. The measured results are compared to the existing board-level alternatives in the market. Lastly, conclusions and future work are summarized in Chapter 5. Mathematical details of inductor modeling calculations are presented in the Appendix.
Chapter
2
RF Switches
2.1 Introduction In predominantly analog wireless transceivers, low-loss switches are very important in several applications. Two types of switching functions are needed in a transceiver. The first type requires the switch to be operated continuously by rapidly turning it on and off at the radio-frequency, e.g., in a mixer. Such a switch can be designed using typical scaled MOSFETs because the signal levels are low and limited by the supply voltage, Vdd. In the second type of function, the switch is left in one state, on or off, for long intervals, ~1 ms, before it is switched to the other state. The main requirement of such a switch is that it must present very low on-resistance in the conducting mode for a large range of signal amplitudes, which could be higher than Vdd, and provide a high degree of isolation when turned off. We consider only the second category of switches in this research. Such high performance switches are required for the purposes of multiplexing access to shared resources in the wireless system. RF switches can be implemented electronically using either integrated on-chip CMOS transistors or board-level components which use GaAs MESFETs or PIN diodes. Micromachining provides new alternatives such as RF micro-electro-mechanical-systems (MEMS) [10], but integration and reliability challenges have prevented these solutions from being adopted. The details of each of these switches, and their benefits and limitations are presented in this chapter. Finally, we explain the ‘inductive substrate bias technique’ to improve the RF performance of an on-chip CMOS switch.
9
Chapter 2: RF Switches
10
2.2 Switching Devices In digital applications, a switching device is characterized by metrics such as its switching time, and input capacitance, etc. For RF applications, a switching device is commonly characterized with the help of the circuit of Figure 2.1. When the switch is closed and the circuit is complete, some power is lost in the switch due to its imperfections. This loss is commonly referred to as the insertion loss (IL) of the switch. In the closed-state, the linearity of the switch is specified by its one dB compression point1. In the open-state, the signal attenuation provided by the switch is known as the isolation (ISO) of the switch. Insertion loss, linearity, and isolation are the key metrics of an RF switch. Additionally, the switch must provide good input and output matching besides ensuring reliable operation at high powers.
Rsource = 50Ω
Vsource
DUT
Rload = 50Ω
Figure 2.1: Circuit to determine the quality of an RF switch. The switch is connected in series with a 50-Ω RF source and a 50-Ω load resistance. Losses in the switch and its linearity are measured when the switch is closed while its isolation performance is tested with the switch open.
2.2.1 MESFET MESFETs are majority carrier devices which makes them suitable for high speed operation [11]. They can be implemented using silicon, GaAs, InP, and as
1. The input power for which the insertion loss drops by one dB over the insertion loss at very low input powers is referred to as the one dB compression point.
Chapter 2: RF Switches
11
heterostructures. MESFETs implemented in silicon are incapable of handling large powers and typically are slower than those implemented using the other materials. MESFETs implemented using GaAs are commonly used for high-power (> 1 W) and high-frequency (> 1GHz) applications. GaAs has a large bandgap, and hence a large breakdown voltage that permits high-voltage operation without reliability concerns. Moreover, the high low-field mobility of GaAs enhances the usable bandwidth of the device. GaAs MESFETs also use a semi-insulating substrate which further lowers loss in the device. The performance of GaAs switches is found is be excellent in practice, as shown in Chapter 5. GaAs MESFET switches achieve a very low insertion loss of about 1 dB and high-power capability. Research is now being carried out to develop high-speed, low-loss switches using heterostructures [12][13].
GATE
SOURCE
DRAIN
RG
RS
Rf
CGD
CGS RDS
RD
CDC
CDS
Semi-insulating GaAs Figure 2.2: Simplified GaAs MESFET cross-section and physical origin of main RF equivalent circuit elements (after Sze [11], pp. 342)
Chapter 2: RF Switches
12
For the design of a GaAs MESFET, the main trade-off is between its on-resistance and off-state capacitance. In order to achieve a low insertion loss, a large device with a low on-resistance can be used. Tthis degrades the isolation performance since the off-state capacitance, CDS in Figure 2.2, will be large. A narrowband technique which places an inductor in parallel with the device that resonates with the off-state capacitance at the frequency of operation, could be used to improve isolation performance. Another limitation of GaAs MESFET switches is their power handling capability, as compared to PIN diodes, when low control voltages are used. In order to get around this limitation, switches using stacked gates, LC-resonators [14], feed-forward capacitors [15], and combination of these have been proposed. An important thing to note is that GaAs FET switches, unlike PIN diodes, do not consume static power, which makes them attractive for low-power hand-held wireless communication devices. An important limitation is that they cannot be integrated with silicon-based transceivers.
2.2.2 Diode Diodes are widely available in CMOS technologies and also as discrete components. PN-junction diodes found in standard CMOS, however, have a low breakdown voltage fo about 10 V and are unsuitable for controlling large signal swings. Consequently, discrete PIN diodes have been used for high-power RF switches. In the on-state, the diode is biased using a large current of about 10 mA which ensures that the ac resistance is low. In the off-state, the PIN structure has a low junction capacitance which ensures a large isolation. PIN diodes can be fabricated in silicon, GaAs, or even using heterostructures. While PIN diodes show excellent insertion loss (< 1dB) and power handling (> 5 W) up to very high frequencies, their static power consumption due to the bias current remains a severe limitation. PIN diodes have been demonstrated with a low on-resistance for a low current bias using InP heterostructures [16]. It is possible to design switches with low static power consumption using an asymmetric design with LC-resonators [17]. Since a large bias current is typically required for switch operation, it must be supplied through a choke. Since integrating chokes on silicon is technologically challenging,
Chapter 2: RF Switches
13
monolithic-microwave-integrated-circuits (MMICs) with integrated chokes using PIN diode switches are rarely found. Due to limitations of static power consumption and the absence of MMIC diode switches − despite superior performance − diode switches are being gradually replaced by GaAs MESFET MMICs, which offer only slightly worse performance for significantly lower static power consumption.
2.2.3 MOSFET The MOSFET is the cheapest of all the switch options. It is available in a CMOS process and its performance improves every generation. Only silicon-based MOSFETs, however, are viable due to the absence of a good gate insulator for other materials. The on-resistance of a silicon MOSFET is significantly worse than a GaAs MESFET due to poor electron and hole channel-mobilities at low electric fields. Modern technology offers very small channel length MOSFETs with a good R on x C off product. The thin gate dielectric and small channel length, however, permit a low-voltage operation only. These switches cannot be used for high-power RF applications. The typical performance of MOSFET switch at RF is poor compared to its GaAs and PIN diode counterparts. Figure 2.3 shows the small-signal equivalent circuit of the MOSFET for RF applications. The channel resistances, RC1 and RC2, and the substrate resistances, RB1, RB2, and RB3, are the main sources of loss in the MOSFET. The substrate resistance, RB3, may be reduced by grounding the substrate as close to the device as possible. The low quality factor of the source and drain parasitic junction capacitors, C SB and C DB , (Q ~ 10−20 @5 GHz) can also lead to significant losses, especially as the frequency of operation increases. The linearity of the MOSFET switch is limited for large signal swings due to conductivity modulation caused by a changing gate-source (Vgs) and drain-source (Vds) voltage for a large-signal input. Another cause of non-linearity is the parasitic source and drain junction diodes which can clip the signal at about 0.7 V above the power supply or 0.7 V below ground
Chapter 2: RF Switches
14
GATE
SOURCE
DRAIN BULK
RG COX
n+
RC1 CSB
RB1
n+
RC2 RB2
CDB
p+ RB3
P-Well Figure 2.3: Simplified MOSFET cross-section and physical origin of main RF small-signal equivalent circuit elements.
2.2.4 MOSFET with an Inductive Substrate Bias In order to increase the linearity of the MOSFET switch, the gate is often biased using a large resistor. At RF, the gate becomes a floating node. The gate voltage is bootstrapped to the source/drain voltages and Vgs remains approximately constant. The source/drain junction diodes can still turn on and distort the incoming signal for large voltage swings. With the source/drain diodes turned on, the bootstrapping fails and trans-conductance modulation sets in leading to further signal distortion. Concerns of latch-up prevent biasing the substrate through a large resistor to float it in a fashion similar to that of the gate. Floating the substrate at RF is possible if the substrate is biased to ground or Vdd through an inductor as shown in Figure 2.4(a). This is referred to as the inductive substrate bias technique. The inductor presents a high impedance at RF, effectively floating the substrate node. The inductor now appears in series with the source/drain diodes with
Chapter 2: RF Switches
15
respect to ground. If a positive or negative voltage appears across the diode-inductor pair, the high impedance of the inductor in series with the diode will permit only a small amount of current to flow through it. This prevent the source/drain diode turn-on from distorting signals. At the same time, latch-up is avoided as it is a much slower event with a time-constant of several nanoseconds. For the latch-up transient, the inductor presents a low impedance and grounds the substrate node effectively. Since on-chip inductors are accompanied by large parasitic capacitors, it is hard to obtain good quality integrated RF chokes. Therefore, the inductive substrate bias technique is modified to include a capacitor in parallel with the inductor, such that LC-tank resonates at the operating frequency. A schematic of a MOSFET with this modified inductive substrate bias is shown in Figure 2.4(b). This tank has the same effect of floating the substrate as discussed above, albeit in a narrow frequency range. This is acceptable since most RF circuits are narrowband.
Source / drain junction diodes Substrate resistance
(a) (b) Figure 2.4: MOSFETs with inductive substrate bias. (a) An inductor is used to bias the substrate node to ground. (b) Due to limitations of obtaining an integrated inductor of large value (~100 nH) a narrowband version using an LC-tank may be used for on-chip applications.
Chapter 2: RF Switches
16
30 w/ Inductive substrate bias
Pout (dBm)
25 w/o bias
20
W/L = 200µm/0.18µm
15 15
20
25
30
Pin (dBm)
Cdrain (fF)
Figure 2.5: Effect of inductive substrate bias on linearity of a pass-gate MOSFET with Rsource = Rload = 50 Ω. The gate is biased to Vdd through a 10 KΩ resistor.
w/o bias
100 w/ inductive substrate bias
30% improvement
10 1
10 Ron (Ω)
Figure 2.6: On-resistance trade-off with off-state capacitance is better by about 30% for source-grounded MOSFETs with inductive substrate bias.
Chapter 2: RF Switches
17
A MOSFET may be used as a switch in RF transceiver circuits in one of two ways. Case(a): Pass-gate configuration − The main requirements here are a low-loss, high-linearity, and high-isolation design. Using the circuit of Figure 2.1, a simulation was carried out to compare the linearity of a MOSFET in the pass-gate configuration, with and without inductive substrate bias. The simulated linearity of the MOSFET with an inductive substrate bias is significantly improved as seen from Figure 2.5. An added benefit is that since the parasitic junction diodes are connected to the high impedance substrate node, their capacitance no longer affects the RF signals. Case(b): Source-grounded configuration − Such a switch is commonly employed to switch capacitors or inductors in and out of circuits as shown in the previous chapter in Figure 1.4. The main requirements for such applications are a low on-resistance and a low off-state drain capacitance. The performance of MOSFET with an inductive substrate bias is better by about 30% as seen from Figure 2.6. In the off-state, the quality factor of the drain capacitor is greatly improved as the capacitive current no longer flows to ground through the substrate resistor. Instead, its flows from the drain terminal to ground primarily through the two back-to-back diodes formed by the drain-substrate and substrate-source junctions. This path has low loss due to the close physical proximity of the source-drain junctions.
2.3 Summary RF CMOS holds great promise as a solution to the low-cost, low-power requirements of modern wireless circuits. High quality RF switches, however, are not easily obtained in modern CMOS technology due to low carrier mobility in silicon. Simulations indicate that MOSFETs with inductive substrate bias can play a significant role in improving the performance of switches in integrated transceivers. This technique can increase the linearity of a MOSFET in the pass-gate configuration substantially, while in the source-grounded configuration, it can offer 30% reduction of off-state capacitance. In the
Chapter 2: RF Switches
18
remaining chapters, the inductive substrate bias technique is extensively studied by careful characterization of its components and measurement results of an RF T/R switch fabricated using a commercial CMOS process.
Chapter
3
High-Frequency Spiral Inductor Model
3.1 Introduction Inductors are critical components of RF wireless circuits. Improvements in technology such as the increase in the number of metals, the use of copper metallization, and the use of dielectrics with reduced permittivity have improved the quality of on-chip inductors. Despite these enhancements, a variety of phenomena degrade the performance of on-chip spiral inductors at high frequencies. Typical spiral inductor analysis tools use computationally intensive techniques such the ‘partial element equivalent circuit’ (PEEC) method [18] or finite element solutions of Maxwell’s equations [19]. A physics-based equivalent circuit model, also known as a compact model, which captures the principal phenomena that affect the performance of the spiral at high frequencies, is very desirable for fast and accurate circuit simulation as well as inductor optimization. Apart from its utility for studying the inductive substrate bias technique proposed in the previous chapter, such a model has applications in the simulation of integrated wireless designs. In this chapter, a physics-based simplified circuit model, which includes all the main physical phenomena that affect its performance at frequencies up to 20 GHz, is presented for the spiral inductor. The chapter begins with a description of the relevant physical phenomena. This is followed by detailed characterization and modeling of each of the effects. Each of the phenomena is modeled to obtain simple expressions for elements of the equivalent circuit. This circuit mimics the behavior of the spiral at high frequencies for narrowband applications. The circuit model is verified using simulations and experiment.
19
Chapter 3: High-Frequency Spiral Inductor Model
20
This work is consolidated in a web-based modeling tool, which enables quick synthesis and analysis of integrated spiral inductors in different technologies.
3.2 Physical Phenomena and Circuit Model for Spirals 3.2.1 Fundamentals of Spiral Inductors Several choices are available for implementing an on-chip inductor, of which the spiral inductor gives an optimal combination of performance and control. Spiral inductors are commonly designed by placing metal in a planar spiral configuration. The two ends of the spiral are the terminals of the inductor. A scanning electron micrograph (SEM) of a square spiral inductor with 7 turns, an outer diameter of 300 µm, turn-width of 13 µm, and 7 µm spacing between turns is shown in Figure 3.1.
Terminal 1 Terminal 2 13 µm 7 µm
Figure 3.1:
300 µm
Scanning electron micrographs of a 7 turn square spiral inductor. The spiral has an outer diameter of 300 µm, turn-width of 13 µm and a turn-to-turn spacing of 7 µm.
The quality of such spirals is degraded due to processing limitations which give rise to the presence of parasitics. Figure 3.2 shows the physical basis of the most commonly used
Chapter 3: High-Frequency Spiral Inductor Model
21
equivalent circuit for modeling the spiral inductor on a doped substrate. Figure 3.2(c) is a simplified circuit model derived from Figure 3.2(b). The inductance, Ls, can be computed from the formulae given by Grover [20] or Greenhouse [21]. The dc series resistance value, Rs, is computed by using technology parameters such as metal sheet resistance. The parasitic capacitances, C p and C s , are computed by calculating area and fringe components of the spiral. Simple formulae for calculating the geometry dependent values for these circuit elements of the equivalent circuit can be found in [23]. The quality factor, Q, is a common figure of merit for spiral inductors, and is often defined as the ratio of the imaginary to the real part of the impedance of the spiral1 with one of its terminals connected to ground. Using Figure 3.2 (c), Q can be shown to be given by (3.1) for a spiral on a doped substrate. 2
ωL s Rp Rs ( C s + C p ) 2 - ⋅ 1 – ------------------------------– ω Ls ( C s + C p ) Q = ---------- ⋅ ------------------------------------------------------------2 R s R + [ 1 + ( ωL ⁄ R ) ]R Ls p s s s Substrate – l oss factor
(3.1)
Self – r esonance factor
In order to maximize Q, a few observations can be made from (3.1): 1. Using thicker metal or using a metal with greater conductivity (e.g., copper, silver, gold) improves inductor Q by reducing Rs. 2. Placing the inductor as far from the substrate as possible minimizes Cp and enhances the self-resonance factor. 3. Doping the substrate very lightly or very heavily results in a large Rp. This decreases the electrically induced losses in the substrate. Other high-frequency effects, however, induce loss in heavily doped substrates, as is discussed later. 4. Operating at higher frequencies can improve Q, until other high-frequency effects become significant, as is discussed later.
1. While there are some other ways of evaluating Q, the above definition is most commonly used for evaluating integrated spirals.
Chapter 3: High-Frequency Spiral Inductor Model
22
Cs Metal
Cox
Ls Rs
Cox Oxide
CSi
GSi CSi GSi
Ls
Silicon substrate
(a)
Cs
Rs Cox Ls
Cs
CSi
Rs
GSi
(b)
Cp
Rp
(c)
Figure 3.2: Generation of a simple circuit model for the spiral inductor. (a) Spiral inductor cross-section. (b) Equivalent circuit model which includes the circuit elements from the cross-section. (c) Reduced equivalent circuit model obtained by combining Cox, CSi, and GSi from (b) to a parallel circuit composed of Cp and Rp.
Chapter 3: High-Frequency Spiral Inductor Model
23
Optimization is required since all the above methods of improving Q are limited by technological constraints. The task of optimization becomes much simpler if compact expressions are available for the equivalent circuit elements. While significant progress has been made in terms of understanding and designing high quality spiral inductors, several effects which affect performance at higher frequencies have been neglected in previous compact models.
3.2.2 High-frequency Issues Various electromagnetic phenomena affect the performance of a spiral inductor at high frequencies. The prominent amongst these are described in the following sub-sections. 3.2.2.1
Electric Field Induced Substrate Loss
Spiral inductors are typically fabricated on top of a doped silicon substrate. The bottom of the substrate is connected to ground. Consequently, there is a time-varying electric field which originates from the inductor and mostly terminates on ground. This field penetrates the substrate and causes loss as shown in Figure 3.3. The amount of loss depends on the substrate doping, the inductor geometry, the height of the inductor above the substrate, and the frequency of operation. Additionally, such an inductor couples noise capacitively into the substrate and is susceptible to noise from the substrate. A patterned ground shield (PGS) was introduced by Yue [24] to address this problem. The PGS terminates the electric field and prevents it from reaching the substrate as shown in Figure 3.4. This eliminates the electric field induced substrate loss but increases the parasitic capacitance, Cp, of the inductor. The shield must be patterned in order to avoid eddy currents in the shield. An detailed treatment of inductors with PGS can be found in [25]. In presence of a well-designed PGS, the substrate loss factor of (3.1) may be eliminated. Process limitations, however, lead to non-optimal PGS designs. In Section 4.3, we present the inductor parasitics associated with a PGS and propose a new PGS design which minimizes them.
Chapter 3: High-Frequency Spiral Inductor Model
24
V1
V2
E-field based substrate loss
Oxide Silicon substrate Gnd
Figure 3.3:
Physical mechanism of electric field based substrate loss. The time-varying electric field from the spiral inductor penetrates the conducting substrate and terminates on the ground plate at the bottom.
V1
V2
Patterned ground shield
Oxide Silicon substrate Gnd
Figure 3.4:
3.2.2.2
Preventing electric field based substrate loss by terminating the electric field using a PGS.
Skin and Proximity Effects
Skin effect is a well-known phenomenon in which current flows closer to the surface of a conductor as frequency increases. Due to current crowding at the surface and corners of the conductor, the effective cross-sectional area of current flow contracts and the resistance increases. Inductance is also affected by skin effect. The total inductance of a system can be considered as the sum of an ‘internal’ inductance and an ‘external’ inductance. Internal inductance is due to the magnetic flux that is contained within the
Chapter 3: High-Frequency Spiral Inductor Model
25
cross-section of the conductor while external inductance, which is the dominant part, is due to the magnetic flux outside the conductor cross-section. Skin effect decreases the internal inductance as current flows near the surface of the conductor thereby reducing field lines inside the conductor. Although skin effect modifies the field outside the conductor, the net change in its external inductance value is small. Proximity effect, also a current crowding phenomenon, is the result of other currents flowing in the vicinity. Proximity effect causes the resistance to increase and the internal inductance to decrease in a manner similar to skin effect. Since external inductance is mostly unaffected, inductance reduction due to skin effect and proximity effect is seen to be small in typical spiral inductor designs and is not considered in this research. Section 3.4 covers the modeling of resistance and inductance change at RF due to skin and proximity effect. 3.2.2.3
Magnetic Field Induced Substrate Loss
The interaction of magnetic fields with the substrate plays a crucial role in determining performance of RFICs. The time-varying magnetic field induces eddy currents in the substrate which cause loss. This loss manifests itself as a decrease in Q of inductors and increased attenuation in transmission lines. It has been shown that this loss can be modeled as a resistance in series with the inductance [26]. While it is understood that substrate eddy currents lead to power loss, their effect on inductance is not commonly studied. The induced eddy currents in the substrate create their own magnetic field, which opposes that of the spiral inductor, causing the net inductance to decrease. Although a PGS can prevent interaction of electric field with the substrate, it does not prevent magnetic field interaction. Attempts have been made to eliminate substrate loss caused due to magnetic fields by techniques such as fabricating suspended inductors by etching pits in the silicon underneath [27], using MEMS to fabricate inductors far from the silicon surface [28], and using high-resistivity, ρsub > 10 Ω-cm, substrates. Due to its distributed nature, the substrate is inherently hard to model. While finite element techniques have been used extensively for computing magnetic field effects in the
Chapter 3: High-Frequency Spiral Inductor Model
26
substrate [19], accurate compact expressions are absent. Although Koldyaev [42] proposed an empirical expression for the frequency dependence of eddy current induced substrate loss in a spiral inductor, he does not provide the geometric dependence. Mohan [43] obtained simplified expressions for the substrate loss as a function of frequency and geometry. Measurement results [43], however, show limited accuracy for those expressions. While the qualitative effects of substrate doping, inductor geometry, and frequency on the substrate loss are well-known, the quantitative dependencies are not available. Accurate modeling expressions need to be developed in order to quantify these dependencies while providing physical insight into the phenomenon. Section 3.5 deals with the modeling of eddy currents in the substrate. 3.2.2.4
High-Frequency Equivalent Circuit
Figure 4.4 summarizes the manner in which the various phenomena that affect the performance of a spiral inductor at high frequencies translate to circuit behavior. The resulting three-terminal circuit model, which includes all these effects, is shown in Figure 3.6. While dc values of the elements of the circuit model are relatively easy to compute, their high-frequency value prediction is still a challenge. Sections 3.3, 3.4 and 3.5 deal with modeling the physical phenomena to calculate the circuit element values as a function of frequency and inductor geometry. Since most RF applications are narrowband, the equivalent circuit is suitable for accurate circuit simulation. It could also be used in broadband applications to estimate worst case behavior by setting parameter values using the highest frequency of interest. A distributed circuit model may also be used if greater a c c u r a c y i s d e s i r e d , e s p e c i a l l y a r o u n d t h e s e l f - r e s o n a n c e f r e q u e n c y, ω SR ~ (L.(C p +C s )) -0.5 . The geometrical parameters used in this model are shown in Figure 3.7, where in typical designs W >> s.
Chapter 3: High-Frequency Spiral Inductor Model
27
Skin and proximity effects Shield parasitics
Eddy current loss
Metal
PGS contact
PGS
Oxide
Silicon substrate
Figure 3.5: Relevant high-frequency effects in spiral inductors and their relationship to the circuit model. The PGS parasitics lead to increased parasitic capacitance. Skin/proximity effects lead to increased series resistance of the inductor. Eddy currents in the substrate cause power loss which can be modeled as a resistance in series with the inductor.
Cs (DC + Eddy currents) L(f)
Cp
(Eddy currents) Rsub(f)
Rmetal(f) (DC + Skin + Proximity)
Cp
(Shield parasitics)
Rshld
Rshld
PGS contact
Figure 3.6: Equivalent circuit model for a spiral inductor with PGS with frequency dependent circuit parameters for the relevant high-frequency effects.
Chapter 3: High-Frequency Spiral Inductor Model
28
Dout Metal
s
T
T1 Din A
Patterned ground shield
A’ Silicon substrate W
(a)
(b)
Figure 3.7: Geometric parameters of a square spiral inductor. (a) Top view, and (b) Cross-section along AA’.
3.3 Shield Parasitics Since typical PGS designs [29] are not optimal, the parasitics associated with a PGS, Cp and Rshld, must be modeled and minimized. The top view for the PGS design used in this research is shown in Figure 3.8. The next two sub-sections show the proposed design to be an optimal one.
3.3.1 Parasitic Capacitance Capacitance, Cp, can be assumed to be frequency independent for frequencies less than about 20 GHz. A simple model for estimating the capacitance of a rectangular conductor over a ground plane was proposed by Meijs and Fokkema [30]. The same equation when applied to the spiral inductor using the geometric parameters of Figure 3.7 gives (3.2). A factor of 0.5 appears for Cp because half the capacitance is distributed in each leg of the equivalent circuit. In order to minimize the parasitic capacitance, it is obvious that T1 must be as large as possible. Maximum T1 is obtained by designing the PGS in silicided poly or silicided diffusion.
Chapter 3: High-Frequency Spiral Inductor Model
29
s = 0.5µm Metal-1 strapped to silicided poly
Ws = 6µm
Wm= 2 Ws Silicided poly
Figure 3.8: Top view for PGS layout with polysilicon fingers and metal-1 straps.
2
2
( D out – D in )ε C area = ---------------------------------T1 W 0.25 T 0.5 C perimeter = ( 4D out + 4D in )ε 0.77 + 1.06 ------- + ------ T 1 T 1 C p = 0.5 ( C area + C perimeter )
(3.2)
Chapter 3: High-Frequency Spiral Inductor Model
30
3.3.2 Parasitic Resistance The parasitic resistance, Rshld, arises from the finite distance that the distributed capacitive current must flow through before it reaches the PGS contact. This resistance is depicted in Figure 3.9. In the PGS design shown below, it can be seen that the ‘X’ of the shield is where the capacitive current merges and flows. Consequently, to minimize Rshld, strapping this ‘X’, as well the strip between the PGS contact and the center of the PGS, with metal-1 using adequate2 contacts is recommended. This decreases the series resistance by more than an order of magnitude. The novel PGS design shown here has two important consequences. First, the ‘X’ shape geometrically enables a lower value for the resistance, Rshld, than those obtained by all other PGS designs in literature. This is because the capacitive current needs to travel the smallest distance, on an average, to get to the PGS contact. Next, the capacitive current, which flows through the PGS, has no net mutual coupling effect with the current in the spiral. As shown in Figure 3.10, the mutual inductance effects of various segments of the spiral cancel each other out on the ‘X’ of the PGS. This cancellation of magnetic fields on the shield has been independently shown by Tiemeijer [31], without providing any reasons, to be beneficial to inductor performance. Equation (3.3) gives the expression for Rshld using the geometrical parameters of PGS from Figure 3.7 and designed using silicided poly where RSHM1 and RSHPoly are the sheet resistances for metal-1 and silicided poly respectively. The additional factor of 2 in front of the equation comes about because Rshld is modeled as the resistance on each leg of the equivalent circuit of the spiral. D out 1 D out 1 R shld = 2 ----------- + ------ ----------- RSH M1 + --- RSH Poly 2W 4 12 2W s s
(3.3)
2. Number of contacts should be large enough to ensure that the contact resistance is negligible compared to the total resistance, Rshld, of the PGS.
Chapter 3: High-Frequency Spiral Inductor Model
31
Ic1
Cp Ic
Ic2
Rshld
Terminal 1
Terminal 2
PGS Contact
Figure 3.9: PGS parasitics. Note that the distributed capacitive currents add up in the ‘X’ of the PGS and flow through the resistance, Rshld, to the PGS contact. .
IL
Vinduced Vinduced IL
Figure 3.10: Induced voltages on the shield are equal and opposite implying that the net mutual inductance between PGS and the spiral is very small.
Chapter 3: High-Frequency Spiral Inductor Model
32
3.4 Skin and Proximity Effect In this section, we present a new modeling methodology for skin and proximity effect, which results in compact expressions to compute the ac resistance increase. Skin effect is treated as being composed of a ‘vertical’ skin effect and a ‘lateral’ skin effect. Proximity effect is modeled by an extension of the skin effect formulation. Simulation results have been included for model verification.
3.4.1 Skin Effect: Previous Work Numerous experimental studies [32, 33, 34] as well as studies based around numerical methods can be found in literature [35, 36, 37]. As frequency of operation of modern ICs continues to increase, the effects of skin and proximity effect have become very relevant. Although numerical tools exist to predict quantitatively this complicated effect [19, 38], simple compact formulae are lacking for the rectangular geometries prevalent in modern ICs. Pettenpaul proposed a compact formula for estimating skin effect in [39]. The accuracy of this formula degrades rapidly for a width to thickness ratio of the conductor greater than 12 which makes the formula unsuitable since such geometries are commonly found in spiral inductor designs. Another compact formula was proposed by Kuhn [40], which uses an estimate of eddy current loss in neighboring conductors to estimate proximity effect. This analysis is accurate only up to a cut-off frequency which often turns out to be lower that the frequency of operation.
3.4.2 Skin Effect: Modeling A plane wave, normally incident on a metal surface is shown in Figure 3.11. Fields inside the metal decay exponentially with skin depth ‘δ’ as predicted by Maxwell’s equations. Fields inside a rectangular conductor carrying current, however, do not exhibit this exponential behavior. Consequently, the associated current inside the conductor does not fall off exponentially from the surface either. Maxwell’s equations need to be reapplied to this geometry to solve for the current distribution inside the conductor.
Chapter 3: High-Frequency Spiral Inductor Model
33
Consider a parallel plane waveguide of finite width, W, as shown in Figure 3.12, with the two metal planes of finite conductivity separated vertically3 by a distance of the order of a few microns such that higher order modes cannot exist. Energy propagates in the z-direction in a quasi-transverse-electric-magnetic mode for frequencies less than 20 GHz. The magnetic field has only x- and y-components. The electric field has x-, y-components, and a z-component due to losses in the metal. The current flows primarily in the z-direction4. Due to the finite conductivity of the metal planes, current flows inside the metal thickness. Now consider the cross-section of one of the metal conductors as shown in Figure 3.13. According to Maxwell’s equations, ac current inside a metal conductor is a function of the H-field in the x and y-directions as given by (3.4). ∇×H = J
Jz =
∂H y ∂x
–
∂H x ∂y
(3.4)
Two-dimensional (2-D) simulations using MaxwellTM[19], a commercially available fullwave simulator, indicate that for wires whose width is much larger than their thickness, the x-component of the H-field is dominant which results in (3.5). Jz ≅ –
∂H x ∂y
(3.5)
As shown in Figure 3.13, the current in the conductor has a vertical, i.e. along the y-axis, non-uniformity which we refer to as ‘vertical’ skin effect. The non-uniformity of current density in the lateral direction, i.e along the x-axis, is referred to as ‘lateral’ skin effect. In typical IC wires, where the thickness is limited to 2 µm and width is limited to 30 µm, for frequencies below 20 GHz, the magnitude of the x-component of the H-field changes slowly in the x-direction, as illustrated in Figure 3.13. Since the width to thickness ratio of the conductors of a spiral is typically large, it is possible to solve (3.5) by using a separation of variables as shown in (3.6).
3. This skin effect analysis also holds if the planes were separated laterally by a similar distance. 4. The x- and y-components of current in the metal are negligible for this problem.
Chapter 3: High-Frequency Spiral Inductor Model
34
H x = F ( x )G ( y )
(3.6)
Substituting for Hx from (3.6) in (3.5), (3.7) is obtained. F(x) then represents the lateral skin effect while G’(y) represents the vertical skin effect. Jz ≅ F( x) ⋅
d G( y) dy
(3.7)
The vertical skin effect solution is shown in Section 3.4.2.1 and the lateral skin effect problem is solved in Section 3.4.2.2.
Vacuum
Eincident
κincident
Metal
Etransmitted
y
κtransmitted
Htransmitted
z
Hreflected
Hincident
x
κreflected |H|,|E|,|J| ~ exp(-x/δ)
Ereflected
x Figure 3.11: Field profiles for a plane wave normally incident on a metal surface. The fields and current fall off exponentially from the surface of the metal.
W
y z x
Direction of wave
E
Metal
H
propagation
Parallel plane waveguide
E
E
Metal
H
Figure 3.12: Field profiles for a wave propagating along the z-direction in a parallel-plane waveguide with finite metal conductivity and finite lateral dimensions.
Chapter 3: High-Frequency Spiral Inductor Model
35
Jz
Lateral skin effect
Jz
Actual current density
x
y
y z
Vertical skin effect
x
Figure 3.13: Vertical and lateral current density non-uniformities in a current carrying conductor.
3.4.2.1
Vertical Skin Effect
The case in which vertical skin effect is dominant is shown in Figure 3.14. In this instance, a signal line has two perfectly conducting ground lines, located above and below the signal line, carrying the return current. The width, W, is much greater than the spacing, s. This problem can be solved analytically, and its solution is presented in relevant texts [22]. The exact expression for the ac resistance due to vertical skin effect is presented in (3.8), where ‘t’ is the thickness of the metal, and ‘R dc ’ and ‘Rvac ’ are the signal line dc and ac resistances, respectively. t t Rv ac = real R dc • ϒ --- • coth ϒ --- 2 2
(1 + i) ϒ = ---------------δ
(3.8)
A simplified model, (3.9), in which ‘ρ’ is the resistivity of the metal, is obtained by considering the low and high-frequency asymptotes of the above equation. A better approximation, (3.10), can be derived for a frequency range of interest by considering the first two terms in the Taylor series expansion of (3.8). ρ ------Wt Rv ac1 = ρ ----------2Wδ
t < 2δ (3.9) t > 2δ
Chapter 3: High-Frequency Spiral Inductor Model
36
1024 t 8 4 t 4 Rv ac2 = R dc • 1 + ------ ⋅ ------ – ------------------ ⋅ ------ 725760 2δ 45 2δ
W
y z
s
(3.10)
Ground
H J
t
Signal line
x H
Ground Figure 3.14: Cross-section for simulation and analysis of vertical skin effect. Note that the width, W, of the line is much larger than the spacing, s, between the signal and ground lines. This ensures that the H-field magnitude is constant in the x-direction.
Signal Line Resistance p.u.l (Ω/m)
250 2-D simulation Theory (Eq. 3.7) Simple Model (Eq. 3.8) Advanced Model (Eq. 3.9) Ref [23]
200
150
100
Figure 3.15:
0
5
10 Frequency (GHz)
15
20
Comparison of models for vertical skin effect in copper. W = 100 µm, t = 1.6 µm, s = 1 µm; refer Figure 3.13 for geometry.
Chapter 3: High-Frequency Spiral Inductor Model
1.8
t = 0.5 µm (2-D sim) t = 1.0 µm (2-D sim) t = 1.6 µm (2-D sim) Model (Eq. 3.9)
1.6
Rac/Rdc
37
1.4
1.2
1.0
Figure 3.16:
0
5
10 Frequency (GHz)
15
20
Comparison of vertical skin effect model vs. simulation in copper for different thicknesses. W = 100 µm, s = 1 µm; refer Figure 3.13 for geometry.
Figure 3.15 plots the simulation results along with the different analytical models presented in (3.8)-(3.10) for the ac resistance of copper. An often used formula [23] is also plotted for comparison. Since that formula assumes a physically inaccurate distribution of current inside the metal conductor, it suffers from large errors in the frequency range of interest. In Figure 3.16, the advanced model, (3.10) is compared with simulated data for multiple thicknesses. The only requirement in the analysis of the vertical skin effect is that the horizontal H-field is constant along the width of the conductor. 3.4.2.2
Total Skin Effect
Figure. 3.17 shows the geometry for total skin effect analysis and simulations. The ground return line is located very far from the signal line so that the fields around the signal line are largely independent of the current in the ground line. This ensures the absence of proximity effect in these simulations.
Chapter 3: High-Frequency Spiral Inductor Model
38
y
W
z
t
x P = 300 µm
Signal line Figure 3.17:
Gnd
Cross-section for simulating total skin effect.
Ruehli [18] showed that the current distribution in a conductor can be computed by dividing the conductor into multiple segments, as in Figure 3.18, and then solving the equivalent RLC-network. Current divides up into the respective segments depending on the relative impedances. By subdividing the conductor laterally into a sufficiently large number of segments, as shown in Figure 3.18, we can assume that Hx, and hence Jz, is constant along the x-axis for each segment. Thus, for a given segment Hx is only a function of y. Therefore, from (3.7), within each segment, the current density has a vertical non-uniformity only and each segment suffers from the vertical skin effect only. To estimate the total skin effect, the resistance of each segment, Ri5, is modeled by (3.10), while the self and mutual inductances of each segment are modeled using Greenhouse’s formulae [21]. At lower frequencies, Ri >> Xi, and the current distribution is laterally uniform. At higher frequencies, the inductive terms dominate and the line appears as a set of coupled inductors in parallel. It is found that six segments of unequal widths are sufficient to model lines up to 20 GHz. The unequal segment widths are required since the lateral current non-uniformity increases towards the ends and can be captured accurately only by having narrower segments in that region. Consequently, the optimum segment widths are found to be [W/20, W/20, 2W/5, 2W/5, W/20, W/20] for a wire of width W. Using symmetry, only 3 equations need to be solved as given by (3.11).
5. i refers to the segment index of the subdivided conductor.
Chapter 3: High-Frequency Spiral Inductor Model
Li: Self inductance Mij: Mutual inductance
M23 L2 R2
Seg 1
Seg 2
Figure 3.18:
V V = V
39
L3 R3
Seg 3
Seg 4
Seg 5
Seg 6
Modeling lateral skin effect.
R 1 + jω ( L 1 + M 16 )
jω ( M 12 + M 15 )
jω ( M 13 + M 14 )
I1
jω ( M 12 + M 15 )
R 2 + jω ( L 2 + M 25 )
jω ( M 23 + M 24 )
I2
jω ( M 13 + M 14 )
jω ( M 23 + M 24 )
R 3 + jω ( L 3 + M 34 ) --I- – I – I 2 1 2
(3.11)
V R metal ( f ) = Real ---- I
The complete skin effect model is compared to simulation data in Figure 3.19 and Figure 3.20. The data from Figure 3.16 gives the magnitude of only the vertical skin effect in copper, e.g., for a line whose thickness is 0.5 µm, vertical skin effect causes less than a 5% increase in resistance at 20 GHz. Comparing this to the total skin effect results from Figure 3.19 for a line of the same thickness, it can be concluded that lateral current redistribution is the dominant source of resistance increase. In general, this is true for most geometries found in on-chip spiral inductors where t < 2 µm. Since the onset of lateral current redistribution depends on the resistance of each segment, thicker wires with smaller resistance suffer lateral skin effect at lower frequencies. Conversely, thicker wires show a larger percentage increase in their resistance at any given frequency as can be seen from Figure 3.19. Along similar lines, wider wires have a larger X/R ratio at any given frequency and hence have a larger percentage increase over the dc value as seen in Figure 3.20.
Chapter 3: High-Frequency Spiral Inductor Model
40
6000 t = 0.5 µm (2-D sim) t = 1.0 µm (2-D sim) t = 1.6 µm (2-D sim) Model (6-segment)
Rac p.u.l (Ω/m)
5000
4000
3000
2000
1000
0
5
10 Frequency (GHz)
15
20
Figure 3.19: Comparison of total skin effect ac resistance model to 2-D simulation results for different thicknesses in copper. W = 10 µm; geometry of Figure 3.17. 6000
W = 5 µm (2-D sim) W = 10 µm (2-D sim) W = 15 µm (2-D sim) Model (6-segment)
Rac p.u.l (Ω/m)
5000
4000
3000
2000
1000
0
5
10 Frequency (GHz)
15
20
Figure 3.20: Comparison of total skin effect ac resistance model to 2-D simulation results in copper for different widths. t = 1 µm; geometry of Figure 3.17.
Chapter 3: High-Frequency Spiral Inductor Model
41
3.4.3 Proximity Effect: Modeling As illustrated in Figure 3.21, a spiral inductor suffers from proximity effect due to conductors carrying current in the same direction as well as from those carrying current in the opposite directions. Simulations indicate that the proximity effect due to conductors carrying current in opposite directions in a typical spiral inductor with a hollow center is small. This is due to the large separation between these currents and therefore, those proximity effects can be neglected. Proximity effect in spiral inductors for conductors carrying current in the same direction is modeled by treating them as a single conductor of effective width, Weff, for W >> s. The resistance increase with frequency is estimated from (3.11). The proximity effect model is verified by comparison to 2-D simulations. The ground conductor is kept far from the signal lines in the simulated cross-section of Figure 3.22 so that the effect of the ground return path on proximity effects can be neglected. Figure 3.23 shows that the net resistance of one, two, and three signal line structures, for all of which Weff = 30 µm, is almost the same up to 20 GHz. This agrees well with the model predictions. Although this method systematically underestimates the loss as the number of signal lines increases, for most inductor geometries the model is quite accurate. Weff
Currents flowing in the same direction
Currents flowing in opposite directions
Figure 3.21: Different types of proximity effects in spiral inductors.The effect due to currents flowing on opposite sides of the spiral can be neglected since the distance between them is typically large.
Chapter 3: High-Frequency Spiral Inductor Model
Signal 1
42
Signal 2 P = 300µm
t W1
s Weff
Gnd
W2
Figure 3.22: Cross-section for simulating proximity effect of two signal lines. The ground return line is placed at large distance of 300 µm so that the fields due to ground current do not affect the signal lines. 1.8
W = 30 µm (Skin effect only) W1 = W2 = 15 µm (Skin + Proximity effect) W1 = W2 = W3 = 10 µm (Skin + Proximity effect) Model (6-segment)
Rac/Rdc
1.6
10% max error
1.4
1.2
1.0
0
5
10 Frequency (GHz)
15
20
Figure 3.23: Proximity effect model comparison to 2-D simulations in aluminum. Weff = 30 µm, s = 1 µm; see geometry of Figure 3.22.
Tiemeijer [41], recently, reported advances in reducing skin and proximity effect. This was done by first dividing each turn into multiple filaments of equal width followed by intertwining the filaments6 such that no one is a preferred ac current path which forces equal currents in all filaments and significantly decreases skin and proximity effects. The proposed skin/proximity effect model over-estimates resistance for such geometries.
6. This is similar to the concept of the Litz wire.
Chapter 3: High-Frequency Spiral Inductor Model
3.4.3.1
43
Small Spacing or Large Spacing?
A common problem faced in spiral inductor design is the choice of inter-turn spacing. A larger spacing decreases proximity effect and inter-wire capacitance but also decreases the mutual coupling between turns while increasing the area occupied for a given inductance. Thus, it is not obvious if a larger spacing is beneficial in spiral inductor design. To resolve this issue, results of a composite L/R ratio, obtained from 2-D simulations, are compared for the signal lines as shown in Figure 3.24. The data indicates that a significant improvement in inductor performance is not likely by increasing spacing between turns. The increase in resistance due to increased proximity effect is offset by the increased mutual coupling. Thus, in the interest of saving valuable silicon die area, a small spacing is recommended. 9
8
W1 = W2 = 20 µm (2-D sim) W1 = W2 = 10 µm (2-D sim)
ωL/R
7
6
5
4
0
2
4 6 Turn-to-Turn Spacing (µm)
8
10
Figure 3.24: Effect of turn-to-turn spacing on inductor performance in copper for two widths. In both cases ωL/R ratio is relatively independent of turn-to-turn spacing. f = 5 GHz, t = 1 µm.
Chapter 3: High-Frequency Spiral Inductor Model
44
3.4.4 Skin and Proximity Effect Summary The simulated data indicate that at frequencies above 1 GHz, skin and proximity effects cannot be neglected in spiral inductors with wide wires. As CMOS processes move from aluminum to copper metallization, skin and proximity effects increase with the result that wire resistance becomes more frequency dependent. Modern technologies employ several metal levels. It is possible to effect a thicker metal layer and decrease the resistance by strapping several metal layers together. Excessive strapping in spiral inductors, however, can be detrimental to performance at higher frequencies where the gains of added strapping are limited by the vertical skin effect as well as an increased parasitic capacitance. Using the models developed here, it is possible to optimize the number of metal layers to be strapped. The proximity effect analysis results suggest that the spiral inductor layout should be hollow and use minimum spacing between wires. The predictions of the physical models developed in this chapter are compared with simulated data. These models can be implemented in software thereby enabling quick predictions for different geometries.
3.5 Eddy Current Substrate Loss In this section, we focus on understanding and modeling magnetic field induced substrate loss. The electromagnetic problem posed by a spiral inductor geometry is quite complex and no compact solution for Maxwell’s equations, comparable to (3.8), for example, is known to exist. The problem must be simplified before any solution is attempted. Simplifying assumptions are presented first. This is followed by a derivation of compact model equations for coplanar transmission lines above a doped substrate. 2-D simulations are used to verify this model. This work is extended to include spiral inductors and the resulting model is verified with measured data.
3.5.1 Modeling Assumptions The substrate loss model is based on three simplifying assumptions:
Chapter 3: High-Frequency Spiral Inductor Model
45
(i) For every filamentary signal current, there exists a substrate current flowing in the opposite direction. The magnitude of the substrate current is equal to that of the filamentary signal current. The justification for this assumption can be seen from Figure 3.25(a) by asymmetrically enlarging the size of the return conductor. In the limit, when the ground return conductor is spread to look like the substrate with a semi-infinite thickness, the total return current in the substrate must still be the same value as the signal line. (ii) The substrate current is assumed to flow uniformly through a rectangular cross-section with x- and y-dimensions equal to the skin depth in the substrate, δ sub. Figure 3.25 illustrates the graphical approximation of this assumption. Since the coaxial ground return line current penetrates a distance of the order of the skin depth in the metal, δm, it assumed that the substrate current also penetrates a distance of the order of skin depth in the substrate, δsub, in the x- and y-dimensions. The resistance of the coaxial ground return line can be calculated with the assumption that the current flows uniformly in the hashed area shown in Figure 3.25 (a). Similarly, it is also assumed for case (b) of Figure 3.25 that the substrate current flows uniformly in the hashed area whose dimensions are equal to δsub. This results in rectangular cross-section for the substrate current flow. A fitting parameter, ‘α’, allows adjustment for the assumption of a rectangular cross-section area as shown in (3.12). (iii) The net current distribution in the substrate is a superposition of all the substrate currents as defined by the previous assumptions. The substrate current flows in a non-uniform manner for which there is no known closed-form mathematical solution. Assumptions (ii) and (iii), although not completely physical, provide the basis for a mathematical solution that matches closely with experimental and simulation results.
Chapter 3: High-Frequency Spiral Inductor Model
y
Effective area of return current flow Signal
46
Effective area of return current flow Signal
z x
∼δm ∼δm
δsub
δsub tsub Substrate (a)
Figure 3.25:
Ground return (b)
Ground return current flow for (a) Coaxial line and (b) signal line over substrate. In the coaxial line, the return current flows in the outer conductor to a depth of the order of the skin depth in the metal, δm. Similarly, it is assumed that the return current in (b) has a penetration depth equal to the skin depth in the substrate, δsub, in the x- and y-directions. This results in a rectangular current profile for the substrate current.
The substrate is assumed to have a large lateral dimension and a thickness given by t sub. If I signal is the total current in a signal line, the uniform current density in the substrate, Jsub, under the signal line is found by integrating over the area of substrate current flow (3.12). The assumption of a rectangular cross-section for the substrate current and the use of fitting parameter α results in a simple expression for Jsub. It is shown in later sections, that a single α can fit a wide variety of design parameters. I signal =
∫
A sub
J sub =
∫
J sub dx dy
Rect ( A sub )
I signal ⇒ J sub = -----------------2 2αδ sub
(3.12)
3.5.2 Substrate Effects in Coplanar Transmission Lines Model equations to predict substrate effects due to magnetic fields for coplanar lines of infinitessimal cross-section are first derived. Initially, only effects of substrate doping, frequency, and pitch are included. The equations are then extended to include effect of
Chapter 3: High-Frequency Spiral Inductor Model
47
non-zero width of the signal lines and the separation from the doped substrate. Inductance is estimated based on the modeled geometry of current flow. 3.5.2.1
Loss in Lines of Infinitessimal Cross-section
In Figure 3.26, a signal line and a coplanar ground line of an infinitesimal cross-section, both perfect conductors, are separated by pitch P and lie at a height h above a substrate of resistivity ρsub. Depending on the frequency of operation and line pitch, there are various possibilities for the substrate current distribution. When the pitch is smaller than twice the thickness of the substrate7, three distinct substrate current distributions are possible, as shown in the figure. At very high frequencies, case (a), the substrate current flows in a small cross-section under the signal and ground lines and do not overlap. At intermediate frequencies, case b, the substrate currents overlap and the total loss is calculated by superposition. At even lower frequencies, case c, the skin depth is larger than the thickness of the substrate and the substrate current extends all the way to the bottom of the substrate. Each of these cases gives rise to a different frequency dependence for substrate loss. The results obtained here are compared with the theoretical results obtained by Hasegawa [26] in the very-high-frequency limit. Case (a): Pitch > 2δsub Power dissipated per unit length PDsub, in the substrate is calculated by integrating I2R losses over the area of substrate current flow, as shown in (3.13). Substituting for Jsub from (3.12) in (3.13), we get (3.14). PD sub = 2
ρ sub 2 2 2 2 J sub ⋅ ρ sub dx dy = 2αJ sub ⋅ ρ sub ⋅ 2δ sub = I s ⋅ --------------------- (3.13) 2 α ⋅ δ sub substrate
∫
ρ sub 2 PD sub = I s ⋅ --------------------2 α ⋅ δ sub
(3.14)
7. This is quite common since typical substrate thicknesses are about 200 - 500 µm and most inductor geometries have pitches less than 300µm.
Chapter 3: High-Frequency Spiral Inductor Model
48
From (3.14), it can be seen that the total substrate loss due to the signal and coplanar ground lines can be modeled as a resistor Rsub in series with the signal line, and another equal resistor in series with the coplanar ground return, given by (3.15). Note that the model predicts, to first order, that the substrate loss at high frequencies is independent of pitch and substrate doping. ρ sub R sub = ------------------------2 2α ⋅ δ sub
Pitch > 2δ sub
(3.15)
Case (b): Pitch < 2δsub < 2tsub Proceeding in an identical fashion as case (a), we can derive Rsub in this case to obtain (3.16). The substrate loss in this frequency range is proportional to pitch indicating that, at these frequencies, coplanar lines which have a larger separation have a larger loss. ρ sub ⋅ Pitch R sub = ----------------------------3 4αδ sub
Pitch < 2δ sub < 2t sub
(3.16)
Case (c): 2δsub > 2tsub In this case, the area of substrate current flow is bounded on the bottom side since the skin depth is greater than the thickness of the substrate. For this frequency range, the model predicts that the substrate loss is proportional to the square of the frequency and the thickness of the substrate. ρ sub ⋅ Pitch ⋅ t sub R sub = ------------------------------------------4 4αδ sub
δ sub > t sub
(3.17)
When the pitch is greater than twice the thickness of the substrate, depending on the frequency and skin depth in the substrate, a different set of possibilities exist. The losses for the respective cases can be calculated in a similar fashion.
Chapter 3: High-Frequency Spiral Inductor Model
Signal
49
Coplanar ground
Pitch = P
h δsub
δsub
δsub
tsub
δsub
Induced substrate currents
Substrate
(a) P > 2δsub Pitch = P
Coplanar ground
δsub
h
tsub
δsub
P Induced currents cancel here
Substrate
(b) P < 2δsub < 2tsub Signal
Pitch = P
h
tsub
Coplanar ground δsub
Increasing frequency
Signal
P Substrate Induced currents cancel here
(c) tsub < δsub Figure 3.26: Substrate current flow for a coplanar transmission line for different frequencies. At lower frequencies, case (c), the induced substrate currents overlap significantly. At very high frequencies, case (a), the induced currents do not overlap at all and substrate loss is maximum.
3.5.2.2
Width Dependence of Loss
When signal and ground lines have a finite width W, the substrate loss can be calculated analytically from the previous assumptions. The signal/ground line is
Chapter 3: High-Frequency Spiral Inductor Model
50
subdivided into infinitesimally narrow filaments, each with their own substrate current. The substrate currents are then superimposed to calculate the net current distribution in the substrate. The resulting current distribution is uniform in the vertical direction and non-uniform laterally. A sample case at high frequencies is depicted in Figure 3.27. The net substrate resistance is found by integrating the power loss over the substrate area. The detailed integration is illustrated in Appendix A and the results are repeated in (3.18). Width dependencies for other geometric cases are given in Appendix B.
W
Pitch = P Signal δsub
Coplanar ground
tsub Substrate
Induced substrate currents (a)
Jsub
x (b)
Figure 3.27: Substrate currents for signal and ground lines of width W, where P-W > 2δsub. (a) Total substrate current is a superposition of substrate current contributions due to each infinitessimal segment of the signal and ground line. (b) Net current density is trapezoidal in the substrate along the x-axis.
ρ sub W ---------------------- 1 – --------------- 6δ sub 2 2αδ sub R sub =
( P – W ) > 2δ sub > W
2 ρ sub 2δ sub W – --3- δ sub ---------------------- ------------------------------------------------ 2 2 W 2αδ sub
(3.18) W > 2δ sub
Chapter 3: High-Frequency Spiral Inductor Model
51
ρ sub Note that for W > 2δsub, in the limit of very high frequency, R sub → ------------------------- which ( W ⋅ δ sub ) matches the theoretical result obtained by Hasegawa [26]. 3.5.2.3
Dependence of Loss on Distance from Substrate
The magnetic field below the signal line is decreased by the presence of the coplanar ground which in turn decreases the magnitude of substrate currents induced. The effect of this magnetic field reduction on substrate loss must be modeled especially if P ~ h. Typical spiral inductor geometries, however, have P >> h and the range of available separations from the substrate are limited to only a few microns with 5 µm < h < 10 µm. This implies that the dependence of eddy-current induced substrate loss on separation from the substrate is small in typical integrated spiral geometries. It was found that an attenuation factor, η, given by (3.19), experimentally fits the height dependence of substrate loss. 2h η = 1 – ------------------------------------------ 2 2 Pitch + ( 2h ) 3.5.2.4
(3.19)
Modeling Inductance
Frequency dependent substrate current distributions, seen in cases (a)−(c) of Figure 3.26, result in a frequency dependent inductance. Figure 3.28 shows the current distributions and the mutual coupling between them for case (a). Greenhouse’s formulae [21] are used to calculate the self and mutual inductances for each of the currents. Equation (3.20) is used to estimate mutual inductance as a function of frequency where the total substrate current, Isub, is a function of frequency while the total signal current, Isig, and Msig-sub, the mutual inductance calculated from Greenhouse’s formulae [21], are independent of frequency. Since the magnitude of all the currents is the same in this case, the effective mutual and self-inductances are given by (3.21). The net frequency dependent inductance, Leff, for the coplanar line is given by (3.23), where Ldc is the low frequency value of the coplanar line inductance and Lsub is the substrate dependent factor to be subtracted from it. For cases (b)−(c) of Figure 3.26, because the total eddy current magnitude is not the same
Chapter 3: High-Frequency Spiral Inductor Model
52
as the current flowing in the signal lines, the mutual inductance between the signal line and substrate must be scaled by the ratio of these two currents. I sub ( f ) M sig – sub ( f ) = ------------------M sig – sub I sig
Msig-gnd Msig-sub2
Lsig
(3.20)
Lgnd
Msig-sub1
Mgnd-sub2 Lsub1
Lsub2
Figure 3.28: Mutual coupling between signal/ground lines and the image eddy currents in the substrate. Self inductance names all begin with ‘L’ while all mutual inductances begin with ‘M’.
L sig ( f ) = L sig – M sig – sub1 ( f ) eff L gnd ( f ) = L gnd – M gnd – sub2 ( f ) eff
(3.21)
M sig – gnd ( f ) = M sig – gnd – M sig – sub2 ( f ) eff (3.22) L sub ( f ) = M sig – sub1 ( f ) + M gnd – sub2 ( f ) + 2M sig – sub2 ( f ) L eff ( f ) = L dc – L sub ( f )
(3.23)
Chapter 3: High-Frequency Spiral Inductor Model
3.5.2.5
53
Model Verification for Coplanar Lines
The resistance and inductance models are verified using 2-D simulations in MaxwellTM. Effects of doping are studied using coplanar lines of negligible cross-section and infinite conductivity in Figure 3.26 on three heavily doped substrates with ρsub = 0.01, 0.02, and 0.05 Ω-cm. Magnetic field induced substrate effects decrease with doping, as is evident from Figure 3.29. The plot confirms the model prediction that Rsub for all the different substrates converges to the same asymptote at higher frequencies, where loss is relatively independent of substrate doping. A value of 3.3 for the parameter α is used to fit the model predictions to the simulated data. Using the same cross-section, model performance with respect to pitch is examined by simulating coplanar lines with three different separations with P = 50, 100, and 200 µm. Coplanar lines with a larger pitch show a larger frequency dependence of loss. Inductance also shows a larger frequency dependence and drops off significantly for a separation of 200 µm. Note that the simulated data for the resistance converges at higher frequencies as predicted by the model. For this case as well, a value of 3.3 for α is used to fit the model predictions to the data. Although the height dependence of substrate loss is not very large, the empirical fit (3.19) is observed to be good in Figure 3.31. Width dependence is shown in Figure 3.32 where several different widths are simulated using the cross-section of Figure 3.26 where the coplanar lines have a non-zero width and infinite conductivity. The simulations confirm the model prediction that the substrate loss is weakly dependent on width. The effect of current redistribution within the signal and ground lines on the substrate loss is not modeled here and is a source of error especially at higher frequencies, f > 15 GHz. Despite this, the model captures the trends of the simulated data.
100
2.5
10
2.0
1
1.5
0.1
1.0 ρsub = 0.01 Ω-cm (2-D sim) ρsub = 0.02 Ω-cm (2-D sim) ρsub = 0.05 Ω-cm (2-D sim) Model (α = 3.3)
0.01
0.001 0.1
Figure 3.29:
1 10 Frequency (GHz)
0.5
0.0 100
Effect of substrate doping on resistance and inductance of coplanar transmission lines. W = 1 µm, P = 100 µm, tsub = 200 µm, h = 10.5 µm.
100
2.5
10
2.0
1
1.5
0.1
1.0
0.01
0.001 0.1
P = 50 µm (2-D sim) P = 100 µm (2-D sim) P = 200 µm (2-D sim) Model (α = 3.3)
1 10 Frequency (GHz)
Leff p.u.l. (nH/mm)
Rsub p.u.l. (Ω/mm)
54
Leff p.u.l. (nH/mm)
Rsub p.u.l. (Ω/mm)
Chapter 3: High-Frequency Spiral Inductor Model
0.5
0.0 100
Figure 3.30: Effect of separation on resistance and inductance of coplanar transmission lines. W = 1 µm, ρsub = 0.01 Ω-cm, tsub = 200 µm, h = 10.5 µm.
Chapter 3: High-Frequency Spiral Inductor Model
2.5
2.0
30
1.5 20 h = 10.5 µm (2-D sim) h = 5.5 µm (2-D sim) h = 2.5 µm (2-D sim) Model (α = 3.3)
10
0 0.1
Figure 3.31:
1.0
Leff p.u.l. (nH/mm)
Rsub p.u.l. (Ω/mm)
40
55
0.5
1 10 Frequency (GHz)
0.0 100
Effect of separation from the substrate, h, on resistance and inductance of coplanar lines. W = 1 µm, ρsub = 0.01 Ω-cm, P = 100µm, tsub = 200 µm.
Rsub p.u.l. (Ω/mm)
30 f = 5 GHz (2-D sim) f = 10 GHz (2-D sim) f = 15 GHz (2-D sim) Model (α = 3.3)
20
10
0
1
10 Width (µm)
100
Figure 3.32: Effect of changing width of signal and ground lines on resistance and inductance. W = 1 µm, ρsub= 0.01 Ω-cm, P = 150 µm, tsub = 200 µm.
Chapter 3: High-Frequency Spiral Inductor Model
3.5.2.6
56
Eddy Current Loss in Spiral Inductors
3.5.2.6.1 Model Derivation For a single-turn inductor, effects of the interaction of its magnetic field with the substrate are modeled by treating the spiral as the sum of two coplanar transmission lines 8, as shown in Figure 3.33. The model for the eddy current effects in a coplanar line has been derived previously in Section 3.5.2. For a spiral inductors with N turns, the substrate effects are calculated by treating the multiple closely spaced turns as a single turn of effective width Weff as in Figure 3.34. gnd
sig
sig
Average Pitch = Davg gnd Top view for a square single turn inductor
Transmission line 1
Transmission line 2
Figure 3.33: Decomposition of a single turn spiral inductor into two coplanar transmission lines.
W eff Average Pitch = Davg
Figure 3.34: Modeling the multi-turn spiral as a single turn inductor of effective width Weff.
8. The analysis for the spiral inductor assumes that the inductor dimensions are much smaller than the wavelength of the electromagnetic waves at the operating frequency.
Chapter 3: High-Frequency Spiral Inductor Model
57
For a multi-turn spiral, the substrate loss resistance, Rsub, and the self and mutual inductances are scaled by a factor of N2 to account for the composite effect of the multiple turns. The average diameter of the spiral, Davg, replaces the pitch, P, in the equations. The complete set of equations for the spiral inductor is given in Appendix C.
3.5.3 Eddy current loss summary It is observed from the model that the eddy current loss in the substrate is strongly dependent on spiral area, pitch, substrate doping and frequency, while the dependence on height above the substrate is relatively weak. This makes the choice of technology paramount, since the model predicts that the spiral inductors can have significantly higher losses on an epi substrate where ρ sub ~ 0.015 Ω-cm, as compared to a non-epi bulk substrate for which ρsub ~ 10 Ω-cm.
3.6 Experimental Verification Experimental verification of this model was carried out by fabricating several spiral inductor geometries on a variety of substrates in the Stanford Nanofabrication Facility. Davg W
W
Air
Metal-3 1.6 µm Al
Metal-3 2.2 µm (SiO2) Metal-1 Substrate Contact
1.0 µm (SiO2)
Metal-2 (underpass) 0.8 µm Al
0.3 µm (SiO2)
PGS 0.3 µm Al
Substrate (p or n-type)
Figure 3.35: Spiral inductor cross-section showing the various layers. Metal-3 is used for creating the turns of the spiral with the underpass located in metal-2. The PGS is designed in metal-1.
Chapter 3: High-Frequency Spiral Inductor Model
58
3.6.1 Test Structure Fabrication A six mask process using deposited silicon-dioxide, εr=4, as insulator and sputtered Aluminium, ρ = 2.9e7S/m, as metal was designed and developed for making test structures. The process cross-section is shown in Figure 3.35. The substrate is connected in all the cases and shorted, along with the PGS, to the ground pad. The PGS is of ‘X’ shape and made in metal-1 to ensure minimal loss in the substrate. Consequently, the remaining loss mechanisms dominate performance. Five wafer splits, K2, I2, H2, M2, and L2, are used with substrate dopings of 13, 0.64, 0.084, 0.036, and 0.018 Ω-cm, respectively. The least doped substrate, ρsub = 13 Ω-cm, is typical of starting silicon in a bulk technology, while the highest doped substrate, ρsub = 0.018 Ω-cm, is typical for an epi technology. A set of geometries, shown in Table 3.1, with multiple outer diameters (Dout), widths (W), and number of turns (N), were fabricated for each of the five splits. The probe pads used for measuring the test structure introduce an unwanted parasitic capacitance in the measurements. All test structures are accompanied by structures to subtract out the effects of the pad capacitance. . Table 3.1: Spiral inductor test structure matrix. Split
Substrate ρ (Ω-cm)
Inductor geometries W (µm)
Dout (µm)
N
K2
13
5 − 10
100 − 300
1−8
I2
0.64
5 − 10
100 − 300
1−8
H2
0.084
5 − 10
100 − 300
1−8
M2
0.036
5 − 10
100 − 300
1−8
L2
0.018
5 − 10
100 − 300
1−8
3.6.2 Measurements and Results One-port S-parameter measurements were carried out using the HP8510 network analyzer. The standard technique of ‘Short-Open-Load’ calibration was used to ensure accurate
Chapter 3: High-Frequency Spiral Inductor Model
59
measurements [44][45]. After subtracting the effects of the pad capacitance, the measured S-parameters are transformed to input impedance Zin. Inductor Q is calculated as the ratio of the imaginary part of Zin to the real part. The effect of various substrate dopings is illustrated in Figure 3.36. The most heavily doped sample shows a peak quality factor reduction of almost 35% as compared to the most lightly doped sample for the given geometry. The rapid rise of resistance with frequency is the main cause of the lower peak-Q frequency in heavily doped samples. The model uses α = 3.3, which is the same value used in the modeling of transmission lines. The measurements also confirm the model prediction that bulk technologies, ρsub ~ 13 Ω-cm, do not suffer from magnetic field induced losses in the substrate. For a given inductor, the effect of substrate doping decreases for lower frequencies. Lower frequency, f ~ 1 GHz, RF circuits, however, often require larger inductances, which correspond to a larger Dout and an increased number of turns. Therefore, eddy current induced substrate loss cannot be neglected at lower frequencies as it increases rapidly with both these factors. Measured results in Figure 3.37 show that, even at 1.2 GHz, a 10 nH inductor suffers from Q-factor reduction as large as 25% in an epi-type wafer, L2, when compared to a bulk-like wafer, K2. Figure 3.38 (a),(b) illustrate the model performance with respect to geometry for heavily as well as lightly doped substrates. Spiral inductors on lightly doped substrates suffer primarily from skin and proximity effect. The model predicts these phenomena well in Figure 3.38(a) for several geometries. For spiral geometries on heavily doped substrates, the eddy current losses are significant. Figure 3.38(b) confirms the accuracy of the eddy current substrate loss model for a variety of geometries. While the previous plots verify that Q is well modeled, the modeling of the real and imaginary parts of the measured impedance need to be separately verified. Figure 3.39(a) and (b) compare the effective resistance, Real(Z in ), and inductance, Imag(Z in )/ω, respectively, for a spiral inductor on heavily and lightly doped substrates. The effective resistance is much higher and the effective inductance is lower in the epi-type sample.
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60
4 Peak-Q shifts to lower frequency K2 H2 M2 L2 Model (α = 3.3)
Q
3
2
Increasing substrate doping
1
0 0.1
Figure 3.36:
1 Frequency (GHz)
8
Effects of increasing substrate conductivity on Q. Higher doping leads to decreased Q. Dout = 250 µm, W = 5 µm, N = 4, Ldc = 7.88 nH. 5
K2 L2 Model (α = 3.3)
4 25%
Q
3
2
1
0
0
1 2 Frequency (GHz)
3
Figure 3.37: Effect of substrate doping for a 10-nH inductor at lower frequencies. Even at 1.2 GHz, the heavily doped sample shows 25% degradation. Dout = 250 µm, W = 10 µm, N = 8.
Chapter 3: High-Frequency Spiral Inductor Model
61
(K2: Dout = 250 µm, W = 10 µm)
7
N=2 N=4 N=6 N=8 Model (α = 3.3)
6 5
Q
4 3 2 1 0
0
1 Frequency (GHz)
10
(a) (M2: Dout = 150 µm, W = 10 µm)
5
4
N=2 N=3 N=4 N=5 Model (α = 3.3)
Q
3
2
1
0 0.1
1 Frequency (GHz)
10
(b)
Figure 3.38: Model performance with respect to geometry for (a) Lightly doped sample, K2, and (b) Heavier doped sample, M2. Skin and proximity effect models can be evaluated in (a), while models for eddy current loss in the substrate can be evaluated in (b).
Chapter 3: High-Frequency Spiral Inductor Model
62
100
Effective Resistance (Ω)
90
K2 L2 Model (α = 3.3)
80 70 60 50 40 30 20 10 0
0
2
4 6 Frequency (GHz)
8
10
(a)
Effective Inductance (nH)
6 K2 L2 Model (α = 3.3)
4
2
0
0
2
4
6 8 10 Frequency (GHz)
12
14
(b)
Figure 3.39: Effect of epi vs. non-epi substrate dopings on (a) Effective resistance, and (b) Effective inductance. Dout = 200 µm, W = 5 µm, N = 3.
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63
The overall model performance is summed up in Figure 3.40. Model error across all different substrates and inductor geometries is mostly less than 10% including errors due to process variations and measurements. The model uses the value of α = 3.3 for all the test structures.
Number of Samples
40
30
20
10
0 -15
-10
-5 0 5 Percentage Error in Peak-Q
10
15
Figure 3.40: Modeling error for peak-Q across all splits and geometries (145 samples).
3.7 COILS: A New Spiral Inductor Analysis Tool A web-based modeling tool has been created and is publicly available for use at http://haydn.stanford.edu/inductor/index.html to optimize and analyze spiral inductors in a given technology. The overall flow of the web tool is presented in Figure 3.41 and its images, as seen on the screen, are displayed in Figure 3.42 and Figure 3.43.
Chapter 3: High-Frequency Spiral Inductor Model
64
Choose: Epi / Non-Epi Select: Synthesis / Analysis Input: Technology Parameters Synthesis
Analysis
Constraints: Ldes, Cp, f, Dout
Input: Dout, W, N, s, nmetal Submit
Figure 3.41: Web-based spiral inductor tool user interface.
Technology parameters such as inter-layer-dielectric (ILD) thickness, ILD permittivity, metal thickness, metal sheet resistance, number of metal layers, and substrate doping are used as inputs. Once the user decides on an inductance value and a frequency of operation, the program synthesizes near optimal geometric parameters subject to constraints such as a maximum parasitic capacitance and area. The optimum is obtained by sweeping the geometric space which consists of Dout, N, W, and the number of strapped metal layers, nmetal. Based upon results from Section 3.4.3.1, the turn-turn spacing is kept fixed at minimum value of 1 µm. Instead of linearly searching the geometric space for the optimum, the search is made faster by using a binary search algorithm. The tool also lets the user evaluate a certain inductor geometry in a given technology by calculating the equivalent circuit parameters as a function of frequency.
Chapter 3: High-Frequency Spiral Inductor Model
COILS: Your Premier Inductor Synthesis and Analysis Software. Synthesize and analyze spiral inductors in a technology of your choice.
How to use?? As easy as ABC.... Follow steps 1 through 4 and press Submit. Ready or not here goes ......
Step 1 : Please choose EPI if you use an Epi substrate or choose NON-EPI if you use bulk substrate.
Technical Details: 1. All designs are intended for on-chip square spiral designs. 2. All designs assume a silicided,metal strapped polysilicon patterned ground shield in ’star’ shape and a Metal1 underpass. A sample shield picture is shown here. 3. Technologies are assumed to be using CMP for all dielectric layers in the back-end. Also all ILD are assumed to be of the same permittivity. 4. The current version assumes Al only or Cu only as metal layers.Cu-Al stacks will result in extra error at high frequencies. 5. The program uses a set of L,C etc parameters and geometry parameters which are defined here. Complete documentation including theory etc coming very soon.... FAQ Comments or suggestions : Please send email to Niranjan Talwalkar
Figure 3.42: Main web page for spiral inductor synthesis/analysis tool. http://haydn.stanford.edu/inductor/index.html
65
Chapter 3: High-Frequency Spiral Inductor Model
66
Analyze / Synthesize an inductor in an Non-epi process. Step 2: Make a design choice: Inductor Synthesis Inductor Analysis Step 3: Enter Technology data 6 metal levels max ( Help on entering Technology data.) Layer Name
Layer Number
Layer Prop.
Metal
8
RSH=
ILD
8
K=
Metal
7
RSH=
ILD
7
K=
Metal
6
RSH=
ILD
6
K=
Metal
5
RSH=
ILD
5
K=
Metal
4
RSH=
Thickness (microns)
Input required for Synthesize choice 2 Desired inductance (nH) Maximum outer dimension 200 (microns) Maximum parasitic cap. to gnd 150 shield (fF) 5 Frequency of operation (GHz) Yes Half_turn_inductor?? No ** This operation takes about 1 min to complete. Please wait..
ILD
4
K=
Metal
3
RSH=
ILD
3
K=
Metal
2
RSH=
0.5
2
K=
0.5
Metal
1
RSH=
0.5
ILD
1
K=
0.4
Poly
0
RSH=
Sub
0
Rho(Ohm-cm)=
ILD
Step 4: Enter appropriate Input depending on your design choice.
0.07
4.0 0.07
4.0
0.3
5 10
Input required for Analyze choice 200 Outer dimension (microns) 3 Number of turns Number of strapped metal layers 1 Width of each turn (microns) 10 Spacing between turns (microns) 2
Step 5: Submit your request Submit QueryReset
500
Figure 3.43: Bulk substrate web page for spiral inductor tool
3.7.1 Need for optimization In order to understand the need for optimization, a 3 nH inductor was optimized in (a) a lightly doped, ρsub1 = 10 Ω-cm, bulk process and (b) a heavily doped, ρsub2 = 0.01 Ω-cm, epi process subject to the following constraints: D out < 250 µm, C p < 150 fF, and f = 5.2 GHz. The results of the optimizations yielded two geometries, Lopt epi and Loptnonepi, as listed in Table 3.2. The optimum geometries are vastly different for the two
Chapter 3: High-Frequency Spiral Inductor Model
67
technologies. The performance of the optimized geometries is presented in Figure 3.44. The heavily doped epi-type substrate results in an optimal Q of 5.9 while the lightly doped substrate achieves a Q of 10.
Table 3.2:
Optimized geometries for a 3-nH spiral inductor in Epi and Bulk processes. Geometry
Outer Diameter (µm) Width of each turn (µm) Number of Turns Number of strapped metals Turn-turn spacing (µm)
12
Epi Process (ρsub = 0.01 Ω-cm) 90 3.5 6 4 1
Bulk Process (ρsub = 10 Ω-cm) 170 10 4 4 1
Constraints: Dout < 250 µm, Cp < 150 fF, fo = 5.2 GHz
10
Bulk
Q
8 6 4
Epi
2 0 0.1
1 Frequency (GHz)
10
Figure 3.44: Predicted performance of optimized 3-nH inductors in epi, ρsub1 = 10 Ω-cm, and bulk, ρsub2 = 0.01 Ω-cm, technologies differing only in substrate doping.
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68
If the inductor, optimized for a bulk substrate, is used on the epi substrate, the performance is inferior to the one optimized for the epi substrate as shown in Figure 3.45. It can be concluded that optimization with respect to the particular substrate is essential.
6
Loptepi Loptbulk
Q
4
2
0 0.1
1 Frequency (GHz)
10
Figure 3.45: Comparison of performance of two 3 nH inductors in an epi process. Loptbulk, is optimized for a bulk process, while Loptepi is optimized specifically for the epi process.
3.8 Summary RF circuit design requires accurate modeling and characterization of spiral inductors for a variety of technologies at high frequencies. This chapter studies the principal phenomena affecting spiral inductor performance at RF, viz. shield parasitics, skin and proximity effects, and eddy current substrate loss. A new PGS design is developed and shown to be near optimal. A physics based model is developed to provide qualitative and quantitative insight into the RF phenomena.The proposed model is verified using 2-D simulations and measurements. A web-based modeling tool is developed and described to assist RF circuit designers in quick analysis and synthesis of inductors.
Chapter
4
Transmit-Receive Switch using Inductive Substrate Bias
4.1 Introduction A typical superheterodyne RF transceiver architecture contains a few blocks which are routinely implemented off-chip using alternative technologies, as shown in Figure 4.1. These include the antenna, the pre-selection bandpass filter, the IF SAW filter, and the transmit-receive (T/R) switch. While efforts are being made to integrate these blocks on a single chip using standard CMOS technologies [9, 46], the quality factor of on-chip inductors and the substrate parasitics of MOSFETs remain important limiting factors. The inductive substrate bias technique and the improvements in inductor design, described in the previous chapters, allows investigation of novel topologies for improved performance. Typical off-chip blocks Antenna
LNA
Rx T/R Switch
Bandpass Filter
RF Mixer
Image Reject Filter
IF Mixer Bank SAW Filter
Frequency Synthesizer
Frequency Synthesizer
LC Filter
Tx PA
Buffer
SSB Mixer
I Q
φ
o φ+90
Baseband: I/Q Signals
I IF Mixer Bank
Q
Figure 4.1: Sample RF superheterodyne architecture [4]. The antenna, bandpass filter, T/R switch, and SAW filter are usually implemented off-chip
69
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
70
Recent publications [5, 6] suggest that receivers are being integrated from the LNA onwards while the transmitters are integrated up to the PA. An integrated T/R switch which includes matching networks for the LNA and PA will push the integration boundary further towards the antenna as shown in Figure 4.2. Such an improvement also decreases board component count and hence total cost. Therefore, the T/R switch is a desirable, as well as a suitable, candidate for evaluating the impact of the inductive substrate bias technique.
Matching Networks
Z
LNA
Rx
Z BPF
T/R Switch
Z
This work
PA
Tx
An integrated transceiver IC
Chip-to-board boundary
Figure 4.2:
A radio front-end block diagram showing the integration of the T/R switch and matching networks. The effect of integrating the T/R switch is to push the chip-to-board boundary closer to the antenna.
The purpose of a T/R switch is to alternately couple the antenna to either the transmitter or the receiver, and to protect the receiver while transmitting high power. A simple schematic of a T/R switch is shown in Figure 4.3. The switch operates in either the transmit (Tx) mode, in which power is transmitted from the PA to the antenna, or in the receive (Rx) mode, when power is delivered from the antenna to the LNA. The two switches, S1 and S2, are operated using opposite phases of a control signal, Vctrl, thereby ensuring that the antenna is connected to either the LNA or the PA, but not both. Ideally,
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
71
for all input power levels, S1 and S2 would be perfect ‘shorts’ with zero impedance when closed and perfect ‘opens’ with infinite impedance when the contacts are separated.
Vctrl Tx & PA
S1
Antenna & BPF
Vctrl S2
Rx & LNA
Figure 4.3: Simplified schematic of a T/R switch.
This chapter presents an integrated 5.2 GHz CMOS T/R switch design, implemented in a 0.18 µm CMOS technology, for use in wireless communication systems. The chapter begins with an introduction to the various families of switch topologies used in previous work. Specifications for an integrated CMOS switch are then developed, followed by a description and working of the topology used. Reliability concerns due to electrostatic discharge (ESD) are also discussed. In Section 4.4, measured performance data are presented and compared to simulations. Finally, the integrated prototype developed here is compared with other CMOS switches described in the literature and with commercially available discrete switches which use alternative technologies.
4.2 Integrated T/R Switch Requirements Based on previous work [17] and datasheets of existing parts [48], a set of specifications are developed for an integrated T/R switch for 802.11 type wireless-local-area-network (WLAN) systems. The asymmetry in the received and transmitted power levels can be effectively used to arrive at a set of specifications which can be met by designs in a CMOS technology.
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72
4.2.1 Performance Metrics for T/R Switches The performance of a T/R switch is characterized by several parameters in the transmit and receive modes. A brief description of each of these is presented below: 1. Insertion Loss (IL): For an ideal switch, no power is lost in the switch. Insertion loss is the power lost in the T/R switch, and is given by ‘Pout(dB) − Pin(dB)’, under matched conditions. For a WLAN system, a T/R switch with an IL < 1.5 dB is desirable. 2. Isolation (Iso.): Isolation is a measure of the signal attenuation from the signal port to the unused port, e.g., in the Tx mode, isolation is measured from the Tx port to the unused Rx port. Although, isolation is usually in the negative dB range, it is common practice to use its absolute value. Isolation greater than 30 dB is desirable to protect the unused port from high power and minimize loss. 3. Return Loss: This parameter is a measure of the input and output matching conditions. Similar to the isolation parameter, the return loss is usually expressed in absolute value terms even though the actual value is usually in the negative dB range. A return loss greater than 10 dB, at the input and the output, usually indicates acceptable power transfer conditions. 4. Linearity: Linearity or power handling capability is a measure of the ability of the T/R switch to maintain a low loss without distorting the signal at high input power levels. The desired value of this parameter depends on the maximum input and output power of the application. The 1 dB compression point, P1dB, is a common measure of linearity in T/R switches. 5. Power: Static power dissipation must be kept as low as practical. Power consumption of less than 1 mW is desirable. 6. ESD reliability: The ESD performance of the switch is usually measured using the human-body-model (HBM) method. This method essentially measures the robustness of the part when subjected to a static discharge arising from human contact. In applying this model, a 200 pF capacitor is charged to a certain voltage and then discharged through the device-under-test (DUT). The DUT breaks down and ceases to function as the voltage on the capacitor exceeds a certain threshold. This breakdown voltage is used as a measure of the ESD reliability of the DUT. Most GaAs RF components are rated at 500 V HBM. Other practical requirements of the T/R switch include robustness with respect to antenna mismatch. Also, control voltage levels used to toggle the state of the switch must be available in the system. The turn-on and turn-off times typically must be less than about
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
73
10 ns to enable rapid transition between Tx and Rx modes, although specific values depend on the appplication.
4.2.2 Previous Work Board-level T/R switches typically use either PIN diodes or GaAs FETs as the switching elements. Switches using PIN diodes [17] usually have a low insertion loss, IL < 1 dB, and a high power handling capability, P 1dB > 35 dBm, at the cost of high static power consumption, Ps ~ 0.015 W. A simple diode based T/R switch is presented in Figure 4.4. Using appropriate control voltages, diodes, D1 and D2, are alternately switched on or off. The control voltages often need to be high, ~ 5−10 V, to ensure sufficient linearity. When switched on, diodes need to be biased with high currents to achieve to low series resistance. These requirements of a high current bias and a high control voltage makes diode switches unattractive for integration on silicon.
Vctrl1
Vctrl2
Antenna
RFC Tx
RFC Rx
D1
RFC
D2
Figure 4.4: Simplified schematic of a diode based T/R switch. The RF chokes (RFC) bias the diodes, D1 and D2, with DC current and provide a high impedance at the frequency of operation.
FET based T/R switches are typically implemented in a ‘series-shunt’ topology with FET devices as switches, as in shown in Figure 4.5 [15]. Transistors, M3 and M4, increase the isolation performance of the switch. GaAs FET switches are being increasingly preferred over PIN-diode switches due to their significantly lower static power consumption, typically less than 1 mW, and only a slightly worse IL of about 1.2 dB. An
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
74
additional advantage is that these switches can be designed with CMOS compatible control voltages. Antenna Vctrl
Tx Vctrl
M1 M3
Vctrl
M2 M4
Rx Vctrl
Figure 4.5: A ‘series-shunt’ T/R switch topology using FETs. Transistors, M3 and M4, improve the isolation performance.
Integrated CMOS T/R switches, using the series-shunt topology, typically suffer performance degradation at frequencies greater than about a gigahertz due to the substrate resistance and the parasitic source/drain junction capacitances. In order to decrease loss in the substrate, F.J-Huang [9] decreased the substrate resistance by placing ground connections as close to the transistors as possible. This design achieves an IL of 0.8 dB but suffers from the lower linearity, P1dB < 12 dBm, for control voltages less than Vdd. Performance degradation is observed at frequencies greater than 2 GHz, due to large parasitic source/drain capacitances. Recently, efforts have been made to eliminate substrate loss by increasing the substrate resistance to a very large value by blocking the p−-well implants for the switch transistors [46]. This design also suffers from limited power handling capability. Yamamoto [49] designed T/R switches for low-power applications with acceptable performance at higher frequencies. Due to limited linearity and inferior performance at high frequencies, integrated CMOS T/R switches have, so far, been an unattractive option. Narrowband switch designs using components such as inductors and transmission lines [14], have been investigated to overcome problems with parasitic capacitance effects and high control-voltage operation,
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
75
but none have been integrated in standard CMOS due to the low quality factor of on-chip passive components.
4.2.3 Switch Specifications The specifications for an integrated T/R switch used in a WLAN system at 5.2 GHz are summarized below in Table 4.1. The switch also must meet other criteria which include: 1. Protection of active devices against voltages greater than Vdd. 2. Minimize high temperature effects. 3. Low switch-on/switch-off times. 4. Robustness with respect to mismatch and large reflections at the antenna. Table 4.1: Target specifications for the T/R switch. Specification Parameter Operating frequency (GHz) Insertion Loss (dB) Return Loss (dB) Isolation (dB) Input Linearity: P1dB (dBm) ESD (HBM kV) Control Voltages (V) DC power (mW)
Target value 5.2 < 1.5 > 10 > 25 (Tx mode); > 15 (Rx mode) > 25 (Tx mode); > 10 (Rx mode) >2 0 < Vctrl < Vdd <1
4.3 Circuit Design 4.3.1 Schematic Figure 4.6 presents the circuit schematic of the proposed T/R switch. The switch is composed of a transmit path and a receive path as shown in the figure. The circuit is
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76
intentionally designed to be asymmetric in the Tx and Rx paths because the requirements in the two modes are quite different. Receive Path
L2
LNA & Rx M2
BPF C2a + Ant.
Rb2
C2b
Rb4
Vctrl INV M1 Transmit Path
Rb1
Rb3
PA & Tx C1
L1
Figure 4.6: Schematic for the CMOS T/R switch operating at 5.2 GHz.
M1 (W/L = 250 µm/0.18 µm) and M2 (W/L = 600 µm/0.18 µm) are multi-finger nMOS devices with 13-µm finger width. L1 (6 nH) and L2 (1.4 nH) are spiral inductors with ground shields. The spiral inductors are critical components of the switch, which have been optimized using the modeling tool developed in the previous chapter. The Q-factors for L1 and L2 are 8 and 13 respectively. Capacitors C1 (166 fF), C2a (550 fF), and C2b (550 fF) are laid out as metal-oxide-metal sandwiches using Metal-1 through Metal-6. Q-factors for the capacitors are estimated to be greater than 20. All resistors are used for biasing (~10 kΩ) and are fabricated with nonsilicided n +−polysilicon. The parasitic capacitance due to the pad is included in C2a while the drain capacitance of M2 is included in C2b. In CMOS LNA designs, the optimal input impedance from noise figure considerations could be less than 50 Ω. Although this prototype is designed to operate in a 50-Ω
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
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environment, the receive path design can be modified to match an LNA with a different input impedance without affecting the transmit performance. This design change is described in section Section 4.3.2.2. Description of the switch operation in the Tx and Rx modes is described in detail in Section 4.3.2 along with a description of the ESD operation.
4.3.2 Operation 4.3.2.1
Transmit Mode
In the transmit mode, Vctrl is pulled up to Vdd, causing M1 and M2 to operate in the linear region with low on-resistance. An approximate equivalent circuit in this mode of operation is presented in Figure 4.7. . BPF + Ant.
Rrx
rdsM1 CsbM1
Rtx1
PA & Tx CdbM1
RsubM1
Figure 4.7: Simplified small-signal equivalent circuit in transmit mode. With the drain of M2 pulled to Gnd, L2 and C2a form a parallel tank that resonates at 5.2 GHz. This causes the receive path to present a high impedance, assuring that the signal leakage to the receive section is small and most of the power is transmitted to the antenna. In the small signal equivalent circuit of Figure 4.7, this impedance is represented by Rrx, whose value, as estimated from (4.1), is 500 Ω. Similarly, the L1-C1 pair, designed to resonate at 5.2 GHz, makes the substrate node of M1 high impedance at 5.2 GHz thus
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78
reducing loss in the substrate. In Figure 4.7, this is represented by Rtx1, whose value, as estimated from (4.2), is 2 kΩ. When combined with the large gate bias resistor, Rb1, M1 behaves like a ‘floating’ pass-gate. This minimizes substrate loss and allows a large ac voltage to be applied at the Tx port without allowing any two terminals of M1 to develop a differential voltage larger than Vdd. Since the drain of M1 is biased to ground through resistor Rb3, and its source is grounded through M2, M1 operates in the triode region and its on-resistance is minimized. The receiver is adequately isolated from the large voltages at the antenna as the drain of M2 is pulled to ground. Despite the L1C1-tank, there is a layout dependent parasitic resistance from the substrate of M1 to the nearest available ground contact to substrate as illustrated by RsubM1 in Figure 4.7. In order to maximize this resistance, the nearest ground contacts are placed at least 200 µm away from M1. Rrx = Qrx′ ⋅ ω ⋅ L 2 ; Rtx 1 = Q′ ⋅ ω ⋅ L 1 ; 4.3.2.2
ω ⋅ L2 Qrx′ = ------------------------------------------R ( L 2 ) + rds ( M 2 ) ω ⋅ L1 Q′ = -------------R1
(4.1)
(4.2)
Receive Mode
In the receive mode, Vctrl is set to Gnd, thereby turning off M1 and M2. Under these conditions, M1 isolates the transmitter from the antenna, while the π-circuit consisting of C2a-L2-C2b matches the antenna to the LNA. An approximate equivalent circuit of the switch in the receive mode is presented in Figure 4.8. Resistors, Rb3 and Rb4, bias the drain nodes of M1 and M2 to Vdd, thus minimizing the parasitic drain capacitance of the respective transistors. For matching to LNA input impedances which are less than 50 Ω, the circuit of Figure 4.9 is effective. The additional inductance L2b resonates with capacitor C2b at the frequency of operation. The L-match of C 2a -L 2 then matches the lower LNA input impedance to the 50-Ω antenna. The receive path in this proposed design makes a narrowband match compared to the broadband match that was achieved by the 50-Ω
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
79
prototype described in the preceding paragraph. The additional inductor, L2b, does not change the transmit performance of the switch or its ESD reliability. LNA &Rx L2 BPF + Ant.
C2b
C2a
PA & Tx CsbM1
CdbM1
Rtx1
50 Ω
RsubM1
Figure 4.8: Simplified small-signal equivalent circuit during receive mode with a 50-Ω termination for the Tx port.
Receive Path BPF C2a + Ant.
L2
LNA & Rx L2b
M2
Rb2
C2b
Rb4
Vctrl INV M1 Transmit Path
Rb1
Rb3
PA & Tx C1
L1
Figure 4.9: Proposed schematic for LNA input impedance less than 50 Ω.
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
4.3.2.3
80
ESD Considerations
ESD is a major reliability concern with CMOS circuits. An ESD event can occur between any two pins of a chip. It can also be of positive or negative polarity. Most chips are designed with a very good ESD path between Vdd and Gnd which does not interfere with normal circuit operation. An ESD event between any two pins, Pin1 − Pin2, is typically designed to be a cascade of Pin1 → Gnd → Pin2 . Thus, for a T/R switch integrated with the LNA and PA, we only need to consider an ESD event between the antenna pin and a Gnd pin. ESD protection circuits for high-frequency I/O pins are difficult to design due to requirements of very low parasitic capacitance. Furthermore, ESD protection circuits for this application must allow very large signal swings at the output. Diodes are unsuitable for ESD protection in switch designs because they need to be reverse-biased at voltages greater than Vdd to ensure linearity. The proposed design includes ESD protection within the switch, thus eliminating the need for additional ESD circuits. This is achieved in the following manner. The drains of both devices, M1 and M2, are tied together, and therefore are subjected to the same ESD stress. Bipolar-assisted breakdown of M2 can be triggered at about 6 V. It handles much larger ESD currents as compared to diode breakdown and also allows better heat dissipation. To further enhance the breakdown characteristics of M2, a resistor, RESD ~100 kΩ, is connected between its gate and Gnd which forces a uniform gate-assisted bipolar breakdown [47] in case of an ESD event. The low substrate resistivity, ρ sub = 10 Ω-cm, for bulk substrates is expected to further help the ESD performance. Since the typical reverse breakdown voltage of diodes in a CMOS process is about 10 V , the breakdown of M2 is the preferred breakdown mechanism during an ESD event.
4.3.3 Layout A standard digital 0.18 µm CMOS technology from the Taiwan Semiconductor Manufacturing Corporation, using six metal layers, was used to fabricate a prototype for
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81
the switch. The die-micrograph of the prototype is presented in Figure 4.10. M 1 is designed with a square geometry to maximize the substrate resistance. In order to ensure that the interconnect parasitics are estimated accurately, the interconnects are laid out as strip lines; each consisting of a wide signal line running over a ground line. The distance from any spiral inductor to the nearest pad is at least 200 µm, thus minimizing loss due to eddy currents induced in the metal pad. Metal structures used to meet coverage rules are formed by a grid of 1x10 µm2 metal strips separated from each other by 1 µm. In order to minimize eddy current losses, the strips are laid out so that the longer dimension is orthogonal to the nearest inductor edge. The nearest ground connection to M1 also is at least 200 µm away to maximize the parasitic substrate resistance. Capacitors, C2a and C2b, can be trimmed by laser to fine tune the circuit, if necessary.
~ 1 mm
L1
p+pickup Antenna
C1
C2a C2b
M1
Rx
~ 1 mm
M2
Tx
L2
Vctrl Gnd Figure 4.10:
Vctrl
Die micrograph of CMOS T/R switch. The die is 1 mm on each side and is tested by use of RF probes. The chip within the area occupied by the pads is 0.56 mm2.
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82
4.4 Switch Performance The performance of the protoype has been measured at the I/O pads, viz. Tx, Rx, and Antenna, using Cascade Microtech’s ACP-40W GSG probes with 150-µm pitch, while the dc control voltages were supplied using an SGS probe. The unused port in any given measurement is terminated by a 50-Ω load.
4.4.1 Small-signal Measurements S-parameter measurements to obtain small-signal IL, isolation, and return loss were carried out using the HP8510 Network Analyzer. The measurement setup is shown in Figure 4.11. Full two-port calibration using Impedance Standard Substrates (ISS) from Cascade Microtech was performed to correct for the effects of the probes and cables. Further corrections, such as contact resistance elimination, were implemented by making use of short, open, and thru test-structures incorporated into the switch design. Pad capacitance subtraction was carried out for the antenna pad but not for Tx and Rx pads since these are absent in an integrated transceiver.
HP 8510 Network Analyzer
Port 2
On-chip
Port 1 Antenna Tx
T/R Switch
Rx
50Ω
Figure 4.11: S-parameter measurement setup for IL, isolation and return loss in the Tx mode. In the Rx mode, Port 1 is connected to the antenna, Port 2 is connected to Rx while Tx is terminated with 50 Ω.
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
83
0 S21
S-parameters (dB)
-5
S22
-10
S11
-15 -20 -25 -30
Isolation from Tx to Rx
-35 -40
0
1
2
3
4 5 6 7 Frequency (GHz)
8
9
10
Figure 4.12: Measured S-parameters and isolation in the transmit mode.
0 S21
S-parameters (dB)
-5 S11
-10
S22
-15 -20 -25
Isolation from antenna to Tx
-30 -35
0
1
2
3
4 5 6 7 Frequency (GHz)
8
9
10
Figure 4.13: Measured S-parameters and isolation in the receive mode.
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
84
Measured results given in Figures 4.12 and 4.13, show that the IL at 5.2 GHz, as given by S21, is 1.5 dB and 1.4 dB for the transmit and receive mode, respectively. In the transmit mode, the measured isolation is 30 dB, assuring adequate protection of the LNA from the high power levels transmitted by the PA. Isolation measured in the receive mode is 15 dB, which is sufficient as the received power is quite low. The return losses, S11 and S22, in both modes are greater than 10 dB indicating acceptable matching.
4.4.2 Power Handling Capability Linearity of the switch is measured using the HP83711 signal generator along with an external power amplifier as shown in Figure 4.14. The output signal is measured by a HP8653 spectrum analyzer. As shown in Figure 4.15, the linearity, measured as P1dB, is 28.0 dBm and 11.5 dBm in the transmit mode and receive mode, respectively. Using the same setup, isolation performance is investigated for high input powers. Measurements results in Figure 4.16 confirm that isolation remains at its small-signal value up to input powers of 8 dBm and 30 dBm in the Rx and Tx mode, respectively.
HP 8563 Spectrum Analyzer
On-chip Antenna HP 83711 Signal Generator
PA
Tx
T/R Switch
Rx
50Ω
Figure 4.14: Linearity measurement setup in the Tx mode. The unused Rx port is terminated by a 50-Ω load.
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
85
40 Rx mode
30
Tx mode
Pout (dBm)
20 10 0 -10 -20 -20
P1dB Rx mode
-10
0
10 Pin (dBm)
P1dB Tx mode
20
30
40
Figure 4.15: Measured linearity of T/R switch in Tx and Rx modes.
-10
Isolation (dB)
Isolation from Antenna to Tx: Rx mode
-20
-30 Isolation from Tx to Rx: Tx mode
-40 -20
-10
0
10 Pin (dBm)
20
30
40
Figure 4.16: Measured isolation under high input powers up to P1dB in Tx and Rx modes. No degradation is observed up to P1dB in the Tx mode.
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
2
86
Vdd Vgd Vgs
Voltage (V)
1 Vdb 0 Vds Vsb
-1 −Vdd -2 9.80
9.85
9.90 Time (ns)
9.95
10.00
Figure 4.17: Simulated voltage waveforms for M1 in Tx mode with Pin = 27.5 dBm and Pout = 25.8 dBm. Note that none of the voltages exceed +/− 1.8 V
4.4.3 Reliability Testing ESD reliability of the prototype was evaluated by subjecting it to HBM stressing conditions. Although M 1 and M 2 have silicided, minimum geometry source/drain junctions, the prototype achieved an ESD rating of 4 kV as measured by a ZapMasterTM ESD tester. This is attributed to the 100-kΩ resistor from gate of M2 to Gnd along with the lightly doped substrate which enhances the bipolar assisted breakdown behavior of M2. Another reliability concern for the switch is mismatch at the antenna. When the antenna port is open-circuit, the signal is completely reflected and the switch is subject to almost twice the nominal voltage levels. Figure 4.17 shows simulation results with antenna port open-circuit. The figure shows that the voltage difference between any two terminals of M1 during transmit mode does not exceed Vdd for a signal voltage of 15 V which is equivalent to 27.5 dBm power under matched conditions. These results suggest sufficient reliability of the switch under antenna mismatch conditions. Verification of these
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
87
simulations using measurements was not done due to the difficulty of measuring the voltages at 5 GHz without disturbing the circuit operating conditions.
4.4.4 Substrate Cross-talk Results The substrate of M1 ‘floats’ at 5.2 GHz, and hence is a source/sink for noise in the substrate. To evaluate this, S-parameters were measured at a 10x50 µm2 p+−pickup in p −−well, seen in the die-photo of Figure 4.10, which is 300 µm away from M 1 . The p+−pickup is surrounded by a p+−guard ring. This structure emulates the substrate contact and p−−well for an amplifier block nearby. During measurements, the antenna port is kept open-circuit to maximize the amount of substrate signal injection. The measured results from Figure 4.18 for substrate crosstalk confirm that substrate crosstalk is low with only −50 dB S21 at 5.2 GHz. Since inductive crosstalk is typically much larger, about −40 dB [50], the substrate path does not degrade the overall performance.
4.4.5 Overall Performance Evaluation The comparison of measured result with simulations is shown in Table 4.2. The mismatch in the measured and simulated linearity is attributed to the lack of good large-signal models for MOSFETs at RF. Current BSIM3 models for MOS devices do not include parasitic bipolar action. Parasitic bipolar action for the MOSFETs is possibly enhanced in this design due to the high substrate resistance at RF. If this is the case, it would explain why the measured one dB compression points are significantly lower than the predictions. Table 4.3 compares performance of the prototype with that of commercially available parts. When compared to the PIN diode part, this switch has significantly lower static power consumption, better isolation, and similar power handling capability with only a slight increase in IL. Compared with its GaAs counterpart, the prototype achieves comparable specifications with highly improved robustness against ESD. The switch also
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88
shows 40x greater power handling capability as compared to all known CMOS switches described to date [9, 46, 49].
p+ pickup
Source
10x50 µm2
M1
n+
p− substrate
p+
d = 300 µm
(a)
Substrate Crosstalk (dB)
-40
from Tx to p+ pickup (Tx mode)
-50
-60
-70
-80
0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz) (b) Figure 4.18: Substrate crosstalk measurements. (a) Measurement cross-section. (b) Measured cross-talk data.
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
Table 4.2:
89
Comparison of simulation and measured results for the T/R switch.
Specifications Insertion Loss (dB) Return Loss, S11 (dB) S22 (dB) Isolation (dB) P1dB (dBm) Frequency (GHz)
Tx mode Simulation Measurement 1.6 1.52 28 30 26 33 32 30 35.0 28.0 5.2 5.2
Rx mode Simulation Measurement 1.5 1.42 13 11 19 25 17 15 19.0 11.5 5.2 5.2
Table 4.3: Comparison of this work to commercially available board-level components. Specifications Insertion Loss (dB) Isolation (dB) P1dB (dBm) Return Loss (dB) Control Voltage (V) DC power (W) ESD HBM (kV) Frequency (GHz)
PIN Diode [17] Tx and Rx 1.0 15 30.0 14 ±8
MESFET [48] Tx and Rx 1.2 26 31.0 15 0−3
This Work Tx mode 1.5 30 28.0 30 0−1.8
This Work Rx mode 1.4 15 11.5 11 0−1.8
~0.015 >2 5.6
< 0.001 > 0.25 5.2
< 0.001
0 >4 5.2
Chapter 4: Transmit-Receive Switch using Inductive Substrate Bias
90
4.5 Summary In this chapter, a narrow-band T/R switch illustrates application of the inductive substrate bias technique. It also enables evaluation of the high-frequency spiral inductor model developed in the previous chapter in a circuit environment. The 5.2-GHz switch is the first resonant design to be implemented in a 0.18 µm six-metal CMOS technology. The inductive substrate bias technique using on-chip spiral inductors significantly enhances the power handling capability of the switch. The prototype achieved a power handling capability which is about 40x its CMOS counterparts, and an overall performance level comparable to its commercially available discrete counterparts. Simultaneously, it increases the level of RF transceiver integration by including a matching circuit which enables the LNA and PA to be matched independently. As the comparison between measurements and simulations show, the spiral inductor model developed previously allows prediction of circuit behavior at high frequencies. This T/R switch can be designed for other commercially relevant frequencies of interest such as 0.9, 1.8−1.9, and 2.4 GHz.
Chapter
5
Conclusions
5.1 Summary Mobile wireless devices have experienced an explosive growth in the last few years, a trend that is expected to continue. The drive for reduced power, lower cost and a smaller form factor continue to motivate innovations in wireless products. Heavily integrated CMOS RF systems are beginning to achieve satisfactory levels of performance and are expected to provide a much needed boost for the consumer wireless market. With silicon-based CMOS technology improving continuously, new techniques and architectures are being actively studied. The inductive substrate bias technique is an example of one such enabling technique. In this research, it is shown that this technique can decrease the system cost by decreasing the number of board-level components without sacrificing performance. Chapter 2 studies various switching elements. It is shown that standard CMOS devices do not function well as a switch at RF due to substrate parasitics. Off-chip components such as PIN diodes require static power to achieve the required performance. GaAs MESFETs do not enable a low-cost, small form-factor solution. Biasing the substrate of the MOSFET using a tuned LC-tank significantly improves the performance of MOSFET as a switch in narrowband applications. The technique allows high voltages to be applied at the terminals of the MOSFET without causing any reliability concerns. Thus, the chapter presents the feasibility of RF switches using standard CMOS. Chapter 3 conducts a detailed study of spiral inductors on various doped substrates at RF. Physics based compact models, developed to explain and predict the principal phenomena that affect the performance of the spiral inductor at high frequencies, are 91
Chapter 5: Conclusions
92
verified and consolidated in a inductor design and optimization tool. Apart from its utility in designing spiral inductors for RF circuits in general, the compact model enables accurate simulations of the proposed inductive substrate bias technique. Chapter 4 presents a transmit-receive switch design to illustrate the benefits of the inductive substrate bias technique. Measured results show that the performance of the prototype is comparable to its board-level counterparts in the market. The switch shows a power handling capability about 40x greater than other CMOS switches described in literature. The simulated and measured small-signal performance of the switch allow another verification for the spiral inductor model. Since most moderate−high power transceivers, 10 dBm < PTx < 25 dBm, have T/R switches off-chip, this design provides a practical on-chip alternative. The key contributions of this research are summarized as follows: 1. The inductive substrate bias technique which uses passive components to bias the substrate of a MOSFET, thereby increasing its linearity and reducing its parasitics. 2. New compact models for the principal phenomena which degrade the performance of an integrated spiral inductor, viz. PGS parasitics, skin/proximity effect, and eddy current induced substrate loss. 3. An improved PGS design which minimizes parasitics. 4. A modeling tool for design and optimization of spiral inductors on a variety of doped substrates. 5. A new T/R switch topology implemented and verified in a standard CMOS technology, which includes practical, built-in ESD protection for the T/R switch which does not affect performance adversely.
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93
5.2 Future Work 5.2.1 Improvements in T/R Switch Performance The main limitation of the current T/R switch design is the area occupied by the MOSFET with inductive substrate bias. The additional area leads to longer interconnects which also result in greater insertion loss. Since the main purpose of the isolated MOSFET is to maximize the parasitic substrate resistance, narrow n-well rings placed in an annular configuration around the MOSFET and biased separately to Vdd through large resistors, R ~ 10 kΩ , can be expected to achieve the same result. Triple-well technology is another alternative which is expected to increase the parasitic substrate impedance of the nMOS device with an inductive substrate bias. Implementation of these options to increase the substrate impedance whould decrease the total area occupied by the T/R switch and improve its performance. Improvements in the quality factor of spiral inductor designs will improve the performance of the T/R switch as well. Using a high resistivity substrate along with a PGS implies that the substrate related losses due to electric fields and magnetic fields can be neglected. Skin and proximity effects are the main sources of Q degradation at high frequencies. Use of improved inductor design techniques, such as those suggested by Tiemejer [31], can significantly decrease losses in the metal due to skin and proximity effects. Finally, using thicker top metal or copper metallization can also improve the Q-factor leading to better overall switch performance.
5.2.2 Other Applications for the Inductive Substrate Bias Technique The inductive substrate bias technique has additional applications in a RF transceiver. As shown in Chapter 2, the substrate bias technique can decrease the parasitic drain junction capacitance. Additionally, it can also improve the quality factor of the parasitic drain junction capacitance. This suggests that the technique might be very useful in a switched capacitor, voltage-controlled oscillator (VCO). As shown in Figure 5.1, devices M3 and
Chapter 5: Conclusions
94
M 4 switch capacitors, C 1 and C 2 , in and out of operation to tune the VCO center frequency. The devices must provide very low on-resistance and a very low off-state parasitic capacitance at the drain in order to permit optimal VCO performance and tuning range. Biasing the substrates of M3 and M4 using the inductive substrate bias technique can decrease the drain capacitance by about 30 − 50% as shown in Figure 2.6 of Chapter 2. The improved drain-capacitance quality factor would result in better phase noise for the oscillator. There are several other locations in RF transceiver designs where the loading and quality of the parasitic drain junction capacitor are limiting factors, e.g., at the output of PA. Further research is needed to quantify the utility of this technique in such extended applications.
C1
M4
C2
M2
M1
M3
Figure 5.1: VCO using switched capacitors, C1 and C2, to increase tuning range. Devices M3 and M4 can use the inductive substrate bias technique to enhance performance.
5.2.3 Inductor and Transformer Modeling Spiral indcutors using octagonal and circular geometries have better area to length ratio as compared to a square spiral. This results in an improvement of about 10% in terms of their quality factor. The compact models developed for the square spiral inductor can be extended to include different geometries such as octagonal or circular.
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95
Transformers can be used for the purposes of isolation and power combining at RF. Transformer usage has been largely avoided in the past due to its complicated layout and the difficulty in predicting performance. With a greater understanding of spiral inductors and the enhanced capabilities of electromagnetic simulation tools, transformer usage can be exploited. Compact models for transformers need to be developed for accurate circuit simulations. The compact models for the spiral inductor developed in this research can be extended to model transformers.
5.2.4 Large Signal MOSFET Modeling at RF Measured results of the T/R switch operating at large signal input powers, P > 25 dBm, are not in agreement with simulated predictions. This is attributed to the increased substrate impedance resulting in increased parasitic BJT action at lower voltages. Furthermore, in connection with parasitic BJT action, non-quasi-static phenomena such as base-charge recombination become important. Existing BSIM3V3 models do not include these effects. Both of these effects are known to be important in power amplifiers with high-power outputs. The same phenomena need to be modeled in the T/R switch for accurate prediction of its large-signal performance. Accurate large-signal models for MOSFETs at RF will enable improved simulation of all blocks in the transceiver during high-power operation.
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96
Appendix A Sample Calculation of Eddy Current Loss In this example, a sample calculation is presented for computing the eddy current induced substrate loss in transmission lines with a finite width W. As explained previously in Section 3.5.2.2, the current density is assumed to be uniform in the vertical direction, and non-uniform laterally. The calculations are presented for the case that W < P−W < P where P is the pitch. Under these conditions, two possibilities exist based on the value of the skin depth in the substrate, δsub. These are presented as case 1(a) and 1(b). Case 1(a) W < 2δsub < P−W The lateral current density profile in the substrate, associated with the signal line, is shown in Figure A.1 below. Isig
Signal
δsub
W
W Jpk |Jsub|
2δsub−W
Figure A.1: Lateral substrate current density profile for the case where W < 2δsub < P−W.
97
x
Appendix A: Sample Calculation of Eddy Current Loss
98
Peak substrate current density, Jpk, is calculated by using the first assumption of Section 3.5.1 in (A.1).
∫
I sig =
J sub ( x, y ) ⋅ dx dy = δ sub ⋅
Substrate
∫
J sub ( x ) ⋅ dx
(A.1)
Substrate
The integral of the substrate current density with respect to x is seen from Figure A.1 as the area under the shaded trapezoid. Thus we get the result in (A.2), in terms of Jpk, the peak current density in the substrate. 2
I sig = 2J pk ⋅ δ sub
(A.2)
The net power loss in the substrate is given by (A.3) and simplified to yield (A.5) Power Loss ( W ⁄ m ) = P sub =
∫
2
ρ sub ⋅ J sub ( x, y ) ⋅ dx dy
(A.3)
Substrate
P sub =
2 J pk
W x 2 J ⋅ ----- dx ⋅ ρ sub ⋅ ( 2δ sub – W ) ⋅ δ sub + 2 ρ sub ⋅ δ sub ⋅ pk W 0
∫
2 2 W P sub = I sig ⋅ R sub = J pk ⋅ ρ sub ⋅ 2δ sub – ----- ⋅ δ sub 3
(A.4)
(A.5)
Using (A.2) in (A.5), we get Rsub in (A.6) for this case. W - ρ sub 2δ sub – ---3 R sub = -------------- ------------------------ 2 2δ sub 2δ sub
(A.6)
Case 1(b) 2δsub < W The lateral current density profile is given by Figure A.2. Using the profile shown, the total substrate current, Isig, is given in terms of the peak current density in the substrate, Jpk, by (A.7) as done for case 1(a). Similarly, as in case 1(a) above, the power loss is calculated to give the effective substrate resistance, Rsub.
Appendix A: Sample Calculation of Eddy Current Loss
∫
I sig =
99
J sub ( x, y ) ⋅ dx dy = δ sub ⋅ Area ( Trapezoid ) = J pk ⋅ δ sub ⋅ W (A.7)
Substrate
Isig
Signal
δsub
x
W 2 δsub
Jpk |Jsub|
W− 2δsub
Figure A.2: Lateral substrate current density profile for the case where 2δsub < W.
Power Loss ( W ⁄ m ) = P sub =
∫
2
ρ sub ⋅ J sub ( x, y ) ⋅ dx dy
(A.8)
Substrate
2 P sub = J pk ⋅ ρ sub ⋅ ( W – 2δ sub ) ⋅ δ sub + 2 ρ sub ⋅ δ sub ⋅
2δ sub
x 2 J ⋅ ------------- dx (A.9) pk 2δ sub 0
∫
2δ sub 2 2 P sub = I sig ⋅ R sub = J pk ⋅ ρ sub ⋅ W – -------------- ⋅ δ sub 3
(A.10)
Using (A.7) in (A.10) we get Rsub in (A.11) for this case. sub W – 2δ -------------- ρ sub 3 R sub = ---------------- ------------------------- W δ sub W
(A.11)
Appendix A: Sample Calculation of Eddy Current Loss
100
Appendix B Eddy Current Induced Substrate Loss for a Coplanar Transmission Line The following equations are the result of calculations of substrate loss using profiles of eddy currents proposed in Chapter 3. The signal and ground lines have a width W and pitch P. The transmission line is at a height h above the substrate. Two possible geometric cases arise, depending on the relationship between W and P . The results for each of these cases are given below. For frequencies at which the thickness of the substrate is lesser than the skin depth in the substrate, the substrate resistance must be scaled by a factor of ‘tsub/δsub’. The expression for η is given by (3.19) while a value of 3.3 for α is suitable. Case I) W < P-W < P Depending on the frequency, and hence the value of 2δsub, one of the five sub-cases, shown below in Figure A.3, determine the eddy current loss per unit length.
Case 1 0
2 W
3 P-W
4 P
5 P+W
2δsub
Figure B.1: Value of 2δsub with respect to the other geometric parameters determines the substrate loss for case I.
case I.1) 2δsub < W
101
Appendix B: Eddy Current Induced Substrate Loss for a Coplanar Transmission Line 102
sub 2δ W – 2δ -------------- ηρ sub sub 3 R sub = --------------- --------------------------------------------- 2 2 W αδ sub
(B.1)
case I.2) W < 2δsub < P-W ηρ sub W R sub = --------------- 1 – -------------- 2 6δ sub αδ sub
(B.2)
case I.3) P-W < 2δsub < P 3 ηρ sub W 4l R sub = ------------------ 2δ sub – ----- – ----------- 3 3 3W 2 2αδ
2δ sub – ( P – W ) ;l = ---------------------------------------2
(B.3)
sub
case I.4) P < 2δsub < P+W 3 ηρ sub W 4l R sub = ------------------ D avg – ----- – ----------- 3 3 3W 2 2αδ sub
( P + W ) – 2δ sub ;l = ---------------------------------------2
(B.4)
case I.5) P+W < 2δsub ηPρ sub W R sub = ------------------- 1 – ------- 3 3P 2αδ sub
(B.5)
Case II) P−W < W < P
Case 1 0 P−W
2
3 W
4 P
5 P+W
2δsub
Figure B.2: Value of 2δsub with respect to the geometric parameters determines the substrate loss for case II.
case II.1) 2δsub < P−W
Appendix B: Eddy Current Induced Substrate Loss for a Coplanar Transmission Line 103
sub 2δ W – 2δ -------------- ηρ sub sub 3 R sub = --------------- --------------------------------------------- 2 2 W αδ sub
(B.6)
case II.2) P-W < 2δsub < W 2δ sub – ( P – W ) ;l = ---------------------------------------2
3 2ηρ sub 2δ sub l R sub = ----------------------- W – -------------- – -------------- 2 2 3 W αδ sub 3δ sub
(B.7)
case II.3) W < 2δsub < P 3 ηρ sub W 4l R sub = ------------------ 2δ sub – ----- – ----------- 3 3 3W 2 2αδ sub
2δ sub – ( P – W ) ;l = ---------------------------------------2
(B.8)
case II.4) P < 2δsub < P+W 3 ηρ sub W 4l R sub = ------------------ P – ----- – ----------- 3 3 3W 2 2αδ sub
( P + W ) – 2δ sub ;l = ---------------------------------------2
(B.9)
case II.5) P+W < 2δsub ηPρ sub W R sub = ------------------- 1 – ------- 3 3P 2αδ sub
(B.10)
Appendix B: Eddy Current Induced Substrate Loss for a Coplanar Transmission Line 104
Appendix C Eddy Current Induced Substrate Loss for a Square Spiral Inductor The following equations are the result of calculations of substrate loss using profiles of eddy currents proposed in Chapter 3. As explained previously, multiturn inductors are treated as a single turn inductor with width given by Weff and an average diameter, Davg. The inductor is assumed to be square and at a height h above the substrate. Two possible geometric cases arise, depending on the relationship between Weff and Davg . The results for each of these cases are given below. For frequencies at which the thickness of the substrate is lesser than the skin depth in the substrate, the substrate resistance must be scaled by a factor of ‘tsub/δsub’. The expression for η is given by (3.19) while a value of 3.3 for α is suitable. Case I) Weff < Davg-Weff < Davg Depending on the frequency, and hence the value of 2δsub, one of the five sub-cases, shown below in Figure A.3, determine the eddy current loss.
Case 1 0
2 Weff
3 Davg-Weff
4 Davg
5 Davg+Weff
Figure C.1: Value of 2δsub with respect to the other geometric parameters determines the substrate loss for case I.
105
2δsub
Appendix C: Eddy Current Induced Substrate Loss For a Square Spiral Inductor
106
case I.1) 2δsub < Weff sub 2δ W – 2δ -------------- 2ηN D avg ρ sub sub eff 3 R sub = -------------------------------------- ---------------------------------------------------- 2 2 W eff αδ sub 2
(C.1)
case I.2) Weff < 2δsub < Davg-Weff 2 W eff 2ηN D avg ρ sub R sub = -------------------------------------- 1 – -------------- 2 6δ sub αδ sub
(C.2)
case I.3) Davg-Weff < 2δsub < Davg 2 3 W eff ηN D avg ρ sub 4l R sub = ----------------------------------- 2δ sub – ------------ – ------------------ 3 2 3 αδ 3W sub
2δ sub – ( D avg – W eff ) ;l = ------------------------------------------------------- (C.3) 2
eff
case I.4) Davg < 2δsub < Davg+Weff 2 3 W eff ηN D avg ρ sub 4l R sub = ----------------------------------- D avg – ------------ – ------------------ 3 2 3 αδ sub 3W eff
( D avg + W eff ) – 2δ sub ;l = ------------------------------------------------------- (C.4) 2
case I.5) Davg+Weff < 2δsub 2 2
ηN D avg ρ sub W eff R sub = ----------------------------------- 1 – --------------- 3 3D avg αδ
(C.5)
sub
Case II) Davg−Weff < Weff < Davg
Case 1 0 Davg−Weff
2
3 Weff
4 Davg
5 Davg+Weff
2δsub
Figure C.2: Value of 2δsub with respect to the geometric parameters determines the substrate loss for case II.
Appendix C: Eddy Current Induced Substrate Loss For a Square Spiral Inductor
107
case II.1) 2δsub < Davg−Weff sub 2δ W – 2δ -------------- 2ηN D avg ρ sub sub eff 3 R sub = -------------------------------------- ---------------------------------------------------- 2 2 W eff αδ sub 2
(C.6)
case II.2) Davg-Weff < 2δsub < Weff 2 3 2δ sub 4ηN D avg ρ sub l R sub = -------------------------------------- W eff – -------------- – -------------- 2 2 3 αW eff δ sub 3δ sub
2δ sub – ( D avg – W eff ) ;l = ------------------------------------------------------- (C.7) 2
case II.3) Weff < 2δsub < Davg 2 3 W eff ηN D avg ρ sub 4l R sub = ----------------------------------- 2δ sub – ------------ – --------------- 3 2 3 αδ 3W sub
2δ sub – ( D avg – W eff ) ;l = ------------------------------------------------------- (C.8) 2
eff
case II.4) Davg < 2δsub < Davg+Weff 2 3 W eff ηN D avg ρ sub 4l R sub = ----------------------------------- D avg – ------------ – --------------- 3 2 3 αδ sub 3W eff
( D avg + W eff ) – 2δ sub ;l = ------------------------------------------------------- (C.9) 2
case II.5) Davg+Weff < 2δsub 2 2
ηN D avg ρ sub W eff R sub = ----------------------------------- 1 – --------------- 3 3D avg αδ sub
(C.10)
Appendix C: Eddy Current Induced Substrate Loss For a Square Spiral Inductor
108
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