USO0RE41751E
(19) United States (12) Reissued Patent
(10) Patent Number:
Heishi et al. (54)
(45) Date of Reissued Patent:
INSTRUCTION CONVERTING APPARATUS USING PARALLEL EXECUTION CODE
4,611,281 A 4,785,393 A 4,858,105 A
(75) Inventors: Taketo Heishi, Osaka (JP); Tetsuya _
-
,
Assignee: Panasonic Corporation, Osaka (JP)
(21) (22)
Appl. N0.: 10/720,030 Filed: Nov. 24, 2003
Relssue of:
an a e
5,452,461 A 5,488,710 A
* *
5,901,301 A
9/1995 Umekita et a1. ..... .. 717/149 1/1996 Sato etal. ................. .. 711/125
5/1999 Mt
03053325 03447021
3/1991 6/1991
JP
05-289870
11/1993
JP
09'026878
1/1997
6,324,639
Issued:
Nov. 27, 2001
Primary ExamineriEddie P Chan
Appl. No: Filed;
09/280,777 Mar, 29, 1999
Assistant Examineriwilliam B Partridge (74) Attorney, Agent, or FirmiMcDermott Will & Emery
(30)
LLP
Foreign Application Priority Data
(57) Mar. 30, 1998
(JP)
Apr. 8, 1998
58 (
t l.
* cited by examiner
(64) Patent N0.:
(52)
.
a Suo e a FOREIGN PATENT DOCUMENTS
JP JP
Related US. Patent Documents
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References Cited
(56)
ABSTRACT
10-083368
A processor can decode Short instructions With a Word
length equal to one unit ?eld and long instructions With a Word length equal to tWo unit ?elds. An opcode of each kind of instruction is arranged into the ?rst unit ?eld assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to
the ?rst unit ?eld to the s-ltA unit ?eld in the parallel execu tion code, and the long instruction is assigned to the s”’ unit ?eld to the s+k—1 th unit ?eld in the same P arallel execution
code.
U.S. PATENT DOCUMENTS 3,955,180 A
*
5/1976 Hiitle ........................ .. 703/26
50 Claims, 29 Drawing Sheets
SUPPLYING 20
32
EXECUTING UNIT
US. Patent
Sep. 21, 2010
Sheet 1 0129
US RE41,751 E
BACKGROUND ART FIG. 1A LONG INSTRUCTION
SHORT INSTRUCTION
I UNITI I UNIT2 | FIG. 1B UNIT 1
UNIT 2
UNIT 3
| UNITlO | UNITll guNI'rlz | UNIT 13 I UN1T14
UNIT 15
UNIT 16 E UNIT 17
mm 1
FIG. 1C UNITI
UNIT2 IUNIT3
PARALLEL
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dNIT4 | UNITS
UNITGI
LONG INSTRUCTION I LONG INSTRUCTION ILONG INSTRUCTION? UNIT? UNIT8 IUNIT9 IUNITIO UNl‘Tll I LONG INSTRUCTION ISHORT IIISIRUCIIONI LONG INSTRUCTION a UNITIZ UNIT13 | UNIT14 UNITIS I UNI'I‘I6 | LONG INSTRUCTION I LONG INSTRUCTION IIIIORTIIISIRIICIDNE UNIT 17 I UNIT 18 UNIT 19 UNIT 20 UNIT 21 I SHIRTI‘ISIRUCIIUI LONG INSTRUCTION LONG INSTRUCTION
UNIT 22
UNIT 23 I UNIT 24 I UNIT25
LONG INSTRUCTION SHORT INSIIIUCIIOII ‘HUIII’IIIIIICIII-‘I
UNIT 26 UNIT 27 I UNIT 28 UNIT 29 SHORTINIIIIUCIIIII SHOII’I INSIRII'II LONG INSTRUCTION
UNIT 30 UNIT31 UNIT 32 I UNIT 33 ISHORIIIIIRUCIION LONG INSTRUCTION 'IIOIIIIIIIIIICIIII
US. Patent
Sep. 21, 2010
Sheet 2 0f 29
US RE41,751 E
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US. Patent
Sep. 21, 2010
FIG. 3A
Sheet 3 0f 29
US RE41,751 E
BACKGROUND ART I} UNIT Q [IEUE 50
UNIT 1
UNIT 2
UNIT 3
REGISTER B
INSTRUCTION REGISTER
INSTRUCI'IO DECODER
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US. Patent
Sep. 21, 2010
Sheet 4 0f 29
US RE41,751 E
FIG. 4
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US. Patent
Sep. 21, 2010
Sheet 5 0f 29
US RE41,751 E
FIG. 5A SUPPLYING OF INSTRUCTIONS FROM THE INSTRUCTION
FETCH UNITTO THE INSTRUCTION BUFFER
UNITI
um'rz
UNIT3
UNIT 4
UNIT 5
UNIT 6
UNIT 7
8
UNIT 9
UNIT 10
UNIT 11
UNIT I2
FIG. 5B SUPPLYING OF INSTRUCTIONS FROM THE INSTRUCTION BUFFER TO THE INSTRUCTION REGISTER UNIT 1
UNIT 2
UNIT 3
UNIT 4
UNITS
UNIT6
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UNIT9 UNIT 10 E UNITII i UNITI2 E FIG. 5C ISSUING OF INSTRUCTIONS FROM THE INSTRUCTION REGISTER TO THE INSTRUCTION DECODER
(IN UNITS OF PARALLEL EXECUTION CODES)
I UNITl lumrz E umrs
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US. Patent
Sep. 21, 2010
Sheet 6 0f 29
US RE41,751 E
PARALLEL EXECUTION BOUNDARY INFORMATION f10 FORMAT INFORMATION 1°11 7 As
FIG. 6A
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