Indo-American Engineers Academy USA
UAE
INDIA (Hyderabad, Guntur)
VLSI Domain Projects IEEE based Projects List 2013 & 2012 CODE
TITLE
IAEA_01
Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes.
IAEA_02
Low Latency Systolic Montgomery Multiplier for Finite Field Based on Pentanomials.
IAEA_03
Multi operand Redundant Adders on FPGAs.
IAEA_04
Low-Complexity Multiplier for Based on GF (2m) All-One Polynomials.
IAEA_05
16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder.
IAEA_06
CORDIC Designs for Fixed Angle of Rotation.
IAEA_07
A High Speed Binary Floating Point Multiplier Using Dadda Algorithm.
IAEA_08
An FPGA Based High Speed Ieee-754 Double Precision Floating Point Multiplier Using Verilog HDL.
IAEA_09
Design A DSP Operations Using Vedic Mathematics.
IAEA_010
Design And Implementation Of 32 Bit Unsigned Multiplier Using CLA And CSLA.
IAEA_011
Design And Implementation Of Truncated Multipliers For Precision Improvement.
IAEA_012
VLSI Implementation Of Fast Addition Using Quaternary Signed Digit Number System
IAEA_013
Design of High Speed Low Power Multiplier Using Reversible Logic: A Vedic Mathematical Approach.
IAEA_014
Design Of high Performance 64 Bit MAC Unit.
IAEA_015
Efficient Approaches To Design A Reversible Floating Point Divider.
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Indo-American Engineers Academy USA
UAE
INDIA (Hyderabad, Guntur)
VLSI Domain Projects IEEE based Projects List 2013 & 2012 TITLE
CODE IAEA_016
High Performance Hardware Implementation Of AES Using Minimal Resources.
IAEA_017
Implementation And Comparison Of Effective Area Efficient Architectures For CSLA.
IAEA_018
Implementation Of Binary To Floating Point Converter Using HDL
IAEA_019
Least Complex S-Box And Its Fault Detection For Robust Advanced Encryption Standard Algorithm.
IAEA_020
Novel High Speed Vedic Mathematics Multiplier Using Compressors.
IAEA_021
Novel Method Of Digital Clock Frequency Multiplication And Division Using Floating Point Arithmetic.
IAEA_022
Optimized Reversible Vedic Multipliers For High Speed Low Power Operations.
IAEA_023
The Floating-Point Unit Of The Jaguar X 86 Cores.
IAEA_024
VLSI Implementation Of A High Speed Single Precision Floating Point Unit Using Verilog.
IAEA_025
A Novel Approach For Parallel CRC Generation For High Speed Application.
IAEA_026
Design And Implementation Of A High Performance Multiplier Using HDL.
IAEA_027
Design and Implementation of High-Performance High-Valency Ling Adders.
IAEA_028
High Speed Modified Booth Encoder Multiplier For Signed And Unsigned Numbers.
IAEA_029
Design Of High Speed Hybrid Carry Select Adder.
IAEA_030
Design Of Modified Low Power Booth Multiplier.
www.indo-americangroup.com
[email protected]
www.academicprojectsworld.com
[email protected]
Indo-American Engineers Academy USA
UAE
INDIA (Hyderabad, Guntur)
VLSI Domain Projects IEEE based Projects List 2013 & 2012 CODE
TITLE
IAEA_031
High-Speed Low-Power Viterbi Decoder Design For TCM Decoders.
IAEA_032
Design And Implementation Of Carry Select Adder Without Using Multiplexers.
IAEA_033
Implementation Of Power Efficient Vedic Multiplier.
IAEA_034
Low-Power And Area-Efficient Carry Select Adder.
IAEA_035
A Parallel-Serial Decimal Multiplier Architecture.
IAEA_036
A High Speed And Area Efficient Booth Recoded Wallace Tree Multiplier For Fast Arithmetic Circuits.
IAEA_037
An Improved BCD Adder Using 6-Lut FPGAS.
IAEA_038
High Speed ASIC Design Of Complex Multiplier Using Vedic Mathematics
IAEA_039
Efficient Design And Implementation Of FFT
IAEA_040
Design Of Low Power And High Speed Configurable Booth Multiplier
IAEA_041
Design And Characterization Of Parallel Prefix Adders Using FPGAs
IAEA_042
An Efficient Implementation Of Floating Point Multiplier
IAEA_043
Design And Implementation Of TPG-LFSR
IAEA_044
Design Of Automatic Washing Machine Based On Verilog HDL Language
IAEA_045
A New Reversible Design Of BCD Adder
www.indo-americangroup.com
[email protected]
www.academicprojectsworld.com
[email protected]
