A 32.5-GS/s Two-Channel Time-Interleaved CMOS Sampler with Switched-Source Follower based Track-and-Hold Amplifier Shunli Ma1,Jiacheng Wang2, Hao Yu2, and Junyan Ren1 State Key Laboratory of ASIC and System, Fudan University, Shanghai, China 200433 2 School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 1

Abstract —This paper presents a high speed and low distortion sampler with two-channel time-interleaved sampler with track-and-hold amplifier (THA). The THA is based on switched source-follower with active inductor load such that wide bandwidth in tack-mode and small signal feed-through in holdmode can be both achieved within compact area. Furthermore, one clock-controlled auxiliary transistor is also introduced to cancel clock feed-through in hold-mode. The chip was fabricated in 65nm RF-CMOS process with core area of 0.07mm2 and power consumption of 192mW. The measured S-parameters show matched input and output up to 40GHz with 19.3GHz bandwidth in track-mode. The measured spurious-free-dynamicrange (SFDR) is 35dB, and total harmonic distortion (THD) is 30dB sampled at 16.26GS/s in one channel. Index Terms — Sampler, track-and-hold amplifier, high speed, low distortion, time-interleaved, feed-through cancellation

at 16.25GHz because of the wideband in track-mode. What is more, given the compact area of one channel, the deployed two-channel time-interleaving can further double the sampling rate to 32.5GHz. In addition, to reduce the hold-mode distortion, clock and signal feed-through are both well cancelled. One clock-controlled auxiliary NMOS transistor is introduced in the THA for clock feed-through cancellation. The signal feed-through is suppressed by the self-biased active inductor. The remaining part of the paper is organized as follows. Section II presents the THA design with the self-biased active inductor and the feed-through cancellation, respectively. Section III shows the design of two-channel time interleaving. Section IV shows the measurement results with conclusion in Section V.

I. INTRODUCTION The GS/s-scale ADCs require high-speed and low distortion sampler to track and hold input signals [1-3]. The traditionally sampler is based on the high cut-off frequency (ft) InP/SiGe HBT bipolar devices with current-domain sampling. However, most of the CMOS based sampler designs perform voltagedomain sampling and suffer from charge injection, nonlinear resistance, and limited gain-bandwidth product of amplifiers [4], it is difficult to design a CMOS sampler at scale of GS/s by the voltage-domain sampling. The CMOS sampler with switched source-follower (SSF) based THA can perform a current-domain signal processing, and is promising for the GS/s-scale sampling. However, passive inductors are required to extend tack-mode bandwidth in the previous SSF design [1]. When time-interleaving is further deployed, it becomes infeasible to utilize passive inductors because of large area overhead in implementation. What is more, the voltage stored in hold-capacitor is not constant during hold-mode operation because it can be distorted by the input signal and clock feed-through due to inherent parasitic capacitor of the source-follower transistor [1-3]. This paper presents a high speed and low distortion currentdomain sampler with SSF-based THAs in 65nm CMOS. A QVCO is utilized for time interleaving. A self-biased active inductor is introduced to replace passive inductors in the SSFbased THA. It can extend the bandwidth within compact area, which consumes less than 1% area (typical 10um x10um) when compared with passive inductors (typical 100um x100um). The sampling rate of each THA channel is achieved

II. TRACK AND HOLD AMPLIFIER DESIGN As shown in Fig.1, the proposed CMOS sampler is designed with THA that consists of an input buffer, a switched source-follower (SSF) and an output buffer. The loads of buffers are self-biased active inductors with series resistors. The supply voltage is 3V to improve the signal swing with both 3.3V high voltage transistor and 1.2V low voltage transistor used. The working principle of the THA can be summarized as track-and-hold mode. In track-mode, CLK is low, and M3 steers the current I1 to flow through M2. Current source I1 and M2 act as a source-follower to track the input signal. In hold-mode, CLK is high, M4 steers the current I1 to flow through R1 and M1. Then the gate voltage of M2 will drop to hold the data on the capacitor Chold. A. Wideband THA by Self-Biased Active Inductor Self-biased active inductor is composed of a resistor R2 and a transistor M1 as show in Fig.1. Compared with the passive inductor load, it not only reduces the areas, but also extends track-mode bandwidth by its inductance part [5]. The track-mode bandwidth depends on the time-constant at node X. A smaller parasitic capacitor at node X will result in a wider bandwidth. The active inductor can absorb parasitic capacitor at node X and reduce the parasitic capacitor. As a result, the bandwidth can be extended β times compared with the track-band without self-inductor. In this design, the β is 3.1 when the width of M1 is 24um and the current is 5mA. B. Low Distortion with Feed-Through Cancellation

Fig.1.Circuit diagram of differential THA with self-biased active inductors and feed-through cancellation.

The signal feed-through and clock feed-through will distort the hold voltage on the capacitor Chold in hold-mode. The input signal feed-through happens as shown in Fig. 2. Due to parasitic capacitor Cgs2, the input signal is amplified by the input buffer, and then is injected at the output node X to distort the hold signal. In order to cancel the input signal feedthrough, the conventional approach is to add capacitors between input buffer and SSF [1-3]. The performance of this cancellation method is limited by the matching of the capacitors (10-50fF), which can be severely degraded in advanced technology node. With the use of the self-biased active inductors, input signal feed-through is relieved by decreasing the gain of the input buffer at hold-mode, because the self-biased inductors take extra voltage headroom compared with passive inductor. The loss of voltage headroom can isolate the input signal because the input pairs of M8 are in deep-triode region reduced gain in hold-mode. Based on the post-layout simulation result, the isolation of input signal feed-through is 48dB at a 16GHz input signal. The clock feed-through happens as shown in Fig. 2. When CLK changes to high in hold-mode, the voltage at node A will drop due to the current I1 flows through R1 and M1. As such, the hold signal stored in Chold will also drop due to the parasitic capacitor Cgs2. In order to cancel the clock feedthrough, a dummy transistor M5 with a half-size of M2 controlled by clock signal input is introduced. It can compensate the voltage drop at node C because the opposite voltage swing at node B has almost the equal amplitude as shown in Fig.1. III. TWO-CHANNEL TIME INTERLEAVING The two-channel time-interleaving architecture is applied to further extend the sampling speed because each channel will sample the input signal in one clock cycle with doubled throughput. However, the performance of interleaving is influenced by phase error between the two channels as well as clock jitter in each single channel. In order to achieve 6-bit resolution time-interleaved THAs with 16GHz input signal, the minimum skew is required <0.1ps meaning the IQ mismatch between the two channels

needs to be less than 0.8°. Meanwhile, the cycle-to-cycle jitter is required less than 0.2ps meaning that the phase noise is about -104dBc/Hz at 1MHz offset from 16GHz center oscillation frequency [6-7]. The S-QVCO structure is utilized to generate the small phase skew and low phase noise clock signals [8]. The inductor of the QVCO and clock distribution are co-designed and simulated in ADS because of the high frequency clock and stringent clock skew and phase noise requirements. The phase error between the two channels is 0.6°, and jitter is

Fig.2(a) 3D view of the QVCO inductor and clock distribution network, the phase error is 0.6°( port 1 to 2, port 3 to 4.port 5 to 6, port7 to 8) (b) two-channel time-interleaved THAs (c) cross-coupled transistors in QVCO , the phase noise is -112dBc/Hz @1MHz at 16.25GHz

0.16ps, which both meet the requirements. IV. MEASUREMENT RESULTS The proposed sampler was fabricated in 65nm CMOS process. Fig. 3(a) shows the chip micrograph with active area of 0.07mm2 including QVCO and two THAs. Each THA operates at 3V supply and draws 60mA current. The supply voltage of QVCO is 1.2V and the current consumption is 8mA.

Fig. 3(b) shows the measured single-ended S-parameters. The

compatible with a 6-bit resolution with input signal frequency up to 6 GHz. Finally, Table 1 shows that performances of the proposed CMOS sampler are comparable to the ones in InP/SiGe HBT process. TABLE I. PERFORMANCES COMPARISON OF STATE-OF-ART SAMPLERS [1]

Fig.3(a)chip micrograph of the sampler and QVCO (b) Measured Sparameter

Fig. 4 (a)Spectrum of sampled signal: input signal at 6GHz sampled at 16.26 GHz;(b) measured spectrum of clock

[2]

[3]

Supply (V)

0.13um CMOS 1.8

InP (170) 5.2

SiGe (150) 4

fsample (GS/s)

30

20

20

BW (GHz)

7

NA

26

SFDR(dB@ finGHz)

40@1

NA

36@1

THD(dB@ fin GHz) Power(mW) Areas (mm2)

-29@7 270 1

-18@9 735 4

NA 453 NA

Process( ft GHz)

This work 65nm CMOS 3 16.26 X 2 19.3 37.42@ 6 -37@6 192 0.36

V. CONCLUSION

Fig. 5(a) Single-end output of one 3GHz sinusoid input signal sampled by 16.264 GHz clock with the feed-through well cancelled in hold-mode (b) Measured THD and SFDR with sampling frequency sweeping from 1GHz to 16GHz

input return loss (S11) and output return loss (S22) are observed better than -10dB up to 40GHz. The S21 further shows that the bandwidth is 19.3GHz in the track-mode. Next, the spectrum of a 6GHz input signal sampled by 16.26GHz clock is shown Fig. 4(a). The SFDR is observed as 37.42dB. The spectrum of on-chip generated clock signal is shown in Fig.4 (b). What is more, the time-domain measurements performed by oscilloscope with results shown in Fig. 5(a). It illustrates that the one-channel single-end output for a 3GHz input signal can be sampled by 16.26GHz clock. As a result, the two-channel THAs are expected to sample the signal at 32.5GS/s. The measurement results show that the clock and signal feedthrough are both well canceled to less than 0.2mV in holdmode, demonstrating the effectiveness of the active inductor and clock-controlled NMOS transistor. In addition, the input compression point of the sampler is measured from 1GHz to 16GHz as shown in Fig. 5(b). The identified compression point is -6dBm at 1GHz, and has a nearly flattened curve up to 10GHz. It shows that the SFDR is about 37dB and hence is

In this paper, a 32.5-GS/s two-channel time-interleaving CMOS sampler has been demonstrated with area of 0.07mm2 and power of 192mW. The self-biased active inductor is utilized to achieve 19.3GHz bandwidth in track-mode with small signal feed-through in hold-mode and less than 1% active areas compared with the passive inductor. The clockcontrolled auxiliary NMOS transistors are also introduced to cancel the clock feed-through at hold-mode. The measured peak SFDR and THD are 37.42dB and -37dB at 6GHz input signal sampled by 16.26GHz clock. REFERENCES [1] S. Shahramian, S. P. Voinigescu and A. C. Carusone, “A 30GS/sec Track and Hold Amplifier in 0.13- µm CMOS Technology,” in Proc. CICC, 2006, pp. 493-496. [2] S. Yamanaka, K. Sano, and K. Murata, “A 20-GS/s Track-andhold Amplifier in InP HBT Technology”, IEEE Trans. Microwave Theory & Tech., vol. 58, pp. 2334-2339, Sept 2010. [3] Lee J, Weiner J, Chen Y K, “A 20-GS/s 5-b SiGe ADC for 40Gb/s coherent optical links,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 57, pp. 65-74, Oct. 2010. [4] A. Mesgarani, H.P. Fu, M. Yan, H. Yu, and S. Ay, "A 5-Bit 1.25GS/S 4.7mW Delay-Based Pipelined ADC in 65nm CMOS," in Proc. ISCAS, 2013, pp. 2018-2021. [5] F. Yuan, “CMOS current-mode circuits for data communications”, New York: Springer, 2007. [6] M. Shinagawa, “Jitter analysis of high-speed sampling systems,” in VLSI Circuits Dig. Tech. Paper. 1989. pp.95-96. [7] B.Razavi, “A study of phase noise in CMOS oscillators,” IEEE J.Solid-State Circuits, vol. 31, pp. 331–343, Mar. 1996. [8] P.Andreani, “A low-phase-noise, low-phase-error 1.8 GHz quadrature CMOS VCO,” in Proc. ISSCC 2002,pp.290–291.