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Impact of Ion Implantation Damage and Thermal Budget on Mobility Enhancement in Strained-Si N-Channel MOSFETs Guangrui Xia, Hasan M. Nayfeh, Minjoo L. Lee, Eugene A. Fitzgerald, Member, IEEE, Dimitri A. Antoniadis, Fellow, IEEE, Dalaver H. Anjum, Jian Li, Member, IEEE, Robert Hull, Nancy Klymko, and Judy L. Hoyt, Senior Member, IEEE

Abstract—The impact of processing factors such as ion implantation and rapid thermal annealing on mobility enhancement in strained-Si n-channel metal–oxide–semiconductor field-effect transistors (n-MOSFETs) has been investigated. Long-channel strained-Si and bulk n-MOSFETs were fabricated with various channel-region implant doses and thermal budgets. Neutral Si and Ge species were used to study the impact of the implant damage on mobility separately from ionized impurity scattering effects. Electron mobility enhancement is shown to degrade considerably when the implant dose is above a critical dose for a given thermal budget. Transmission electron microscopy, secondary ion mass spectrometry and Raman spectroscopy were used to investigate the mobility degradation mechanisms. Residual implant damage and implant damage enhanced Ge up-diffusion into the Si are shown to be responsible for the mobility degradation. Two-dimensional damage simulations of 30-nm scale MOSFETs are used to examine potential technological implications of these findings. Index Terms—Electron mobility, Ge diffusion, ion implantation damage, rapid thermal anneal, strained-Si n-channel metal–oxide–semiconductor field-effect transistors (n-MOSFETs).

I. INTRODUCTION

S

TRAINED-Si technology is a promising method to enhance metal–oxide–semiconductor field-effect transistor (MOSFET) performance due to improved carrier transport properties [1]–[3]. Enhanced mobility and current drive have been demonstrated in sub-100-nm strained-Si/relaxed SiGe MOSFETs [4]–[6]. As the scaling of strained-Si MOSFETs continues, the performance enhancement may become susceptible to degradation during processing, particularly from ion

Manuscript received January 19, 2004; revised May 25, 2004. This work was supported by the Semiconductor Research Corporation under Grant 841.002. The review of this paper was arranged by Editor T. Skotnicki. G. Xia, M. L. Lee, E. A. Fitzgerald, D. A. Antoniadis, and J. L. Hoyt are with the Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139 USA (e-mail: [email protected]). J. Li and R. Hull are with the Department of Materials Science and Engineering, University of Virginia, Charlottesville, VA 22904 USA. D. H. Anjum was with the Department of Materials Science and Engineering, University of Virginia, Charlottesville, VA 22904. He is now with The Burnham Institute, La Jolla, CA 92037 USA. N. Klymko is with the IBM Microelectronics Division, Hopewell Junction, NY 12533 USA. H. Nayfeh was with Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139 USA. He is now with the IBM Semiconductor Research and Development Center (SRDC), IBM Microelectronics Division, Hopewell Junction, NY 12533 USA. Digital Object Identifier 10.1109/TED.2004.839116

implantation and thermal processing effects. The ion implant dose under the gate (e.g., associated with the halo implants) increases with scaling. In addition, the lateral damage associated with the source/drain extension regions may comprise a larger portion of the channel as the device is scaled. Ion implantation damage may supply point defects that assist Ge diffusion and the relaxation of strain. Residual ion implantation damage, remaining after annealing, may act as carrier scattering centers. Thus, the impact of ion implant damage on mobility enhancement in strained-Si MOSFETs requires investigation. In addition to ion implantation effects, thermal processing of strained-Si MOSFETs is an issue that requires investigation. In strained-Si films above a critical thickness, thermal processing can cause misfit dislocations to form, leading to strain relaxation as well as enhanced impurity diffusion along the source/drain axis [7]. Ge from the underlying SiGe can diffuse up into the Si interface, strained-Si channel and segregate at the degrading the mobility due to alloy scattering and Coulomb scattering by interface states and fixed charges [8]–[10]. Moreover, Ge in strained-Si reduces the lattice mismatch between Ge underneath, which the strained-Si and the relaxed Si reduces the strain in the layer. In this paper, the impact of ion implantation and thermal processing on strain and mobility enhancement has been investigated. Long-channel strained-Si and bulk n-channel MOSFETs (n-MOSFETs) were subjected to Si and Ge implants of varying dose, and the mobility and strain characteristics were analyzed. Neutral species (Si and Ge) were used to emulate the damage associated with commonly used dopants in order to investigate the impact of the implant damage on mobility separately from ionized impurity scattering effects, which have been studied by Nayfeh et al. [11]. II. EXPERIMENTAL PROCEDURE Long-channel strained-Si and bulk n-MOSFETs were fabricated with various Si and Ge implant conditions and thermal budgets. Relaxed Si Ge layers were epitaxially grown on Ge buffer layers in an ultrahigh vacuum graded relaxed Si chemical vapor deposition (UHVCVD) reactor as virtual substrates for the strained-Si MOSFETs. The strained-Si layer and the Si Ge layer were in-situ doped with boron to a level cm . The Czochralski (CZ) control wafers were of 3 cm . The p-type wafers doped with boron to a level of

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TABLE I WAFER MATRIX USED IN THIS WORK. FOR WAFERS WITH SI IMPLANTS, THERE IS ONE IMPLANT CONDITION ON EACH HALF OF THE WAFER, I.E., “NO IMPLANT 2.7 10 ” INDICATES THAT THE LEFT HALF OF WAFER HAS NO IMPLANT, WHILE THE RIGHT HALF OF THE WAFER IS IMPLANTED WITH 2.7 10 cm SI

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Fig. 1. Structure of a long channel strained-Si n-MOSFET after processing. The hatched area illustrates the region with the as-implanted damage associated with the Si or Ge implants that took place before gate stack formation.

thickness variation of the strained-Si layer in these particular from wafer to wafer. The growths was estimated to be 30 as-grown thickness of the strained-Si layer was . Ion implantation was performed prior to gate stack formation. In order to avoid ionized impurity scattering effects, neutral Si and Ge were implanted into the channel. The gate oxide was grown at 800 C for 30 minutes in dry oxygen ambient. The gate oxide thickness was measured to be 43–47 across the boat by ellipsometry. After the gate etch, reoxidation was performed at 800 C in dry oxygen ambient for 11 minutes on all wafers except one wafer to investigate the effect of reoxidation. The deep source/drain regions and gate were implanted with phosphorus at 10 keV. In order to inves5 tigate the effects of thermal processes on damage anneal and mobility behavior, three rapid thermal annealing (RTA) splits, 1000 C for 1 s, 1000 C for 10 s, and 950 C for 10 s, were used to anneal the implantation damage and activate the source/drain and gate dopants. The structure of a strained-Si n-MOSFET after fabrication is illustrated in Fig. 1. The strained-Si was partially consumed during MOSFET processing. Based upon the cleaning and low-temperature oxide deposition steps, it is estimated that the strained-Si thickness at the time the wafers were pushed into the was at 800 C oxidation furnace, and approximately the time the wafers were subjected to rapid thermal annealing. Thus, it is important to note that at the time the wafers were subjected to thermal processing, the strained-Si thickness is estimated to be below the critical thickness for misfit dislocation formation [12], [13]. From the transmission electron microscopy (TEM) images, the remaining strained-Si thickness in the samples with the least amount of Ge up-diffusion is estimated to be 80 to 100 after complete processing, consistent with the above estimate of the strained-Si layer thickness. The implant and RTA conditions of all processed wafers are shown in Table I. The Si implant doses range from 4 to cm , and the Ge implant doses range from 3 5 to 1 cm . The wafers with epitaxial strained-Si layers are denoted as E1–E10. The CZ control wafers are denoted as CZ1–CZ10. Wafer E4 is the only wafer without the reoxidation step. There are two implant conditions on each wafer for those ion implanted with Si.

The Si and Ge implant doses and energies were chosen based on simulation results using UT–MARLOWE 5.0, a software platform for Monte Carlo simulation of ion implantation [14]. The damage model used was the Kinchin–Pease damage model [14]. In UT–MARLOWE, normalized interstitial concentration profiles were generated to represent the degree of amorphization in the implanted substrate. When the interstitial concentracm (10% of Si lattice density) at a given tion reaches 5 depth, the sample is defined to be amorphized at that depth [14]. It should be noted that the UT–MARLOWE simulations were used to chose the Si and Ge implant conditions with equivalent as-implanted damage to the commonly used B and As implant conditions, and the simulations were not designed for detailed implant damage and amorphization study. First, the damage proand files were simulated for commonly used boron (7 cm both at 10 keV) and arsenic ion implantation con5 cm at 30 keV). Then the implantation conditions (1 ditions of Si were carefully chosen to match the damage profiles of B, as shown in Fig. 2(a). The right axis in Fig. 2(a) is the axis for the corresponding as-implanted interstitial concentration. The simulated Ge damage profiles are shown in Fig. 2(b). Since Si and P have very close atomic mass, 28.09 and 30.97 respectively, we assume that the damage profiles of Si implants are good matches to P profiles under the same implant conditions. Similarly, Ge damage profiles are well matched to those of cm As under the same implant condition. Si doses of 5 and Ge doses cm amorphize the channel region. Si doses and Ge doses of 3 were chosen to represent of 1 cases in the subamorphous regime. versus vertical electric Effective electron mobility field data were extracted from – and split capacitance–voltage ( – ) measurements. The mobility was calculated using (1) and (2) below (1)

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Fig. 2. Damage profiles of (a) Si, B implants and (b) Ge implants simulated by UT–MARLOWE. The right y axis in (a) shows the corresponding as-implanted interstitial concentration.

Fig. 3. Effective electron mobility  for 1 s and (b) 1000 C for 10 s.

versus vertical effective field E

for the strained-Si devices subjected to Si ion implantation and annealed at (a) 1000 C

(2) Si is the drain conductance, is the integrated inwhere version charge density, calculated from the split – measureis the depletion charge (computed from the doping ments, extracted from – ), and Si is the permittivity of Si. All the demobility data shown were obtained from 100 100 vices. The mobility of the devices with the same processing conditions can be different by 10%–15% mainly due to processing nonuniformity. When comparison is made among different mobility curves, a difference less than 15% is considered within the error bar of this experiment. III. RESULTS In this paper, we focus on the mobility data of devices versus for the annealed at 1000 C. Fig. 3 shows strained-Si devices with different implant and RTA conditions. Fig. 3(a) shows the mobility curves for devices annealed at 1000 C for 1 s. In this figure, the electron mobility for devices with no implant has an enhancement factor of 1.7

Fig. 4. Mobility data for Si implanted CZ control devices annealed at 1000 C for 1 s.

over the universal electron mobility for unstrained-Si [8] at MV/cm. It is seen that the effective mobility degrades monotonically with increasing implant dose, but and this effect is negligible for Si implant doses of 4

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Fig. 5. Effective electron mobility at E = 0:7 MV=cm for strained-Si and CZ control devices versus implant doses for (a) devices with Si implants (the equivalent B doses are shown in upper x axis), and (b) devices with Ge implants.

2.7 cm . For doses of 1 and 5 cm , MV/cm, the enhancement factor degrades to at 1.3 and 1 respectively, which indicates that the mobility enhancement from the strain induced energy band splitting is mostly eliminated. Fig. 3(b) shows the mobility curves for the strained-Si devices annealed at 1000 C for 10 s. The mobility for the devices with no implant is the same in Fig. 3(a) and (b), i.e., 1 s and 10 s RTA yield the same mobility in the absence of channel implantation. In Fig. 3(b), we see that the combination of implantation damage and high thermal budget causes mobility degradation. The mocm . bility starts to show degradation at a dose of 2.7 ,1 and 5 cm The devices with doses 2.7 have the same mobility within experimental error, which is different from their counterparts in Fig. 3(a). The cause of this behavior will be discussed in detail in Section IV. The mobility data of the devices with and without reoxidation (not shown) are the same, within the error bar of the measurement. Therefore, the reoxidation step used in this paper (11 minutes at 800 C) has little impact on the mobility. Fig. 4 shows the mobility curves of CZ control devices annealed at 1000 C for 1 s on the same scale as in Fig. 3. Mobility degradation of a few percent is seen in the implanted CZ devices compared to the unimplanted devices. Since there is no concern about strain relaxation or Ge diffusion in CZ control devices, the small amount of mobility degradation seen in CZ devices is mainly due to ion implantation damage. The mobility curves for CZ control devices annealed at 1000 C for 10 s and 950 C for 10 s (not shown) are a few percent higher than those shown in Fig. 4. In summary, the mobility of the CZ control devices with the three different RTA conditions has little dependence on implant dose and thermal budget, compared to the strained-Si devices. In order to study the implant dose and RTA dependence of the mobility, electron mobility is plotted against the implant dose at a fixed vertical effective field in Fig. 5 for (a) Si implants and (b) Ge implants. The field was chosen to be for two reasons: first, modern devices are operating near this field, secondly at high fields, for the doping levels used in this paper, the Coulomb limited mobility has less influence on the

total mobility [8] and the measured mobility is closer to the universal mobility of strained-Si. In Fig. 5(a), we can see that for a specific thermal budget the electron mobility of strained-Si n-MOSFETs starts to degrade at a certain implant dose. We can for this thermal define this dose as the critical implant dose budget, above which the mobility degrades significantly. The depends on the thermal budget. The higher the critical dose thermal budget is, the lower the critical dose. For example, for Si implanted devices annealed at 1000 C for 1 s is apcm , while for those annealed at proximately 2.7 1000 C for 10 s is approximately 4 cm . Below this critical dose, mobility degradation is negligible. As mentioned above, the damage profiles of Si are very close to those of P. Therefore, the critical doses for Si implants should be good approximations to those of P with same thermal budget. The equivalent B implant doses in terms of implant damage profiles are shown on the upper axis of Fig. 5(a) for reference. The estifor B implanted devices annealed at 1000 C for 1 s mated is 5 cm , while for B implanted devices annealed cm . at 1000 C for 10 s is approximately 7 Fig. 5(b) shows the electron mobility at for Ge implanted devices annealed at 1000 C for 1 s. The critical dose for Ge and thus As implants annealed at 1000 C for 1 s to cm . This is significantly lower is in the range of than the critical dose range for B, which is consistent with the larger amount of damage per ion for As compared to B. It should be noted that the critical doses obtained in this paper are based on the study of neutral Si and Ge implants without ionized impurity scattering effects, in order to isolate the impact of implant damage. The results of the present paper imply that implant damage effects did not play a significant role in the mobility study of Nayfeh, et al. that investigated effects of ionized impurity scattering on strained-Si MOSFETs [11], since cm (annealed the maximum B dose in that work was 7 at 1000 C for 1 s), which is below the critical dose found in Fig. 5(a). IV. MATERIALS ANALYSIS AND DISCUSSION Ion implantation and thermal processing are shown to degrade the mobility in strained-Si MOSFETs. To understand

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Fig. 6. XTEM images for strained-Si devices with (a) no implant (RTA at 1000 C for 1 s), (b) 5 10 Si implant (1000 C 10 s RTA).

Fig. 7. PVTEM images for strained-Si devices with (a) 1 (c) 5 10 cm Si implant (1000 C 10 s RTA).

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Si implant (1000 C 1 s RTA) and (c) 5

Si implant (1000 C 1 s RTA), (b) 5

the mobility degradation mechanisms, materials analysis was performed. Cross-section TEM (XTEM) and plan-view TEM (PVTEM) were used to study the implant damage and misfit dislocations in the strained-Si layers. Secondary ion mass spectroscopy (SIMS) was performed to obtain Ge diffusion

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Si implant (1000 C 1 s RTA), and

profiles, and Raman scattering was used to check the strain status of the strained-Si channel. Ion implantation damage was confirmed by XTEM and PVTEM images. Figs. 6 and 7 are the XTEM and PVTEM images of strained-Si samples. In the PVTEM images (Fig. 7),

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Fig. 8. Ge profiles obtained by SIMS of Si implanted strained-Si substrates annealed at 1000 C for (a) 1 s, and (b) 10 s. The slope of the Ge profile of an as-grown epitaxial substrate is shown by the dashed line for reference. Variations in the as-grown strained-Si layer thickness from wafer-to-wafer produce a lateral shift in some of the profiles, as evident particularly in (a). Comparison of data in (a) and (b) indicates that there is significantly more Ge present in the channel region for samples annealed for 10 s than for 1 s. TABLE II RTA SPLITS, IMPLANT CONDITIONS, DISLOCATION LOOP AND f311g DEFECT DENSITIES ESTIMATED FROM PVTEM IMAGES, AND THE MOBILITY ENHANCEMENT FACTORS OF THE SAMPLES IMAGED BY TEM AND PVTEM IN THIS WORK

two types of defects that are commonly observed in implanted defects and dislocation loops. No Si are seen: rod-like misfit dislocations are observed in any of the PVTEM images in this paper, indicating that strain relaxation by misfit dislocations did not occur in thermal processing, which is consistent with our estimate that the strained-Si layer thickness during thermal processing was thinner than the critical thickness. The RTA defect splits, implant conditions, dislocation loop and densities estimated from PVTEM images, and the mobility enhancement factors for the samples imaged by TEM and PVTEM in this paper are listed in Table II. For devices without implantation, no damage is observed in the channel as shown in Fig. 6(a). For devices with the highest cm , implantation damage is clearly Si implant dose 5 seen in the strained-Si layer and nearby SiGe layer, as shown in Fig. 6(b) and (c). The amount of residual damage depends on the annealing conditions. The residual implantation defect densities are lower for samples annealed at 1000 C for 10 s as seen in Figs. 6(c) and 7(c), compared to those annealed at 1000 C for 1 s as seen in Figs. 6(b) and 7(b), indicating that more implant damage is annealed in the longer RTA. The samples in 7(a) and (b) are annealed at 1000 C for 1 s, and 5 cm respecwith Si implant doses of 1

tively. The sample in 7(a) has lower defect densities compared to the sample in 7(b), and the mobility enhancement factors of those samples are 1.3 and 1.0 respectively. This indicates that residual ion implantation damage is one mobility degradation mechanism in the devices annealed at 1000 C for 1 s. Statistical data obtained by PVTEM for samples annealed at 1000 C for 10 s with Si implant doses of 2.7 ,1 and 5 cm are listed in the last three columns of Table II. These three samples have similar mobility curves (enhancement factor degraded from 1.7 to 1.2 in all three samples). The cm Si has a considerable sample implanted with 5 amount of residual implant damage as seen in Fig. 7(c), while no residual implantation damage is observed in the other two samples. Therefore, ion implantation damage is not the primary mobility degradation mechanism for devices annealed at 1000 C for 10 s. One possible explanation is that Ge diffusion becomes the dominant mechanism of mobility degradation for 1000 C 10 s RTA, as opposed to residual implant damage. To verify this hypothesis, SIMS was used to obtain Ge profiles as shown in Fig. 8. In this experiment, the as-grown thicknesses of the strained-Si epitaxial layer varied by as much as from wafer-to-wafer, which causes the Ge profiles to shift laterally within 30 in Fig. 8. Therefore, in Fig. 8(a) the Ge profile slopes rather than their positions are evidence of Ge diffusion in this plot. In Fig. 8(a) and (b), the as-grown sample has a steeper Ge profile than any of the processed samples, indicating that some Ge diffusion took place during MOSFET processing. For samples annealed at 1000 C for 1 s, the surface Ge fractions are very close for samples both with and without mobility degradation (e.g., the transistors without ion implantation and with a Si cm have similar Ge surface concentrations, dose of 5 but very different mobilities). Therefore, Ge up-diffusion is not the primary cause for the mobility degradation for the samples that received the 1000 C 1 s RTA. Fig. 8(b) shows the Ge profiles for 1000 C 10 s RTA. Compared to Fig. 8(a), Ge diffuses much more during the longer RTA. Ge diffuses most in the samples with the two highest imand 5 cm most likely due to implant doses, 1

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Fig. 9. Raman scattering spectra (325-nm excitation) of unstrained-Si, as-grown fully strained-Si on Si Ge , and strained-Si on Si Ge samples after processing, including 1000 C 1 sec RTA. The symbols are Raman data and the lines are Lorentz fits to the data. Raman spectra (a)–(c) are fitted by two Lorentzian functions to account for the signal from the underlying Ge (x < 0:2) layer formed by Ge up-diffusion. The numbers in Si parentheses are the Si-Si phonon peak positions from the Si layer (as opposed to the Si Ge layer).

plant damage enhanced Ge diffusion. The near-surface Ge fraction in Fig. 8(b) increases with increasing implant dose. Therefore, Ge up-diffusion is considered to be the key mechanism for the mobility degradation seen in the samples annealed at 1000 C for 10 s. Another hypothesis to explain the observed mobility degradation is strain relaxation due to ion implantation damage and thermal processing. In the PVTEM images, no misfit dislocations are observed. Raman spectroscopy was performed to check for strain relaxation in the Si, perhaps by defects other than misfit dislocations. Raman analysis was performed using 325-nm excitation, which samples approximately the top 10 nm. Fig. 9 shows the Raman spectra of the unstrained-Si, as-grown fully strained-Si on relaxed Si Ge , and strained-Si with and without implantation after 1000 C 1 s RTA. In Fig. 9, the large peak at 520.0 cm is due to the Si phonon mode of unstrained-Si, and the peak at 513.4 cm is due to the Si-Si mode in the as-grown fully strained-Si layer on relaxed Si Ge . Tensile strain in Si layer shifts the Raman peak to the left in proportion to the biaxial stress, and the relaxation of tensile strain shifts the peak toward the unstrained-Si peak at 520.0 cm [15]. In Fig. 9, the samples with 1000 C 1 s RTA and different implant doses show no shift to the right. Therefore, strain relaxation is not observed in these samples and is not considered to be a major mechanism for mobility degradation for the 1000 C 1 s RTA. Broadening and asymmetry of the spectra in samples (a), (b), and (c) are observed in Fig. 9. These effects are likely due to the residual disorder and the diffusion of Ge into the strained-Si layer [16]. It should be noted that this Raman analysis samples the top 10 nm of the semiconductor. Thus on wafers with Ge diffusion into the strained-Si layer, a thin buried, strained-SiGe layer will be formed. The signal from this layer could be responsible for the shoulder observed near 509 cm . In summary, materials analysis indicates that residual ion implantation damage is the key mobility degradation mechanism

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Fig. 10. As-implanted interstitial contours (lines) for a 30-nm gate length p-MOSFET simulated by TSUPREM-4 using analytic ion implant models. The simulation employed As halo implants at 30 keV with 38 tilt to a dose of 3 10 cm , and B S/D extensions implanted at 0.7 keV with 0 tilt to a dose of 3 10 cm B. The implant moment tables used are “ARSENIC” for As and “TR.BORON” for B. The symbols show the contour corresponding to a net doping concentration of 2 10 cm .

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for devices annealed at 1000 C for 1 s, while implant damage enhanced Ge up-diffusion is the key mobility degradation mechanism for the MOSFETs annealed at 1000 C for 10 s. V. IMPACT ON TECHNOLOGY AND CONCLUSION Phosphorus, boron and arsenic are widely used in current CMOS technology. Among the various implants, source and drain (S/D) extension, halo and channel implants are located closest to the channel, which can introduce implant damage to the channel region and affect the mobility behavior. In 50-nm node technology, typical doses for As and B S/D extension imand cm respectively. For plants are in the range of cm . halo implants, the typical dose for As and B is The critical doses for uniformly implanted As and B were esto cm and 7 to timated in this paper to be cm respectively, depending on the thermal budget. 5 Arsenic implants are thus expected to be more problematic than boron implants. In order to estimate two-dimensional (2-D) implant damage in more realistic device structures, a process simulation tool, TSUPREM-4 [17], was used to simulate as-implanted interstitial profiles in MOSFETs with halo implants. In the UT–MARLOWE simulations [Fig. 2], interstitial concentration is a measure of implant damage. The parameters in the TSUPREM-4 simulations were calibrated in order to match the simulated as-implanted interstitial profiles generated by one-dimensional UT–MARLOWE simulations. Fig. 10 shows 2-D as-implanted interstitial contours of a 30-nm gate length p-MOSFET simulated using TSUPREM-4. The as-implanted interstitial concentration in the channel region is approximately cm , which is roughly equivalent to that produced 5 cm [see by uniform Si implants with a dose of 2.7 Fig. 2(a)]. In the uniformly implanted, long-channel n-MOSFETs fabricated in this paper, that dose resulted in a significant electron mobility degradation for 1000 C, 10 s annealing [Fig. 3(b)], but no significant mobility degradation was observed for 1000 C, 1 s annealing [Fig. 3(a)]. Thus, it is

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expected that there should be an annealing condition window in which the damage from the As halo implants can be annealed without significant hole mobility degradation in 30-nm scale strained-Si p-MOSFETs, when optimized ion implant energy and angle are used. Two-dimensional simulations were also carried out for 30-nm n-MOSFETs (not shown). In that case, the channel-region as-implanted interstitial concentration is on the order cm , which is approximately the peak interstitial of cm concentration associated with a Si dose of 4 [Fig. 2(a)]. This low dose implant did not induce a significant electron mobility degradation in our experiments for 1000 C, 1 or 10 s annealing. Thus, implant damage will be less of an issue for scaled strained-Si n-MOSFETs than for p-MOSFETs. In summary, the impact of ion implantation and rapid thermal annealing on electron mobility enhancement in strained-Si/relaxed SiGe n-MOSFETs has been investigated. Electron mobility enhancement is shown to degrade considerably when the implant dose is above a certain critical dose for a given annealing condition. The critical doses of Si and Ge and the inferred equivalent P, B and As critical doses were obtained quantitatively. Implant damage enhanced Ge up-diffusion was observed. Residual implant damage and Ge up-diffusion were shown to be the major mechanisms for mobility degradation for 1000 C 1 s and 1000 C 10 s RTA respectively. In designing the annealing conditions for high dose implants, there is a strong trade-off between damage annealing (which requires longer times) and Ge up-diffusion. Further investigation, particularly at lower temperatures, needs to be done to locate an annealing regime where effective defect annealing takes place while Ge diffusion is minimized. The simulated damage range for n-MOSFETs in the 30-nm-scale regime is lower than would be expected to cause mobility degradation based upon the analysis of the uniform channel implants studied in this paper. For 30-nm-scale strained-Si p-MOSFETs, however, the annealing conditions will need to be more carefully optimized to avoid mobility degradation associated with As (halo) and B (source/drain) implants.

ACKNOWLEDGMENT The authors would like to thank G. Goodman at Charles Evans & Associates for SIMS analysis and K. Rim for arranging for the Raman spectroscopy. The devices used were fabricated at the Microsystems Technology Laboratories at MIT.

REFERENCES [1] J. Welser, J. L. Hoyt, S. Takagi, and J. F. Gibbons, “Strain dependence of the performance enhancement in strained-Si n-MOSFETs,” in IEDM Tech. Dig., 1994, pp. 373–376. [2] K. Rim, J. L. Hoyt, and J. F. Gibbons, “Transconductance enhancement in deep submicron strained-Si n-MOSFETs,” in IEDM Tech. Dig., 1998, pp. 707–710. [3] J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, “Strained silicon MOSFET technology,” in IEDM Tech. Dig., 2002, pp. 23–26. [4] K. Rim, S. Narasimha, M. Longstreet, A. Mocuta, and J. Cai, “Low field mobility characteristics of sub–100-nm unstrained and strained-Si MOSFETs,” in IEDM Tech. Dig., 2002, pp. 43–46.

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[5] J. R. Hwang, J. H. Ho, S. M. Ting, T. P. Chen, Y. S. Hsieh, C. C. Huang, Y. Y. Chiang, H. K. Lee, A. Liu, T. M. Shen, G. Braithwaite, M. Currie, N. Gerrish, R. Hammond, A. Lochtefeld, F. Singaporewala, M. Bulsara, Q. Xiang, M. R. Lin, W. T. Shiau, Y. T. Loh, J. K. Chen, and F. Wen, “Performance of 70 mn strained-silicon CMOS devices,” in Symp. VLSI Tech. Dig., 2003, pp. 103–104. [6] K. Rim, J. Chu, H. Chen, K. A. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong, and H.-S. Wong, “Characteristics and device design of sub-100-nm strained-Si N- and PMOSFETS,” in Symp. VLSI Tech. Dig., 2002, pp. 98–99. [7] H. C.-H. Wang, Y.-P. Wang, S.-J. Chen, C.-H. Ge, S. M. Ting, J.-Y. Kung, R.-L. Hwang, H.-K. Chiu, L. C. Sheu, P.-Y. Tsai, L.-G. Yao, S.-C. Chen, H.-J. Tao, Y.-C. Yeo, W.-C. Lee, and C. Hu, “Substrate-strained silicon technology: Process integration,” in IEDM Tech. Dig., 2003, pp. 61–64. [8] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of inversion layer mobility in Si MOSFETs: Part I—Effects of substrate impurity concentration,” IEEE Trans. Electron Devices, vol. 41, pp. 2357–2362, Dec. 1994. [9] T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata, T. Maeda, and S. Takagi, “Design for scaled thin film strained-SOI CMOS devices with higher carrier mobility,” in IEDM Tech. Dig., 2002, pp. 31–34. [10] T. Maeda, T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata, J. Koga, and S. Takagi, “Ultrathin strained-SOI CMOS for high temperature operation,” in Symp. VLSI Tech. Dig., 2003, pp. 99–100. [11] H. M. Nayfeh, C. W. Leitz, A. J. Pitera, E. A. Fitzgerald, J. L. Hoyt, and D. A. Antoniadis, “Influence of high channel doping on the inversion layer electron mobility in strained silicon n-MOSFETs,” IEEE Electron Device Lett., vol. 24, pp. 248–250, Apr. 2003. [12] S. B. Samavedam, W. J. Taylor, J. M. Grant, J. A. Smith, P. J. Tobin, A. Dip, A. M. Phillips, and R. Liu, “Relaxation of strained-Si layers grown on SiGe buffers,” J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 17, pp. 1424–1429, July 1999. =Ge =Si het[13] D. C. Houghton, “Strain relaxation kinetics in Si erostructures,” J. Appl. Phys., vol. 70, pp. 2136–51, 1991. [14] A. Tasch et al.. (1999) UT–MARLOWE 5.0 Manual. [Online]. Available: http://homer.mer.utexas.edu/TCAD/documentation/manual.pdf [15] G. Abstreiter, H. Brugger, T. Wolf, H. Jorke, and H. J. Herzog, “Strain-induced two-dimensional electron gas in selectively doped superlattices,” Phys. Rev. Lett., vol. 54, pp. 2441–2444, Si=Si Ge 1985. [16] M. I. Alonso and K. Winer, “Raman spectra of c-Si Ge alloys,” Phys. Rev. B, Condens. Matter, vol. 39, no. 14, pp. 10 056–10 062, May 1989. [17] TSUPREM-4, version 2002, Synopsys, Inc., Mountain View, CA, 2003.

Guangrui Xia was born in Handan, China. She received the B.S. degree in materials science and engineering from Tsinghua University, Beijing, China, in 1999, the M.Eng. degree in materials science and engineering from Cornell University, Ithaca, NY, in 2000, and the M.S. degree in electrical engineering from the Massachusetts Institute of Technology (MIT), Cambridge, in 2003, where she is currently pursuing the Ph.D. degree. Her primary research interest is in the area of front-end process integration of strained-Si CMOS.

Hasan M. Nayfeh was born in 1974 in Oak Ridge, TN. He received the B.S. degree from the University of Illinois at Urbana-Champaign in 1996, and the M.S. and Ph.D. degrees from the Massachusetts Institute of Technology, Cambridge, in 1998 and 2003, respectively, all in electrical engineering. His Ph.D. research work focused on the study of carrier transport and electrostatics of strained-Si MOSFETs. He is currently an Advisory Engineer/Scientist with the IBM Semiconductor Research and Development Center, IBM Microelectronics, Hopewell Junction, NY. His research and development work involves meeting the continued need for advancement of nanoscale MOSFET devices through investigation of novel materials and structures.

Minjoo L. Lee, photograph and biography not available at the time of publication.

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 12, DECEMBER 2004

Eugene A. Fitzgerald (M’01) received the B.S. degree from the Massachusetts Institute of Technology (MIT), Cambridge, in 1985, and the Ph.D. degree, both in materials science and engineering, from Cornell University, Ithaca, NY, in 1989. He was a Researcher in lattice-mismatched materials and devices at AT&T Bell Laboratories from 1988 to 1994. In 1994, he became an Associate Professor in the Department of Materials Science and Engineering, MIT, and then Full Professor in 2000. In 1998, he co-founded AmberWave Systems Corporation, Salem, NH. He has coauthored or authored more than 150 papers, predominately in the field of lattice-mismatched materials and devices, and he holds 28 issued U.S. patents. His interests include engineered substrates and devices, in particular, strained-SiGe and III-V-based devices. Dr. Fitzgerald is a member of APS, MRS, TMS, and ECS. He is the recipient of the TMS 1994 Robert Lansing Hardy Medal Award. He became a Fellow in the Singapore-MIT Alliance in 1999. In 2000, he received a Lord Career Development Chair, and in 2003 became the Merton C. Flemings–SMA Professor of Materials Engineering.

Jian Li (M’00) received the B.S. and M.S. degrees in physics from Nanjing University, Nanjing, China, in 1997 and 2000, respectively. He is currently pursuing the Ph.D. degree at the University of Virginia, Charlottesville. He is a member of the Materials Research Society.

Dimitri A. Antoniadis (F’00) was born in Athens, Greece. He received the B.S. degree in physics from the National University of Athens in 1970 and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in 1976. In 1978, he joined Massachusetts Institute of Technology (MIT), Cambridge, where he holds the Ray and Maria Stata Chair in Electrical Engineering. Currently, he is Director of the multi-university Focus Research Center for Materials Structures and Devices centered at MIT. He is the author or coauthor of over 200 technical articles. His present research focuses on the physics and technology of extreme-submicrometer Si, SOI, and Si–SiGe MOSFETs. Dr. Antoniadis is the recipient of several professional awards.

Nancy Klymko, photograph and biography not available at the time of publication.

Dalaver H. Anjum received the B.Sc degree in physics and mathematics from The University of Punjab, Punjab, Pakistan, in 1992, and the M.S. and Ph.D. degrees in physics from The State University of New York at Albany, in 1998 and 2002, respectively. From October 2001 to October 2003, he was with the Department of Materials Science and Engineering, University of Virginia, Charlottesville, as a Postdoctoral Research Associate where he worked on the development of nanoscale stress characterization of SiGe-based MOSFETs. He is now with the Burnham Institute, La Jolla, CA. His research interests are the characterization of both physical and biological materials using AEM.

Robert Hull, photograph and biography not available at the time of publication.

Judy L. Hoyt (SM’83) received the B.S. degree in physics and applied mathematics from the University of California, Berkeley, in 1981, and the Ph.D. degree in applied physics from Stanford University, Stanford, CA, in 1987. From 1988 to 1999, she was on the Research Staff of the Electrical Engineering Department, Stanford University. In January 2000, she became a Faculty Member in the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge. Her primary research interests are in the areas of novel silicon-based heterostructure and nanostructure devices, new processes and materials for advanced device applications, Si epitaxy and chemical vapor deposition, and CMOS front-end processing. She has authored or coauthored 80 publications in these areas, and holds four patents. Dr. Hoyt received the IEEE Electron Devices Society Rappaport Award in 1990. She served as General Chair of the IEEE International Electron Devices Meeting in 2001, and is a member of the Electron Devices Society, the American Physical Society, and the Materials Research Society.