Impact of BEOL, multi-fingered layout design, and gate protection diode on intrinsic MOSFET threshold voltage mismatch G. H. Lim1, X. Zhou1, K. Khu2, Y. K. Yoo2, F. Poh2, G. H. See1, Z. M. Zhu1, C. Q. Wei1, S. H. Lin1, and G. J. Zhu1 Abstract – Continued scaling down of MOSFETs, compounded with limitation in process variation control capabilities, has made MOSFET mismatch more significant for advanced technologies. In order to prevent over compensating for MOSFET mismatch in design margin, it is important to characterize the intrinsic MOSFET mismatch accurately. In this paper, test structures are designed to study the influence of back end of line (BEOL), multi-fingered layout, and gate protection diode (GPD) on MOSFET threshold voltage mismatch characterization.

I. INTRODUCTION Continued scaling down of MOSFETs has aggravated impact of process variation on MOSFET mismatch performance. Effects such as random dopant fluctuation (RDF), line edge and width roughness (LER/LWR), surface roughness of channel-oxide interface, and random oxide trapped charges start to play a significant role in affecting intrinsic MOSFET mismatch performance [1, 2]. This is further complicated by difficulties in monitoring newer processes, such as those for strain engineering in more advanced process technologies, accurately and efficiently. The increasing trend of analog/RF circuits adopting silicon-based MOSFET technology further enhances the importance of MOSFET mismatch, especially if high precision is required [2, 3]. Moreover, MOSFET mismatch is also important in digital circuits such as SRAM, whose stability depends greatly on the matching of MOSFETs [2]. Thus, there is motivation to characterize the intrinsic MOSFET mismatch in a generic and accurate manner so that it can be used in any applications. It also provides accurate benchmarking of MOSFET mismatch characteristics for different technologies in a standard way. The intrinsic MOSFET mismatch characteristics referred here is solely attributed to process variations, and it represents the optimum that can be attained for a particular technology. In this paper, different test structures are designed to seek understanding of how they can affect characterization 1

School of Electrical and Electronic Engineering, Nanyang Technological University. E-mail: [email protected] 2 Chartered Semiconductor Manufacturing Ltd.

of intrinsic MOSFET mismatch. In this way, a generic test structure for MOSFET mismatch characterisation can be attained.

II. MISMATCH TEST STRUCTURES During the design of test structures for MOSFET mismatch characterisation, the most important thing is to ensure that layout design is symmetrical so as to negate the impact of layout on intrinsic MOSFET mismatch characterisation. In this work, the method of a simple symmetrical MOSFET pair layout design [4, 5] as shown in Fig. 1 is used.

Active Polysilicon Metal-1 Metal-2 Fig. 1. Symmetrical MOSFET pair used to study the impact of BEOL on intrinsic MOSFET mismatch.

A. Consideration for BEOL Typically, the impact of BEOL on MOSFET mismatch characteristics is neglected and, thus, the test structure being characterized would encompass the full BEOL of the particular technology. It is possible that this can aggravate the intrinsic MOSFET mismatch characterisation and make it unrealistically large. Furthermore, MOSFETs that require good matching would not involve the full BEOL since only local interconnects, such as polysilicon and first metal layer, would be used in routing. In the study of BEOL impact on MOSFET threshold voltage mismatch, the design in Fig. 1 is adopted. The technology used is the 0.18-μm technology from Chartered

Semiconductor Manufacturing. The full BEOL consists of 6 Al metal layers. Probe pad tiles of 2×12 pads are used and the commongate-common-source (CGCS) configuration is employed [5]. This allows 10 pairs of MOSFET in a single probe pad tile. The MOSFET geometries that are being characterized include: L/W (μm/μm) = 0.22/0.22, 0.18/14.4, 14.4/0.22, 14.4/14.4, and 57.6/57.6. Two wafer splits have been fabricated, with one going through the process flow for full BEOL while the other being stopped at first metal layer (Metal-1). Both n- and p-MOSFETs are designed and fabricated. For both splits, the designed routing involved up to first metal only, while the rest of BEOL are for pads.

former layout design. The 90-nm low-power (LP) technology from Chartered with gate oxide thickness of 21Å is the process employed for this study.

B. Consideration for Multi-fingered MOSFET The use of wide MOSFETs is very common in analog/RF circuits. In order to minimize the impact of parasitic gate resistance, multi-fingered layout is very common. It would be useful to study how the MOSFET mismatch performance is affected in this case. In the study of multi-fingered layout impact on MOSFET threshold voltage mismatch, the basis of symmetrical layout of MOSFET pair in Fig. 1 is strictly adopted. Both 0.13-μm and 90-nm technologies from Chartered are employed. For 0.13-μm, probe pad tiles of 2×12 pads are used and CGCS configuration is employed, which allows 10 pairs of MOSFET in a single probe pad tile. Both n- and p-MOSFETs are fabricated for this study. For 90-nm, probe pad tile of 1×25 pads is used and common-source (CS) configuration is employed [5]. This allows 4 pairs of MOSFET in a single probe pad tile. The design for the multi-fingered MOSFETs includes 2, 4, and 8 fingers while the single or non-fingered MOSFET is used as a control device. Both interleaving and non-interleaving multi-finger MOSFET pairs are designed, and characterized, as illustrated in Figs. 2 and 3, respectively. The sources and drains are shared and dummy poly lines are included. The MOSFET geometries for the single-, 2-, 4-, and 8-finger that are being characterized include: L/W (μm/μm) = 0.13/10.4, 0.13/5.2, 0.13/2.6, and 0.13/1.3 for 0.13-μm technology while for 90-nm technology, L/W (μm/μm) = 0.1/7.2, 0.1/3.6, 0.1/1.8, and 0.1/0.9. C. Consideration for Gate Protection Diode As MOSFETs scale towards the deep-submicron size, the gate oxide becomes thinner and thinner. This thinner thickness arguably makes the gate oxide susceptible to plasma charging damage (PCD) during some plasma processing steps and thus degradation of gate oxide integrity may occur [6, 7]. Since PCD can be considered a random event, it may affect the MOSFET mismatch characteristics for advanced process technology using very thin gate oxide. In order to study the impact of PCD on MOSFET mismatch, n-MOSFET pairs are designed with and without gate protection diode (GPD) [7], with Fig. 4 illustrating the

Fig. 2. Layout design of MOSFET pair that is used to study the impact of non-interleaving multi-fingered MOSFET on intrinsic MOSFET mismatch.

Fig. 3. Layout design of MOSFET pair that is used to study the impact of interleaving multi-fingered MOSFET on intrinsic MOSFET mismatch.

Probe pad tiles of 1×25 pads are used and common-source (CS) configuration is employed [5]. This allows 4 pairs of MOSFET in a single probe pad tile. The MOSFET geometries that are being characterized include: L/W (μm/μm) = 0.1/0.12, 0.1/7.2, 0.72/7.2, 7.2/0.12, 7.2/7.2 and 12.5/12.5.

III. THRESHOLD VOLTAGE MISMATCH CHARACTERISATION In this work, for the figure of merit to characterize and quantify the MOSFET mismatch characteristics, only the threshold voltage mismatch is studied while the simplified Pelgrom model [8] in (1) is applied. A (1) σ ΔVt = vt WL

where the threshold voltage mismatch for multi-fingered layout (interleaved & non-interleaved) relative to non-fingered layout is larger than ~1 mV. Meanwhile, σΔVtlin for non-interleaved layout of different finger sizes always performs better than its interleaved counterparts. 30

S td . D e v ., σ Δ V tlin [m V ]

It establishes a linear relationship between the standard deviation in threshold voltage and the inverse of the square root of the channel area. The mismatch constant (Avt) of the model provides a measure of mismatch performance. The threshold voltages, extracted based on the constant-current criterion defined with reference current 0.1µA×(W/L), are acquired from the drain current vs. gate voltage curves for all technologies with drain-source voltage (Vds) biased at 0.1V. This threshold voltage is referred to as Vtlin. The mismatch in threshold voltage is simply obtained by subtracting the Vtlin of the neighbouring two MOSFETs in the symmetrical MOSFET-pair test structure.

n, full BEOL, Avt=6.3486

25

n, only M1, Avt=6.3836 p, full BEOL, Avt=4.6705

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p, only M1, Avt=4.4295

15 10 5 0 0

1

2

3

4

1/√(area) [1/μm] Gate protection diode

Fig. 4. Layout design of MOSFET pair that is used to study the impact of gate protection diode on intrinsic MOSFET mismatch.

A. Impact of BEOL To study BEOL impact on MOSFET mismatch, Pelgrom plots for characterisation of test structures with full BEOL and only first metal layer for both n- and p-MOSFETs are plotted in Fig. 5. For each device size, 1212 devices have been characterized. For both n- and p-MOSFETs, no great difference in the threshold voltage mismatch constant, Avt, is observed. Though it is observed that for p-MOSFETs, a better Avt of ~0.25 mV-µm can be observed for the test structure with only metal-1 (M1) layer. Furthermore, the Avt of p-MOSFETs is better than n-MOSFETs by ~2 mV-µm for both cases. B. Impact of Multi-fingered MOSFET In the study of multi-fingered layout design impact on MOSFET mismatch, plots of σΔVtlin and µVtlin vs. number of fingers for characterisation results of test structures with non-fingered, interleaved and non-interleaved layout design for both n- and p-MOSFETs are plotted for the 0.13-μm technology, as shown in Fig. 6. For each device type and its finger size, 864 devices have been characterized. For n-MOSFETs using 0.13-μm technology, it is observed that with multi-fingered layout, for both interleaved and non-interleaved, the threshold voltage mismatch is better than non-fingered n-MOSFETs of equivalent channel area, except for finger size of 0.13/5.2,

Fig. 5. Pelgrom plot of n-/p-MOSFETs Vtlin to study the impact of BEOL on MOSFET mismatch characterisation for both n- and p-type using the 0.18-μm technology.

For p-MOSFETs using 0.13-μm technology, it is observed that multi-fingered layout, for both interleaved and non-interleaved, the threshold voltage mismatch is better than non-fingered p-MOSFETs of equivalent channel area. For multi-fingered layout of finger size of 0.13/5.2 and 0.13/2.6, for both interleaved and non-interleaved, the σΔVtlin is similar while for the smallest finger size of 0.13/1.3, σΔVtlin is worse than the former two. The σΔVtlin for both interleaved and non-interleaved matches one another quite closely, though it is observed the former is always slightly better than latter. For both n-/p-MOSFET using 0.13-μm technology, narrow wide effect on the µVtlin can be noticed from Fig. 6, with µVtlin increases with decreasing width. On the other hand, the opposite trend occurs for σΔVtlin of both MOSFET types. There appears to be competing effects influencing the σΔVtlin and these factors are believed to include narrow width and STI stress. For n-MOSFETs using 90-nm technology, 680 devices have been characterized for each finger type and size. Fig. 7 shows the plots of σΔnVtlin and µVtlin vs. number of fingers for characterisation results of test structures with non-fingered, interleaved and non-interleaved multi-fingered layout design. It is observed that with multi-fingered layout, for both interleaved and non-interleaved, the threshold voltage mismatch is better than non-fingered n-MOSFETs of equivalent channel area. Multi-fingered layouts of 0.1/1.8 finger size, for both interleaved and non-interleaved, have the smallest σΔVtlin. The σΔVtlin for interleaved layout of 0.1/3.6 finger size is better than that of its non-interleaved counterpart while for the other two sizes, it is the opposite. Similarly as in previous 0.13-μm case, the reverse narrow wide effect on µVtlin is observed while the opposite trend occurs for µVtlin.

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from the MOSFET to be protected from PCD. Last but not least, PCD may not be as serious as presumed for gate oxide thickness of 21Å [6].

Std. Dev., σΔnVtlin [mV]

90

L 0.1 W 0.12 L 0.1 W 7.2 L 0.72 W 7.2 L 7.2 W 0.12 L 7.2 W 7.2 L 12.5 W 12.5 no GPD, Avt=7.9343 with GPD, Avt=8.8331

80 70 60 50 40 30 20 10 0 0

2

4

6

8

1/√(area) (1/μm)

Fig. 6. σΔVtlin & abs(µVtlin) vs. No. of fingers, for both n- and p-MOSFETs using 0.13-µm technology to study the impact of multi-fingered layout on MOSFET threshold voltage mismatch. The length/width of finger size is indicated below the data point as L/W (μm/μm). 0.62

interleaved σnVtlin non-interleaved σnVtlin 0.6 non-fingered σnVtlin interleaved µVtlin non-interleaved µVtlin 0.58 non-fingered µVtlin

11 10.5 10

0.56

9.5

0.54 0.1/3.6

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0.52 0.1/1.8

0.1/0.9

0.1/7.2

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Mean, µ nVtlin (V) [mV]

Std. Dev., σ ΔnVtlin [mV]

11.5

0.48 0

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2

3

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5

6

7

8

9

Fig. 8. Pelgrom plot of n-MOSFETs Vtlin using 90-nm technology for the study of impact of gate protection diode on MOSFET threshold voltage mismatch. Filled symbols represent data ‘without GDP’ while unfilled symbols represent data ‘with GPD’. Length (L) and width (W) in the legend are in µm.

IV. CONCLUSION The impact of BEOL appears not to be significant for σVtlin for the 0.18-μm technology that uses Al-based BEOL. Multi-fingered layout design for wide MOSFETs is recommended as threshold voltage mismatch is not sacrificed at the expense of better parasitic gate resistance for the 0.13-µm and 90-nm technologies. Use of the gate protection diode in this work to enhance threshold voltage mismatch did not show positive results. Thus, there would be reservations on using GPD to enhance threshold voltage mismatch while further studies are needed.

No. of fingers

Fig. 7. σΔnVtlin & µnVtlin vs. No. of fingers for n-MOSFETs using 90-nm technology to study the impact of multi-fingered layout on MOSFET threshold voltage mismatch. The length/width of finger size is indicated below the data point as L/W (μm/μm).

ACKNOWLEDGEMENTS G. H. Lim gratefully acknowledges support of Chartered Semiconductor Manufacturing for fabrication and characterisation of all MOSFET mismatch test structures. REFERENCES

C. Impact of Gate Protection Diode In the study of GPD impact on MOSFET mismatch, Pelgrom plots for characterisation results of test structures with and without gate protection diode are plotted for n-MOSFETs in Fig. 8. It is observed n-MOSFET threshold voltage mismatch performance is better for test structures without GPD. An Avt difference of ~1 mV-μm is observed. This result contradicts the expectation of using GPD. A straight forward explanation would be that GPD does not enhance MOSFET threshold voltage mismatch but worsens it. It is also possible that the GPD may be effective in plasma charging damage (PCD) protection for only one of the MOSFETs in the MOSFET-pair test structure, hence, it results in a worse threshold voltage mismatch. Further studies are required to investigate the effectiveness of GPD with respect to its size and the distance

[1] [2] [3] [4] [5] [6] [7] [8]

B. P. Wong, A. Mittal, Y. Cao, and G. Starr, Nano-CMOS Circuit and Physical Design: John Wiley & Sons Ltd, pp. 343-385, 2005. J. A. Croon, W. Sansen, and H. E. Maes, Matching Properties of Deep Sub-micron MOS Transistor: Springer, 2005. T. Ytterdal, Y. Cheng, and T. A. Fjeldly, Device Modelling for Analog and RF CMOS Circuit Design: John Wiley & Sons Ltd, pp.271-277, 2003. H. P. Tuinhout, "Design of matching test structures [IC components]," IEEE Proc. ICMTS, pp. 21-27, 1994. H. Tuinhout, "Electrical characterisation of matched pairs for evaluation of integrated circuit technologies," PhD Thesis, Technische Universiteit Delft, pp. 39-71, 2005. K. P. Cheung, "Plasma charging damage - where do we stand?" IEEE Proc. ICICT, pp. 83-86, 2005. P. Mario M. A. Pelella, N.Y., "Process for fabricating a MOS device having protection against electrostatic discharge." United States Patent: IBM, Armonk, N.Y., 1994. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1439, 1989.

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