USO0RE41868E

(19) United States (12) Reissued Patent

(10) Patent Number:

Sano et a]. (54)

US RE41,868 E

(45) Date of Reissued Patent:

SEMICONDUCTOR MEMORY DEVICE

4,380,057 A

*

Oct. 26, 2010

4/1983 Kotecha et al. ........... .. 365/184

(75) Inventors: Toshiaki Sano, TachikaWa (JP);

(Continued)

Yano, Hino (JP); Toshiyuki Mine, Fussa (JP)

EP

0504946

EP

0642173

(73) Assignees: Hitachi, Ltd., Tokyo (JP); Hitachi

8/1994

.

Device Engineering Co., Ltd.,

(Commued)

Chiba-ken (JP)

OTHER PUBLICATIONS

(21) App1_ NO; 11 /708,145

Notice of Reason of Rejection, mailed Jul. 6, 2004iEnglish

_

(22)

9/1992

translation of Examiner’s remarks regarding Reason 1 of

Filed:

Feb. 20, 2007

Claim 2_

Related US. Patent Documents

(Continued)

Reissue of:

(64) Patent No.:

6,040,605

Primary ExamineriNgan Ngo

Issued: Appl. No.:

Mar. 21, 2000 09/236,630

(74) Attorney, Agent, or FirmiAntonelli, Terry, Stout & Kraus, LLP.

Filed:

Jan. 26, 1999

(57)

US. Applications: (60)

Division of application No. 10/101,370, ?led on Mar. 20, 2002, which is a continuation-in-part of application No. 09/126,437, ?led on Jul. 30, 1998, now Pat. No. 6,104,056.

(30)

Foreign Application Priority Data

Jan. 28, 1998

(51)

(52)

(JP) ......................................... .. 10-015369

Int. Cl. H01L 29/76 H01L 29/788

(2006.01) (2006.01)

US. Cl. ........................ .. 257/314; 257/66; 257/315;

257/316; 257/368; 257/369; 257/390; 257/E29.129; 365/185.05; 365/185.13; 365/185.29 (58)

Field of Classi?cation Search ................ .. 257/314,

257/315, 316, E29.129, 66, 368, 369, 390; 365/185.05, 185.13 See application ?le for complete search history. (56)

References Cited

A memory cell With a small surface area is fabricated by

forming source lines and data lines above and beloW and by running the channels to face up and doWn. The local data lines for each vertically stacked memory cell are connected to a global data line by Way of separate selection by a molecular oxide semiconductor, and use of a large surface

area is avoided by making joint use of peripheral circuits such as global data lines and sensing ampli?ers by perform ing read and Write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (?oating electrode cell) Which are non-destructive With respect to readout are utilized to alloW placement of memory

cells at all intersecting points of Word lines and data lines While having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read

verify, Write verify and erase verify operations. A register to temporarily hold Write data in a memory cell during Writing is also used as a register to hold a ?ag shoWing that Writing has ended during Write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values

U.S. PATENT DOCUMENTS 4,242,737 A

ABSTRACT

on the Wme-end ?ag

* 12/1980 Bate ......................... .. 365/184

35 Claims, 48 Drawing Sheets

n BIT /_—A_——?

:

i

J

WORD LINE DRIVER

MEMORY CELL ARRAY

L DATA/ SOURCE LINE DRIVER

1

CONTROLLER REGISTER 1 (n BIT)

REGISTER 2 (n an)

_

US RE41,868 E Page 2

US. PATENT DOCUMENTS

7,110,299 B2 *

9/2006

Forbes ................. .. 365/185.18 Guterman et a1. ......... .. 257/319 Guterman etal. ......... .. 438/257

4,892,840 A

*

l/1990

Esquivel er a1 ----------- -- 438/262

7,449,746 B2 * 11/2008 2004/0063283 A1 * 4/2004

5,272,372 A

* 12/1993

Kuzuhara etal. ......... .. 257/608

2006/0163645 A1 *

7/2006

Guterman etal,

5,313,421 A

*

5/1994

Guterman et a1. .... .. 365/185.15

2007/0004134 A1 *

1/2007

Vora ......................... .. 438/257

5,349,221 A

*

9/1994

Shimoji .................... .. 257/324

2008/0111177 A1 *

5/2008

Maayan et a1. ............ .. 257/315

5,411,905 A

257/316

5/1995 Acovic et a1.

5,412,600 A

5/1995 Nakajima

FOREIGN PATENT DOCUMENTS

5,477,068 A

* 12/1995

OZaWa ..................... .. 257/214

5,508,543 A 5,576,570 A

*

4/1996 Hartstein 61 3.1. 11/1996 Ohsawa et a1. .

257/314 257/369

5,589,700 A

* 12/1996 Nakao ............ ..

257/325

5,612,913 A * 3/1997 Cappelletti et 5,654,577 A 8/1997 Nakamuraetal. 5,684,734 A 11/1997 Ishii et a1. 5,739,569 A

*

4/1998

Chen ........................ .. 257/321

5,768,192 A

*

6/1998

Eitan ..... ..

5,793,087 A

8/1998 Chevallier .... ..

5,838,041 A

* 11/1998

Sakagamiet a1. .

5,850,091 A

* 12/1998 Li et a1. .... ..

6,030,869 A * 2/2000 Odake e131. 6,140,181 A * 10/2000 Forbes et a1.

GB

1297899

11/1972

JP JP

04439859 06_267286

5/1992 9/1994

JP

07057484

“995

JP JP JP

9_2l3822 A 9413822 09413822

8/l996 8/1997 @1997

JP

09_2l3898

8/1997

365/185.24

257/390 257/324

OTHER PUBLICATIONS _

_

257/316

T- 1511111, 61211348343 $1I1g1e*E1eCIrOI1*MemOryC611Struc

438/266 438/257

ture With 2P2 per bit, IEDM 97,pp- 924*926 Yano et a1., “RoomiTemperature singleiElectron

6,232,643 B1 *

5/2001 Forbes @181

~~~~~ -- 257/405

Memory”, IEEE Transactions on Electron Devices, V01. 41,

6,246,606 B1 *

6/2001 Forbes et a1.

.. 365/185.03

NO_9,Sep_1994_

6,614,070 B1 *

9/2003

Hirose et a1. .............. .. 257/316

6,649,972 B2 * 11/2003 Eitan ........................ .. 257/324

* cited by examiner

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