A
B
C
D
E
1
1
Compal confidential
2
2
Schematics Document Mobile Yonah uFCPGA with Intel Calistoga_GM+ ICH7-M core logic 2007-03-23
3
3
REV:1.0
4
4
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
www.vinafix.vn C
D
Title
Compal Electronics, Inc.
Size Document Number Custom LA-3491P Date:
Cover Sheet
Monday, April 02, 2007
Sheet E
Rev 1.0 1
of
47
A
B
C
D
E
Volga 2.0
Compal confidential File Name : LA-3491P
1
1
Fan Control
page 4
Mobile Yonah/Merom uFCPGA-478 CPU
Thermal Sensor ADM1032AR
page 4,5,6
Clock Generator ICS9LP306BGLFT
page 4
page 15
FSB H_A#(3..31)
CRT
533/667MHz
H_D#(0..63)
Intel Calistoga MCH 945GM
page 16
LVDS Conn
DDR2 -400/533/667
PCBGA 1466
page 7,8,9,10,11,12
page 17
DDR2-SO-DIMM X2 BANK 0, 1, 2, 3
page 13,14
Dual Channel
2
2
DMI USB2.0
PCI-E BUS INTEL LAN 82562V 10 /100
LED
Intel ICH7-M
PCI BUS
RTC CKT.
RJ45/11 CONN
page 23
page 19
SATA
SPI ROM
CB-1410
page 25
AMP & Audio Jack TPA6017A2 page 28 3
page 22 PATA Slave
25LF080A page 31
page 24
page 27
SATA HDD Connector
SPI
CardBus Controller
MODEM AMOM CX20548
Audio Conexant CX20549-12
mBGA-652
3
Mini-Card WLAN
page 29
page 26
page 18,19,20,21
page 23
page 31
AC-LINK/Azalia
USB Conn x2
IDE ODD Connector page 22
LPC BUS Power OK CKT.
Slot 0
page 34
page 24
SMSC KBC 1070
Power On/Off CKT.
page 30
page 31
4
Int.KBD
Touch Pad CONN.
DC/DC Interface CKT.
page 32
4
page 30
page 33
Page 37
38
39
2006/10/26
Issued Date
40
A
Compal Secret Data
Security Classification
Power Circuit DC/DC
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
www.vinafix.vn C
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Title
Compal Electronics, Inc.
Size Document Number Custom LA-3491P Date:
Block Diagram
Monday, April 02, 2007
Sheet E
2
Rev 1.0 of
47
5
4
3
2
Symbol Note :
Voltage Rails
D
S0-S1
S3
Adapter power supply (18.5V)
N/A
N/A
N/A
AC or battery power rail for power circuit
N/A
N/A
N/A
Core voltage for CPU
ON
OFF
OFF
1.05V power rail for Processor I/O and MCH/ICH core power ON
Power Plane
Description
VIN B+ +CPU_CORE +VCCP
1
: means Digital Ground
S5
OFF
OFF
+0.9V
0.9V switched power rail for DDRII Vtt
ON
OFF
OFF
+1.5VS
1.5V switched power rail for PCI-E interface
ON
OFF
OFF
+1.8V
1.8V power rail for DDRII
ON
ON
OFF
+2.5VS
2.5V switched power rail for MCH video PLL
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3VS
3.3V switched power rail
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+RTC_VCC
RTC power
ON
ON
ON
: means Analog Ground
D
NOXDP@ : means just build when XDP function disable. LP@ : means just build when Low power clock gen. install BATT@ : means need be mounted when 45 level assy or rework stage. 45@ : means need be mounted when 45 level assy or rework stage. 14@ : means need be mounted when 14.1" WLAN@ : means need be mounted when have wireless LED Function WLAN14@ : means need be mounted when have wireless LED Function and 14" XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work. CONN@ : means ME parts Debug@ : means Mini debug card use
Calistoga 945GM R3 SA0000059L0
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Calistoga 945GM R1 SA0000059A0
C
C
Calistoga 940GML R3 SA000011C10 Calistoga 940GML R1 SA000011C00 ICH7 R3 SA00000V1A0 ICH7 R1 SA00000V1F0 IAT50 945GM FF 46147932L01 IAT50 940GML DF 46147932L02 IAT50 940GML DF 46147932L03 (No WLAN) IAT60 945GM FF 46147932L21
B
B
IAT60 940GML DF 46147932L22 External PCI Devices DEVICE
PCI Device ID
CARD BUS
IDSEL #
D6
REQ/GNT #
AD22
2
IAT60 940GML DF 46147932L23 (No WLAN)
PIRQ C
14" and 15.4" M/B board DA600004Z10 (LA-3491P) For 15.4" Switch board DA200007U10 (LS-3561P) For 15.4" ODD board DA200007V10 (LS-3562P)
I2C / SMBUS ADDRESSING
A
DEVICE
HEX
ADDRESS
DDR SO-DIMM 0
A0
10100000
DDR SO-DIMM 1
A4
10100100
CLOCK GENERATOR (EXT.)
D2
11010010
A
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Document Number
Notes List
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
3
of
47
5
4
3
H_D#[0..63] H_A#[3..31]
C
+VCCP
<7>
<7> <7>
H_LOCK# H_RESET#
H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRDY# H_HIT# H_HITM# H_IERR# H_LOCK# H_RESET#
H_RS#[0..2]
<7>
H_RS#0 H_RS#1 H_RS#2 H_TRDY#
H_TRDY#
B
<20> XDP_DBRESET# <7> H_DBSY# <19> H_DPSLP# <19,40> H_DPRSTP# <7> H_DPWR# <40> H_PROCHOT# +VCCP
1 R15 2 56_0402_5% <19> H_PWRGOOD <7> H_CPUSLP#
R16 R17
2 @ 1K_0402_5% 51_0402_5% 1
1 2
H1 E2 G5 F1 H5 F21 G6 E4 D20 H4 B1
Follow datasheet 12/05
F3 F4 G3 G2
XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3
AD4 AD3 AD1 AC4
XDP_DBRESET# H_DBSY# H_DPSLP# H_DPRSTP# H_DPWR# XDP_BPM#4 XDP_BPM#5 H_PROCHOT#
C20 E1 B5 E5 D24 AC2 AC1 D21
H_PWRGOOD H_CPUSLP# XDP_TCK XDP_TDI XDP_TDO TEST1 TEST2 XDP_TMS XDP_TRST#
D6 D7 AC5 AA6 AB3 C26 D25 AB5 AB6
H_THERMDA H_THERMDC H_THERMTRIP#
<7,19> H_THERMTRIP#
H_THERMDA, H_THERMDC routing together. Trace width / Spacing = 10 / 10 mil
A24 A25 C7
BCLK0 BCLK1
ADS# BNR# BPRI# BR0# DEFER# DRDY# HIT# HITM# IERR# LOCK# RESET#
HOST CLK
CONTROL
RS0# RS1# RS2# TRDY#
DINV0# DINV1# DINV2# DINV3#
BPM0# BPM1# BPM2# BPM3# DBR# DBSY# DPSLP# DPRSTP# DPWR# PRDY# PREQ# PROCHOT#
DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3#
MISC
J26 M26 V23 AC20
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H23 M24 W24 AD23 G22 N25 Y25 AE24
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
XDP_BPM#3 XDP_BPM#2 XDP_BPM#1 XDP_BPM#0
R2200 XDP@ 1K_0402_5% 1 2H_PWRGOOD_R XDP_HOOK1
H_PWRGOOD +VCCP
2 C1455 XDP@
1 0.1U_0402_16V7K
Removed at 5/30.(Follow Chimay) XDP_TCK
A20M# FERR# IGNNE# INIT# LINT0 LINT1
LEGACY CPU
THERMAL DIODE
THERMDA THERMDC THERMTRIP#
STPCLK# SMI#
A6 A5 C4 B3 C6 B4
H_A20M# H_FERR# H_IGNNE# H_INIT# H_INTR H_NMI
D5 A3
H_STPCLK# H_SMI#
1
2
54.9_0402_1%
XDP_TMS
R3
1
2
54.9_0402_1%
XDP_TDO
R4
1
2
54.9_0402_1%
XDP_BPM#5
R5
1
2
54.9_0402_1%
XDP_HOOK1
R2199 1
2 @ 54.9_0402_1%
XDP_TRST#
R6
1
2
51_0402_1%
XDP_TCK
R7
1
2
54.9_0402_1%
D
This shall place near CPU
CLK_CPU_XDP CLK_CPU_XDP#
CLK_CPU_XDP <15> CLK_CPU_XDP# <15>
H_RESET#_R XDP_DBRESET#_R XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PRE
1
R2201 1 R2202 2 XDP@ XDP@
+VCCP
2 1K_0402_1% 1 200_0402_1%
H_RESET# XDP_DBRESET#
R2203 XDP@ 0_0402_5% 2 C
Place R2203 within 200ps (~1") to CPU
+3VS
2
C2 0.1U_0402_16V4Z
1
R13 U1 1
H_THERMDA
2
H_THERMDC
3
THERM#
4
C3 1
2
2200P_0402_50V7K H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
<7> <7> <7> <7>
VDD
SDATA
D-
ALERT#
THERM#
GND
8
ICH_SMBCLK
7
ICH_SMBDATA
6
THERM_SCI#
10K_0402_5%
THERM_SCI#
<20>
5
R14 +3VS
1
ADM1032AR-2_MSOP8
2
Address:1001_101
10K_0402_5%
H_DSTBN#[0..3]
<7>
H_DSTBP#[0..3]
<7>
H_A20M# H_FERR# H_IGNNE# H_INIT# H_INTR H_NMI
SCLK
D+
B
ICH_SMBCLK ICH_SMBDATA
<13,14,15,20,25> ICH_SMBCLK <13,14,15,20,25> ICH_SMBDATA
+5VS
PWM Fan Control circuit
PWRGOOD SLP# TCK TDI TDO TEST1 TEST2 TMS TRST#
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
R2
Thermal Sensor ADM1032AR-2
<19> <19> <19> <19> <19> <19>
JP3 1
D1 CH751H-40_SC76
2
+3VS
H_STPCLK# <19> H_SMI# <19>
FOX_PZ47903-2741-42_YONAH
<30>
1
FAN_PWM THERM#
2
1
C4 4.7U_0805_10V4Z
2
1 2
C5 0.1U_0402_16V4Z
ACES_85205-0200 CONN@
FAN
U2
INB
O
D
G 4
3
S
INA
3
1
+VCCP
TC7SH00FU_SSOP5
Q1 AO6402_TSOP6
@ ZD1 RLZ5.1B_LL34 A
R19 H_DPSLP#
@ 56_0402_5%
@ 56_0402_5% R20 H_DPRSTP# 1 2
2 2
R18
B
C
1 OCP# Q2 @ MMBT3904_SOT23 5
1
2
OCP#
Compal Secret Data
Security Classification 2006/10/26
Issued Date
@ 56_0402_5%
E
H_PROCHOT# 3
GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17
CONN@ SAMTE_BSH-030-01-L-D-A
CONN@ A
GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16
+VCCP
XDP_TDI
1 2 5 6
R12 56_0402_5% 1 2
A22 A21
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
XDP_BPM#5 XDP_BPM#4
1
Change value in 5/02
JP29
5
CLK_CPU_BCLK CLK_CPU_BCLK#
<15> CLK_CPU_BCLK <15> CLK_CPU_BCLK#
XDP_DBRESET#_R
Change to same as Chimay 4/6
1
ADSTB0# ADSTB1#
ITP-XDP Connector
R10 2 @ 1K_0402_5%
2
REQ0# REQ1# REQ2# REQ3# REQ4#
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
1
L2 V4
DATA GROUP
E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26
2
H_ADSTB#0 H_ADSTB#1
ADDR GROUP
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#
1
K3 H2 K2 J3 L5
+3VS
YONAH
2
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31#
4
<7> H_ADSTB#0 <7> H_ADSTB#1
J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1
P
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
<7> H_REQ#[0..4]
H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRDY# H_HIT# H_HITM#
<7>
JP1A
D
<7> <7> <7> <7> <7> <7> <7> <7>
1
G
<7>
2
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
<20,30,42>
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Yonah CPU in mFCPGA479
Document Number
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
4
of
47
4
3
Length match within 25 mils The trace width 18 mils space <40> VCCSENSE 7 mils <40> VSSSENSE
1
+VCC_CORE
2 1
R22 100_0402_1% 2
1
R23 100_0402_1% 1 2
VCCSENSE
VSSSENSE
2
R24 2K_0402_1%
Close to CPU pin AD26 within 500mils.
C
1
2
+VCC_CORE VCCSENSE VSSSENSE
1
2
Close to CPU pin within 500mils.
CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
133
0
0
1
166
0
1
1
H_PSI#
<40> <40> <40> <40> <40> <40> <40>
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
R28 54.9_0402_1% 2 1
R27 27.4_0402_1% 2 1
R26 54.9_0402_1% 2 1
H_PSI#
AE6
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
AD6 AF5 AE5 AF4 AE3 AF2 AE2 AD26
V_CPU_GTLREF <15> CPU_BSEL0 <15> CPU_BSEL1 <15> CPU_BSEL2
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
B22 B23 C21
COMP0 COMP1 COMP2 COMP3
R26 U26 U1 V1 E7 AB20 AA20 AF20 AE20 AB18 AB17 AA18 AA17 AD18 AD17 AC18 AC17 AF18 AF17
+VCC_CORE
R25 27.4_0402_1% 2 1
AF7 AE7
K6 J6 M6 N6 T6 R6 K21 J21 M21 N21 T21 R21 V21 W21 V6 G21
+VCCP
<40>
Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal.
1
JP1B
B26
+1.5VS
C6 0.01U_0402_16V7K
R21 1K_0402_1%
V_CPU_GTLREF
C7 10U_0805_10V4Z
+VCCP D
2
JP1C
VCCSENSE VSSSENSE VCCA VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP PSI# VID0 VID1 VID2 VID3 VID4 VID5 VID6 GTLREF BSEL0 BSEL1 BSEL2 COMP0 COMP1 COMP2 COMP3 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
YONAH
POWER, GROUNG, RESERVED SIGNALS AND NC
5
B
D2 F6 D3 C1 AF1 D22 C23 C24 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 T22 B25
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AB26 AA25 AD25 AE26 AB23 AC24 AF24 AE23 AA22 AD22 AC21 AF21 AB19 AA19 AD19 AC19 AF19 AE19 AB16 AA16 AD16 AC16 AF16 AE16 AB13 AA14 AD13 AC14 AF13 AE14 AB11 AA11 AD11 AC11 AF11 AE11 AB8 AA8 AD8 AC8 AF8 AE8 AA5 AD5 AC6 AF6 AB4 AC3 AF3 AE4 AB1 AA2 AD2 AE1 B6 C5 F5 E6 H6 J5 M5 L6 P6 R5 V5 U6 Y6 A4 D4 E3 H3 G4 K4 L3 P3 N4 T4 U3 Y3 W4 D1 C2 F2 G1
AE18 AE17 AB15 AA15 AD15 AC15 AF15 AE15 AB14 AA13 AD14 AC13 AF14 AE13 AB12 AA12 AD12 AC12 AF12 AE12 AB10 AB9 AA10 AA9 AD10 AD9 AC10 AC9 AF10 AF9 AE10 AE9 AB7 AA7 AD7 AC7 B20 A20 F20 E20 B18 B17 A18 A17 D18 D17 C18 C17 F18 F17 E18 E17 B15 A15 D15 C15 F15 E15 B14 A13 D14 C13 F14 E13 B12 A12 D12 C12 F12 E12 B10 B9 A10 A9 D10 D9 C10 C9 F10 F9 E10 E9 B7 A7 F7
FOX_PZ47903-2741-42_YONAH CONN@
D
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
YONAH
POWER, GROUND
K1 J2 M2 N1 T1 R2 V2 W1 A26 D26 C25 F25 B24 A23 D23 E24 B21 C22 F22 E21 B19 A19 D19 C19 F19 E19 B16 A16 D16 C16 F16 E16 B13 A14 D13 C14 F13 E14 B11 A11 D11 C11 F11 E11 B8 A8 D8 C8 F8 E8 G26 K26 J25 M25 N26 T26 R25 V25 W26 H24 G23 K23 L24 P24 N23 T23 U24 Y24 W23 H21 J22 M22 L21 P21 R22 V22 U21 Y21
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
C
B
FOX_PZ47903-2741-42_YONAH CONN@
A
A
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Yonah CPU in mFCPGA479
Document Number
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
5
of
47
5
4
3
2
1
+VCC_CORE
D
1 Place these capacitors on L8 (North side,Secondary Layer)
2
D
1
C8 10U_0805_6.3V6M
2
1
C9 10U_0805_6.3V6M
2
1
C10 10U_0805_6.3V6M
2
1
C11 10U_0805_6.3V6M
2
1
C12 10U_0805_6.3V6M
2
1
C13 10U_0805_6.3V6M
2
C14 10U_0805_6.3V6M
1
2
C15 10U_0805_6.3V6M
+VCC_CORE
1 Place these capacitors on L8 (North side,Secondary Layer)
2
1
C16 10U_0805_6.3V6M
2
1
C17 10U_0805_6.3V6M
2
1
C18 10U_0805_6.3V6M
2
1
C19 10U_0805_6.3V6M
2
1
C20 10U_0805_6.3V6M
2
1
C21 10U_0805_6.3V6M
2
C22 10U_0805_6.3V6M
1
2
C23 10U_0805_6.3V6M
+VCC_CORE
1 Place these capacitors on L8 (Sorth side,Secondary Layer)
C
2
1
C24 10U_0805_6.3V6M
2
1
C25 10U_0805_6.3V6M
2
1
C26 10U_0805_6.3V6M
2
1
C27 10U_0805_6.3V6M
2
1
C28 10U_0805_6.3V6M
2
1
C29 10U_0805_6.3V6M
2
C30 10U_0805_6.3V6M
1
2
C31 10U_0805_6.3V6M
C
+VCC_CORE
1 Place these capacitors on L8 (Sorth side,Secondary Layer)
2
1
C32 10U_0805_6.3V6M
2
1
C33 10U_0805_6.3V6M
2
1
C34 10U_0805_6.3V6M
2
1
C35 10U_0805_6.3V6M
2
1
C36 10U_0805_6.3V6M
2
1
C37 10U_0805_6.3V6M
2
C38 10U_0805_6.3V6M
1
2
C39 10U_0805_6.3V6M
Mid Frequence Decoupling
+VCC_CORE 330U_D2E_2.5VM_R7
1 +
C40 330U_D2E_2.5VM_R7
1 C41
2
+
1
2
1
+
C42
330U_D2E_2.5VM_R7
C43
2
+
1 C44
2
ESR <= 1.5m ohm Capacitor > 1980uF
1
+
C45
2
+ 2
B
@ 330U_D2E_2.5VM_R7
330U_D2E_2.5VM_R7
B
02/26 Change C43 C44 C45 to 1.9mm height for PV build short term solution
330U_D2E_2.5VM_R7
03/27 After ME update tooling, change to height 2.8mm +VCCP
1 +
C47 330U_D2E_2.5VM_R9
2
1
2
C48 0.1U_0402_10V6K
1
2
1
C49 0.1U_0402_10V6K
2
1
C50 0.1U_0402_10V6K
2
C51 0.1U_0402_10V6K
1
2
1
C52 0.1U_0402_10V6K
2
C53 0.1U_0402_10V6K
A
A
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. CPU Bypass capacitors
Document Number
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
6
of
47
H_XSCOMP/H_YSCOMP trace width and spacing is 5/20.
R32 54.9_0402_1% 2 1
J13 H_VREF K13 H_XRCOMP E1 H_XSCOMP E2 H_YRCOMP Y1 H_YSCOMP U1 H_SWNG0 E4 H_SWNG1 W1 R38 24.9_0402_1% 2 1
R37 24.9_0402_1% 2 1
B
HVREF0 HVREF1 HXRCOMP HXSCOMP HYRCOMP HYSCOMP HXSWING HYSWING
HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HADSTB#0 HADSTB#1 HCLKN HCLKP HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 HDINV#0 HDINV#1 HDINV#2 HDINV#3 HCPURST# HADS# HTRDY# HDPWR# HDRDY# HDEFER# HHITM# HHIT# HLOCK# HBREQ0# HBNR# HBPRI# HDBSY# HCPUSLP# HRS0# HRS1# HRS2#
<4> <20> <20> <20> <20>
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
<20> <20> <20> <20>
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
<20> <20> <20> <20>
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
<20> <20> <20> <20>
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
<13> <13> <14> <14> H_REQ#[0..4]
D8 G8 B8 F8 A8
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
B9 C13
H_ADSTB#0 H_ADSTB#1
AG1 AG2
CLK_MCH_BCLK# CLK_MCH_BCLK
K4 T7 Y5 AC4 K3 T6 AA5 AC5
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
J7 W8 U3 AB10
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
B7 E8 E7 J9 H8 C3 D4 D3 B3 C7 C6 F6 A7 E3
H_RESET# H_ADS# H_TRDY# H_DPWR# H_DRDY# H_DEFER# H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY# H_CPUSLP#
B4 E6 D6
H_RS#0 H_RS#1 H_RS#2
<13> <13> <14> <14>
<4>
<13> <13> <14> <14> H_ADSTB#0 H_ADSTB#1
<4> <4>
<4>
<13> <13> <14> <14> R29
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_RS#[0..2]
AC35 AE39 AF35 AG39
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
AE37 AF41 AG37 AH41
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
AC37 AE41 AF37 AG41
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
AY35 AR1 AW7 AW40
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
AW35 AT1 AY7 AY40
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB
AU20 AT20 BA29 AY29
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
AW13 AW12 AY21 AW21
M_ODT0 M_ODT1 M_ODT2 M_ODT3
M_OCDOCMP0 M_OCDOCMP1
AL20 AF10
M_ODT0 M_ODT1 M_ODT2 M_ODT3
BA13 BA12 AY20 AU21
SMRCOMPN SMRCOMPP
DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3 DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3 DMITXN0 DMITXN1 DMITXN2 DMITXN3 DMITXP0 DMITXP1 DMITXP2 DMITXP3
SM_CK0# SM_CK1# SM_CK2# SM_CK3# SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 SM_CS0# SM_CS1# SM_CS2# SM_CS3# SM_OCDCOMP0 SM_OCDCOMP1
<20,40> DPRSLPVR
R33
<18,20,22,24,25,30,31>
PLT_RST#
<20,40> VGATE_INTEL <20,30> PM_POK
R35 R36
1 1
2 @ 0_0402_5% 2 0_0402_5%
G28 F25 H26 G6 AH33 AH34
PM_BMBUSY# PM_EXTTS0# PM_EXTTS1# PM_THERMTRIP# PWROK RSTIN# ICH_SYNC#
PWROK CALISTOGA_FCBGA1466~D
Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.
MCH_SSCDREFCLK# <15> MCH_SSCDREFCLK <15>
GMCH_H32
H32
A3 A39 A4 A40 AW1 AW41 AY1 BA1 BA2 BA3 BA39 BA40 BA41 C1 AY41 B2 B41 C41 D1
C
T32 R32 F3 F7 AG11 AF11 H7 J19 A41 A34 D28 D27 A35
DDR_THERM#
PM_EXTTS#1
1 1 R47 2 1
221_0603_1%
H_SWNG0 0.1U_0402_16V4Z C55
1 R46 2
221_0603_1%
100_0402_1%
B
R39 2 1 10K_0402_5% R40 2 1 @ 10K_0402_5%
M_OCDOCMP0 M_OCDOCMP1
2
R43 40.2_0402_1% 2 1
100_0402_1%
R42 40.2_0402_1% 2 1
2 1 R45
1
@
R44 GMCH_H32
1
2 CLKREQC# 0_0402_5%
CLKREQC#
<15>
@
A
H_SWNG1
5
R50
1
2
0.1U_0402_16V4Z C56
2
2
R49
1
100_0402_1%
2
2
1
0.1U_0402_16V4Z
C57
200_0402_1%
1
H_VREF 100_0402_1%
1 R48
CLK_MCH_REF# <15> CLK_MCH_REF <15>
C40 MCH_SSCDREFCLK# D41 MCH_SSCDREFCLK
2
+VCCP
V_DDR_MCH_REF C54 0.1U_0402_16V4Z
<13,14> V_DDR_MCH_REF
+VCCP
2
CLK_MCH_3GPLL <15> CLK_MCH_3GPLL# <15>
CLK_MCH_REF# CLK_MCH_REF
A27 A26
D
100_0402_1%
+VCCP
1
AG33 CLK_MCH_3GPLL AF33 CLK_MCH_3GPLL#
MCH_CLKSEL0 <15> MCH_CLKSEL1 <15> MCH_CLKSEL2 <15> T1 T2 CFG5 <11> T3 CFG7 <11> T4 CFG9 <11> T5 CFG11 <11> CFG12 <11> CFG13 <11> T6 T7 CFG16 <11> T8 CFG18 <11> CFG19 <11> CFG20 <11>
+3VS
Layout Note: Route as short as possible
R41
R51
RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5 RESERVED6 RESERVED7 RESERVED8 RESERVED9 RESERVED10 RESERVED11 RESERVED12 RESERVED13
+1.8V
Layout Note: H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / H_SWNG1 trace width and spacing is 18/20.
2
NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 CFG3 PAD CFG4 PAD CFG5 CFG6 PAD CFG7 CFG8 PAD CFG9 CFG10 PAD CFG11 CFG12 CFG13 CFG14 PAD CFG15 PAD CFG16 CFG17 PAD CFG18 CFG19 CFG20
K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26
<4>
CALISTOGA_FCBGA1466~D
A
CLK_REQ#
SM_VREF0 SM_VREF1
K28
<18> MCH_ICH_SYNC#
D_REF_SSCLKN D_REF_SSCLKP
SM_RCOMPN SM_RCOMPP
<20> PM_BMBUSY# PM_BMBUSY# DDR_THERM# 0_0402_5% PM_EXTTS#1 1 2 H_THERMTRIP# <4,19> H_THERMTRIP# PWROK PLTRST_R# 2 1 R34 100_0402_1%
D_REF_CLKN D_REF_CLKP
SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3
AK1 AK41
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 G_CLKP G_CLKN
SM_CK0 SM_CK1 SM_CK2 SM_CK3
AV9 AT9
V_DDR_MCH_REF
<13,14> DDR_THERM# H_RESET# <4> H_ADS# <4> H_TRDY# <4> H_DPWR# <4> H_DRDY# <4> H_DEFER# <4> H_HITM# <4> H_HIT# <4> H_LOCK# <4> H_BR0# <4> H_BNR# <4> H_BPRI# <4> H_DBSY# <4> H_CPUSLP# <4>
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
2 80.6_0402_1% 2 80.6_0402_1%
1 1
R30
<4> <4> <4> <4>
AE35 AF39 AG35 AH39
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
+1.8V
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB
<13> <13> <14> <14>
CLK_MCH_BCLK# <15> CLK_MCH_BCLK <15> H_DSTBN#[0..3] <4>
H_DSTBP#[0..3]
Description at page11.
U3B
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
CFG
H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14
PM
R31 54.9_0402_1% 2 1
+VCCP
HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#
DDR MUXING
C
HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#
1
CLK
D
H_A#[3..31]
U3A F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8
2
DMI
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
3
NC
H_D#[0..63]
HOST
<4>
4
RESERVED
5
Stuff R42 & R43 for A1 Calistoga Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Document Number
Calistoga (1/6)
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
7
of
47
5
4
3
2
1
D
D
<13> DDR_A_DQS[0..7]
C
<13> DDR_A_DQS#[0..7]
<13> DDR_A_MA[0..13]
AU12 AV14 BA20
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5
DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13
AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12
DDR_A_CAS# DDR_A_RAS# DDR_A_WE# SA_RCVENIN# SA_RCVENOUT#
AY13 AW14 AY14 AK23 AK24
U3E
SA_BS0 SA_BS1 SA_BS2
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13
DDR SYS MEMORY A
<13> DDR_A_DM[0..7]
DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2
B
<13> DDR_A_CAS# <13> DDR_A_RAS# <13> DDR_A_WE# T9 PAD T11 PAD
SA_CAS# SA_RAS# SA_WE# SA_RCVENIN# SA_RCVENOUT#
AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
DDR_A_D[0..63]
<13> <14> DDR_B_BS#0 <14> DDR_B_BS#1 <14> DDR_B_BS#2 <14> DDR_B_DM[0..7]
<14> DDR_B_DQS[0..7]
<14> DDR_B_DQS#[0..7]
<14> DDR_B_MA[0..13]
<14> DDR_B_CAS# <14> DDR_B_RAS# <14> DDR_B_WE# T10 PAD T12 PAD
DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2
AT24 AV23 AY28
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7
AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5
DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13
AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23
DDR_B_CAS# DDR_B_RAS# DDR_B_WE# SB_RCVENIN# SB_RCVENOUT#
AR24 AU23 AR27 AK16 AK18
CALISTOGA_FCBGA1466~D
SB_BS0 SB_BS1 SB_BS2
SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13
DDR SYS MEMORY B
U3D <13> DDR_A_BS#0 <13> DDR_A_BS#1 <13> DDR_A_BS#2
SB_CAS# SB_RAS# SB_WE# SB_RCVENIN# SB_RCVENOUT#
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3
DDR_B_D[0..63]
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
<14>
C
B
CALISTOGA_FCBGA1466~D
A
A
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Document Number
Calistoga (2/6)
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
8
of
47
5
4
3
2
1
D
D
PEGCOMP trace width and spacing is 18/25 mils.
U3C
LVDSA0+ LVDSA1+ LVDSA2+
<17> <17> <17>
LVDSA0LVDSA1LVDSA2LVDSB0+ LVDSB1+ LVDSB2+
<17> <17> <17>
LVDSB0LVDSB1LVDSB2-
1
ENABLT
2
LVDSAC+ LVDSACLVDSBC+ LVDSBC-
<17> BKLT_CTL <17,30> ENABLT R2211 1 +3VS R2212 1
100K_0402_5%
<17> LCD_CLK <17> LCD_DAT <17> ENAVDD R54
LVDSA0+ LVDSA1+ LVDSA2+
B37 B34 A36
LVDSA0LVDSA1LVDSA2-
C37 B35 A37
LVDSB0+ LVDSB1+ LVDSB2+
F30 D29 F28
LVDSB0LVDSB1LVDSB2-
G30 D30 F29
LVDSAC+ LVDSACLVDSBC+ LVDSBC-
A32 A33 E26 E27
BKLT_CTL ENABLT 2 10K_0402_5% 2 10K_0402_5% LCD_CLK LCD_DAT ENAVDD 2 1 LIBG 1.5K_0402_1%
1
+1.5VS +1.5VS +1.5VS
R55 10K_0402_5%
R2172 R2173 R2174
COMPS 2 0_0402_5% LUMA 2 0_0402_5% 2 0_0402_5%CRMA
1 1 1
1 2 R57 0_0603_5% 1 2 R2251 0_0402_5%
+1.5VS
R56
+1.5VS
2
2
10K_0402_5%
LCD_CLK LCD_DAT
J20 B16 B18 B19 J29 K30
2
3
HSYNC D2
<16>
CRT_GRN
<16>
CRT_RED
1
@ PACDN042_SOT23~D
VSYNC
VSYNC HSYNC
<16> VSYNC <16> HSYNC <16> CRT_BLU
2
1
CRT_IREF
H23 G23 E23 D23 C22 B22 A21 B21 J22
LA_DATA#0 LA_DATA#1 LA_DATA#2 LB_DATA0 LB_DATA1 LB_DATA2 LB_DATA#0 LB_DATA#1 LB_DATA#2 LA_CLK LA_CLK# LB_CLK LB_CLK# LBKLT_CTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL TVDAC_A TVDAC_B TVDAC_C TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC TV_DCONSEL1 TV_DCONSEL0
DDCCLK DDCDATA VSYNC HSYNC BLUE BLUE# GREEN GREEN# RED RED#
CRT
C26 C25
<16> CRT_SMBCLK <16> CRT_SMBDAT
B
A16 C18 A19
EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15
LA_DATA0 LA_DATA1 LA_DATA2
TV
1
+3VS
D32 J30 H30 H29 G26 G25 F32 B38 C35 C33 C32
EXP_COMPI EXP_COMPO
LVDS
<17> <17> <17>
<17> <17> <17> <17>
R53 C
<17> <17> <17>
SDVOCTRL_DATA SDVOCTRL_CLK
CRT_IREF
R58 255_0402_1%
PCI-EXPRESS GRAPHICS
H27 H28
EXP_RXP0 EXP_RXP1 EXP_RXP2 EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15 EXP_TXN0 EXP_TXN1 EXP_TXN2 EXP_TXN3 EXP_TXN4 EXP_TXN5 EXP_TXN6 EXP_TXN7 EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15 EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15
D40 D38
PEGCOMP
1
+1.5VS_PCIE R52 24.9_0402_1% 2
F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38 D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38
C
F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40 D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40
B
CALISTOGA_FCBGA1466~D
A
A
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Document Number
Calistoga (3/6)
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
9
of
47
5
4
3
2
1
+1.5VS_DPLLA
Place close to Pin G41
1 2 R59 0_1206_5% +2.5VS 1
C59 0.1U_0402_16V4Z U3H
+1.5VS
E21 F21 G21
MCH_CRTDAC
2
2
+1.5VS_DPLLA +1.5VS_DPLLB +1.5VS_HPLL
VCCA_LVDS VSSA_LVDS
A38 B39
+2.5VS
VCCA_MPLL
AF2
VCCA_TVBG VSSA_TVBG
H20 G20
2
1
2
C
12/28
PCI-E/MEM/PSB PLL decoupling
R2221 2
1
0_0402_5% +1.5VS_3GPLL
R2222
E19 F19 C20 D20 E20 F20
2
0_0402_5% R2224 2 1
+1.5VS
+1.5VS R64 1 2 0.5_0805_1%
1
0_0402_5% R2223 2 1
1
1
2
R65 3GPLL 2 1 0_0805_5%
C79
2
0_0402_5%
2 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40
2
+3VS 1
1
2
2
+1.5VS_HPLL
+1.5VS_MPLL
0_0402_5%
A23 B23 B25 AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14
1 R67 2 1 0_0805_5%
45mA Max.
C86 1
10U_0805_6.3V6M
2
1
2
+1.5VS
R68 2 1 0_0805_5%
45mA Max. 1
C88 10U_0805_6.3V6M
2
1
2
+1.5VS
C90 10U_0805_6.3V6M
B
+1.5VS
1
2
+VCCP
+1.5VS 2
VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31
+1.5VS R2225
D21 H19
D3 CH751H-40_SOD323 @
D4 CH751H-40_SOD323 @ 1 1
VCCHV0 VCCHV1 VCCHV2
+1.5VS
+2.5VS
R70
+3VS
R71
@ 10_0402_5%
@ 10_0402_5% 2
VCCD_TVDAC VCCDQ_TVDAC
2
@ 10U_0805_6.3V6M
2
VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2
A28 B28 C28
1
C89
AH1 AH2
+2.5VS
0.1U_0402_16V4Z
VCCD_HMPLL0 VCCD_HMPLL1
2
C80 0.1U_0402_16V4Z
VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1
+1.5VS_MPLL
@ 2
BLM11A601S_0603 L3 1
+1.5VS
P O W E R
+
2
10U_0805_6.3V6M
C64 220U_D2_2VM_R9
1
+1.5VS
C75 0.1U_0402_16V4Z
+1.5VS_3GPLL +2.5VS
B26 C39 AF1
VCCA_DPLLA VCCA_DPLLB VCCA_HPLL
1
AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12
AC33 G41 H41
1 C66
2
1 1
2
+ 2
1 C65
+
2
D
1 1
2
MCH_D2
1
C94 0.47U_0603_10V7K MCH_AB1
2
C93 0.22U_0603_10V7K
C91 0.22U_0603_10V7K
1
1
C87
2 B
10U_0805_6.3V6M
W=40 mils
0.1U_0402_16V4Z
1
C84 0.47U_0603_10V7K
MCH_A6
VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC2
R60 0_0805_5% 2 1
C78 0.1U_0402_16V4Z
2
VCCA_3GPLL VCCA_3GBG VSSA_3GBG
AB41 AJ41 L41 N41 R41 V41 Y41
C85 0.1U_0402_16V4Z
C67 220U_D2_2VM_R9
1
VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6
+1.5VS_PCIE
1 1
C92 0.1U_0402_16V4Z
2
C77 2.2U_0805_16V4Z
C76 4.7U_0805_10V4Z
1
B30 C30 A30
2
+2.5VS
2
L2 @ CHB1608U301_0603 1 +1.5VS
C61 330U_D2E_2.5VM
C
VCCTX_LVDS0 VCCTX_LVDS1 VCCTX_LVDS2
1
2
+1.5VS
C63 0.1U_0402_16V4Z
+ 2
VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VTT33 VTT34 VTT35 VTT36 VTT37 VTT38 VTT39 VTT40 VTT41 VTT42 VTT43 VTT44 VTT45 VTT46 VTT47 VTT48 VTT49 VTT50 VTT51 VTT52 VTT53 VTT54 VTT55 VTT56 VTT57 VTT58 VTT59 VTT60 VTT61 VTT62 VTT63 VTT64 VTT65 VTT66 VTT67 VTT68 VTT69 VTT70 VTT71 VTT72 VTT73 VTT74 VTT75 VTT76
H22
+1.5VS_DPLLB
L1 CHB1608U301_0603 2 1
C60 330U_D2E_2.5VM
1
AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1
VCC_SYNC
+1.5VS_DPLLA
C62 0.1U_0402_16V4Z
+VCCP
C74 2200P_0402_50V7K
D
C58 0.1U_0402_16V4Z
+2.5VS
+1.5VS_DPLLB
CALISTOGA_FCBGA1466~D
A
A
Compal Secret Data
Security Classification
www.vinafix.vn 2006/10/26
Issued Date
2006/07/26
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Date:
Compal Electronics, Inc. Document Number
Calistoga (4/6)
Rev 1.0
LA-3491P Monday, April 02, 2007
Sheet 1
10
of
47
5
4
3
2
1
Strap Pin Table CFG[3:17] have internal pull up
2
2
2
10U_0805_6.3V6M
1 + 2
1 + 2
330U_D2E_2.5VM_R9
C110
C109 220U_D2_2VM_R9
C
C115
1 + 2
B
330U_D2E_2.5VM_R9
@
@
VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12
AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17
+VCCP VCC100 VCC101 VCC102 VCC103 VCC104 VCC105 VCC106 VCC107 VCC108 VCC109 VCC110
+1.8V VCC_SM100 VCC_SM101 VCC_SM102 VCC_SM103 VCC_SM104 VCC_SM105 VCC_SM106 VCC_SM107
AR6 AP6 AN6 AL6 AK6 AJ6 AV1 VCCSM_LF2 AJ1 VCCSM_LF1 C117 0.47U_0603_10V7K
M19 L19 N18 M18 L18 P17 N17 M17 N16 M16 L16
CALISTOGA_FCBGA1466~D
1
2
1
2
Place near pin AV1 & AJ1
C98 0.47U_0603_10V7K
C97 0.47U_0603_10V7K
2
1
2
CFG5 CFG7
0 = Reserved 1 = Mobile Yonah CPU
CFG9
0 = Lane Reversal Enable * 1 = Normal Operation (Default)
2
1 C105
2
1
2
00 01 10 11
= = = =
Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation *(Default)
CFG16
0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled
CFG18
0 = 1.05V 1 = 1.5V
CFG19
0 = Normal Operation * (Default) 1 = DMI Lane Reversal Enable
*(Default)
*(Default)
0 = No SDVO Device Present (Default)
SDVO_CTRLDATA
*
1 = SDVO Device Present
CFG20 (PCIE/SDVO select)
0 = Only PCIE or SDVO is operational. *(Default) 1 = PCIE/SDVO are operating simu.
C
1
2
Place near pin BA23 1 C113
*
(According to Intel Napa Schematic Checklist & CRB Rev1.301 document 2.2Kohm pull-down resistor
+1.8V
1
D
*(Default)
1 = Reserved request)
CFG[13:12]
2
*(Default)
0 = Calistoga
Place near pin AT41 & AM41
1
= 667MT/s FSB = 533MT/s FSB
0 = DMI x 2 1 = DMI x 4
CFG11
0.1U_0402_16V4Z
P O W E R
1
C104
1
011 001
CFG[2:0]
VCCSM_LF4 VCCSM_LF5
0.1U_0402_16V4Z
1
AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6
0.1U_0402_16V4Z
C107
VCC_SM0 VCC_SM1 VCC_SM2 VCC_SM3 VCC_SM4 VCC_SM5 VCC_SM6 VCC_SM7 VCC_SM8 VCC_SM9 VCC_SM10 VCC_SM11 VCC_SM12 VCC_SM13 VCC_SM14 VCC_SM15 VCC_SM16 VCC_SM17 VCC_SM18 VCC_SM19 VCC_SM20 VCC_SM21 VCC_SM22 VCC_SM23 VCC_SM24 VCC_SM25 VCC_SM26 VCC_SM27 VCC_SM28 VCC_SM29 VCC_SM30 VCC_SM31 VCC_SM32 VCC_SM33 VCC_SM34 VCC_SM35 VCC_SM36 VCC_SM37 VCC_SM38 VCC_SM39 VCC_SM40 VCC_SM41 VCC_SM42 VCC_SM43 VCC_SM44 VCC_SM45 VCC_SM46 VCC_SM47 VCC_SM48 VCC_SM49 VCC_SM50 VCC_SM51 VCC_SM52 VCC_SM53 VCC_SM54 VCC_SM55 VCC_SM56 VCC_SM57 VCC_SM58 VCC_SM59 VCC_SM60 VCC_SM61 VCC_SM62 VCC_SM63 VCC_SM64 VCC_SM65 VCC_SM66 VCC_SM67 VCC_SM68 VCC_SM69 VCC_SM70 VCC_SM71 VCC_SM72 VCC_SM73 VCC_SM74 VCC_SM75 VCC_SM76 VCC_SM77 VCC_SM78 VCC_SM79 VCC_SM80 VCC_SM81 VCC_SM82 VCC_SM83 VCC_SM84 VCC_SM85 VCC_SM86 VCC_SM87 VCC_SM88 VCC_SM89 VCC_SM90 VCC_SM91 VCC_SM92 VCC_SM93 VCC_SM94 VCC_SM95 VCC_SM96 VCC_SM97 VCC_SM98 VCC_SM99
C103
1
VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99
0.1U_0402_16V4Z
C106
C108 1U_0603_10V4Z
10U_0805_6.3V6M
AA33 W33 P33 N33 L33 J33 AA32 Y32 W32 V32 P32 N32 M32 L32 J32 AA31 W31 V31 T31 R31 P31 N31 M31 AA30 Y30 W30 V30 U30 T30 R30 P30 N30 M30 L30 AA29 Y29 W29 V29 U29 R29 P29 M29 L29 AB28 AA28 Y28 V28 U28 T28 R28 P28 N28 M28 L28 P27 N27 M27 L27 P26 N26 L26 N25 M25 L25 P24 N24 M24 AB23 AA23 Y23 P23 N23 M23 L23 AC22 AB22 Y22 W22 P22 N22 M22 L22 AC21 AA21 W21 N21 M21 L21 AC20 AB20 Y20 W20 P20 N20 M20 L20 AB19 AA19 Y19 N19
C102
2
AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15
CFG[19:18] have internal pull down
+1.8V
U3G
C111 0.47U_0603_10V7K
2
1
VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57
C118 0.47U_0603_10V7K
2
1
C101 0.22U_0603_10V7K
1
C100 0.22U_0603_10V7K
C99 0.22U_0603_10V7K
D
VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72
P O W E R
AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18
+VCCP
+1.5VS
1
C114
2 10U_0805_6.3V6M
1
2
+ C112 2
@ 220U_D2_4VM
<7>
CFG5
<7>
CFG7
<7>
CFG9
<7>
CFG11
<7>
CFG12
<7>
CFG13
<7>
CFG16
R72
1
2 @
2.2K_0402_5%
R73
1
2 @
2.2K_0402_5%
R74
1
2 @
2.2K_0402_5%
R75
1
2 @
2.2K_0402_5%
R76
1
2 @
2.2K_0402_5%
R77
1
2 @
2.2K_0402_5%
R78
1
2 @
2.2K_0402_5%
R79 R80 R81
1 1 1
2 @ 1K_0402_5% 2 @ 1K_0402_5% 2 @ 1K_0402_5%
10U_0805_6.3V6M +3VS
C116 0.47U_0603_10V7K
U3F
+VCCP
<7> <7> <7>
1
CFG18 CFG19 CFG20
B
2
Place near pin BA15
CALISTOGA_FCBGA1466~D
A
A
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Document Number
Calistoga (5/6)
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
11
of
47
5
4
3
2
U3I AC41 AA41 W41 T41 P41 M41 J41 F41 AV40 AP40 AN40 AK40 AJ40 AH40 AG40 AF40 AE40 B40 AY39 AW39 AV39 AR39 AN39 AJ39 AC39 AB39 AA39 Y39 W39 V39 T39 R39 P39 N39 M39 L39 J39 H39 G39 F39 D39 AT38 AM38 AH38 AG38 AF38 AE38 C38 AK37 AH37 AB37 AA37 Y37 W37 V37 T37 R37 P37 N37 M37 L37 J37 H37 G37 F37 D37 AY36 AW36 AN36 AH36 AG36 AF36 AE36 AC36 C36 B36 BA35 AV35 AR35 AH35 AB35 AA35 Y35 W35 V35 T35 R35 P35 N35 M35 L35 J35 H35 G35 F35 D35 AN34 AK34 AG34 AF34
D
C
B
VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99
1
U3J
P O W E R
VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199
AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23 AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21
AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11 J11 D11 B11 AV10 AP10 AL10 AJ10
VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS265 VSS264 VSS263 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279
P O W E R
VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS292 VSS291 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS326 VSS327 VSS328 VSS329 VSS330 VSS331 VSS332 VSS333 VSS334 VSS335 VSS336 VSS337 VSS338 VSS339 VSS340 VSS341 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352 VSS353 VSS354 VSS355 VSS356 VSS357 VSS358 VSS359 VSS360
AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1
D
C
B
CALISTOGA_FCBGA1466~D
CALISTOGA_FCBGA1466~D
A
A
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Document Number
Calistoga (6/6)
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
12
of
47
5
4
3
2
1
+1.8V
+1.8V V_DDR_MCH_REF
<8> DDR_A_DQS#[0..7]
DDR_A_D8 DDR_A_D14
Layout Note: Place near JP34
DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11
+1.8V
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
DDR_A_D21 DDR_A_D17
2
1
C129
C128
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C127
2
0.1U_0402_16V4Z
2
1
C126
C125
2
1
0.1U_0402_16V4Z
C124
2
1
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
C123
2
2.2U_0805_16V4Z
2
1
C122
C121
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D22 DDR_A_D19
2
DDR_A_D25 DDR_A_D24 DDR_A_DM3 DDR_A_D27 DDR_A_D30
C
<7> DDR_CKE0_DIMMA <8> DDR_A_BS#2
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V
DDR_CKE0_DIMMA DDR_A_BS#2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1
<8> DDR_A_BS#0 <8> DDR_A_WE#
+0.9V
<8> DDR_A_CAS# <7> DDR_CS1_DIMMA#
2
1
2
M_ODT1
DDR_A_CAS# DDR_CS1_DIMMA# M_ODT1
1
DDR_A_D35 DDR_A_D32
2
DDR_A_DQS#4 DDR_A_DQS4
C142
C141
C140
C139
C138
C137
C136
C135
C134
C133
C132
C131
C130
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
<7>
DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#
DDR_A_D38 DDR_A_D33 DDR_A_D45 DDR_A_D41
B
DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D52 DDR_A_D53 +0.9V DDR_A_MA5 DDR_A_MA8
RP1
RP2 1 2
RP3
4 3
4 3
56_0404_4P2R_5% RP4 1 4 4 2 3 3
56_0404_4P2R_5% 1 DDR_A_MA7 2 DDR_A_MA6
56_0404_4P2R_5% RP6 DDR_A_RAS# 1 4 4 DDR_CS0_DIMMA# 2 3 3
56_0404_4P2R_5% 1 DDR_A_MA9 2 DDR_A_MA12
DDR_A_MA1 DDR_A_MA3 RP5
DDR_A_BS#0 DDR_A_MA10
A
DDR_A_CAS# DDR_A_WE#
RP7 1 2
56_0404_4P2R_5% RP8 4 4 3 3
1 2
56_0404_4P2R_5% RP10 56_0404_4P2R_5% 4 4 1 DDR_A_MA0 3 3 2 DDR_A_BS#1
RP9
Layout Note: Place these resistor closely JP34,all trace length Max=1.5"
56_0404_4P2R_5% 1 DDR_A_BS#2 2 DDR_CKE0_DIMMA
DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D51 DDR_A_D55 DDR_A_D56 DDR_A_D61 DDR_A_DM7 DDR_A_D58 DDR_A_D59
56_0404_4P2R_5% 1 DDR_A_MA4 2 DDR_A_MA2
<4,14,15,20,25> ICH_SMBDATA <4,14,15,20,25> ICH_SMBCLK
+3VS C143
RP11 56_0404_4P2R_5% RP12 56_0404_4P2R_5% DDR_CS1_DIMMA# 2 3 4 1 M_ODT0 M_ODT1 1 4 3 2 DDR_A_MA13 56_0404_4P2R_5% 4 3
ICH_SMBDATA ICH_SMBCLK
0.1U_0402_16V4Z
1
2
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD
VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
FOX_ASOA426-M4R-TR CONN@
SO-DIMM A REVERSE
DDR_A_DM0 DDR_A_D5 DDR_A_D6
1
2
1
<7,14>
2
D
DDR_A_D12 DDR_A_D13 DDR_A_DM1 M_CLK_DDR0 M_CLK_DDR#0
M_CLK_DDR0 <7> M_CLK_DDR#0 <7>
DDR_A_D9 DDR_A_D15
DDR_A_D20 DDR_A_D16 DDR_THERM#
DDR_A_DM2
<7,14>
DDR_A_D18 DDR_A_D23 DDR_A_D29 DDR_A_D28 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D26 DDR_A_D31 DDR_CKE1_DIMMA
DDR_CKE1_DIMMA
C
<7>
DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 DDR_A_MA13
DDR_A_BS#1 <8> DDR_A_RAS# <8> DDR_CS0_DIMMA# <7> M_ODT0
<7>
DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D39 DDR_A_D34 DDR_A_D40 DDR_A_D44
B
DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D47 DDR_A_D46 DDR_A_D48 DDR_A_D49 M_CLK_DDR1 M_CLK_DDR#1
M_CLK_DDR1 <7> M_CLK_DDR#1 <7>
DDR_A_DM6 DDR_A_D50 DDR_A_D54 DDR_A_D60 DDR_A_D57 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63
A
BOT side
RP13 56_0404_4P2R_5% 1 DDR_CKE1_DIMMA 2 DDR_A_MA11
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
V_DDR_MCH_REF
R83 10K_0402_5% 2 1
D
DDR_A_D7 DDR_A_D1
R82 10K_0402_5% 2 1
DDR_A_D2 DDR_A_D3
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
C120
DDR_A_DQS#0 DDR_A_DQS0
<8> DDR_A_MA[0..13]
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS
C119
DDR_A_D0 DDR_A_D4
<8> DDR_A_DQS[0..7]
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
0.1U_0402_16V4Z
<8> DDR_A_DM[0..7]
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2.2U_0805_16V4Z
JP4
<8> DDR_A_D[0..63]
4
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2
Title Size Date:
Compal Electronics, Inc. DDRII-SODIMM SLOT1
Document Number
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
13
of
47
5
4
3
2
1
+1.8V
<8> DDR_B_DQS#[0..7]
+1.8V
<8> DDR_B_D[0..63]
V_DDR_MCH_REF
<8> DDR_B_DM[0..7]
DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11
+1.8V
2
DDR_B_DQS#2 DDR_B_DQS2
2
DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_DM3 DDR_B_D30 DDR_B_D31
C
<7> DDR_CKE2_DIMMB
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V
<8> DDR_B_BS#2
DDR_CKE2_DIMMB DDR_B_BS#2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
+0.9V
2
1
2
<8> DDR_B_CAS# <7> DDR_CS3_DIMMB# 1
<7>
M_ODT3
DDR_B_MA10 DDR_B_BS#0 DDR_B_WE# DDR_B_CAS# DDR_CS3_DIMMB# M_ODT3 DDR_B_D37 DDR_B_D36
2 C167
C166
C165
C164
C163
C162
C161
C160
C159
C158
C157
C156
C155
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
<8> DDR_B_BS#0 <8> DDR_B_WE#
DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D35 DDR_B_D34
B
DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D47
+0.9V DDR_B_MA1 DDR_B_MA3
RP14 1 2
DDR_B_BS#0 DDR_B_MA10
RP16 56_0404_4P2R_5% RP17 56_0404_4P2R_5% DDR_CKE3_DIMMB 1 4 4 1 DDR_B_MA11 2 3 3 2
DDR_B_MA0 DDR_B_BS#1
RP18 56_0404_4P2R_5% RP19 56_0404_4P2R_5% DDR_B_MA5 1 4 4 1 DDR_B_MA8 2 3 3 2
4 3
RP15 56_0404_4P2R_5% DDR_B_MA9 4 1 DDR_B_MA12 3 2
DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D51 DDR_B_D50 DDR_B_D60 DDR_B_D61 DDR_B_DM7 DDR_B_D58 DDR_B_D59
RP20 56_0404_4P2R_5% RP21 56_0404_4P2R_5% DDR_B_RAS# DDR_B_MA7 1 4 4 1 DDR_CS2_DIMMB# 2 DDR_B_MA6 3 3 2
<4,13,15,20,25> ICH_SMBDATA <4,13,15,20,25> ICH_SMBCLK
RP22 56_0404_4P2R_5% RP23 56_0404_4P2R_5% DDR_B_MA4 1 4 4 1 DDR_B_MA2 2 3 3 2 RP24 56_0404_4P2R_5% RP25 56_0404_4P2R_5% DDR_CS3_DIMMB# 2 M_ODT2 3 4 1 M_ODT3 DDR_B_MA13 1 4 3 2
ICH_SMBDATA ICH_SMBCLK +3VS
DDR_B_CAS# DDR_B_WE#
56_0404_4P2R_5%
C168 0.1U_0402_16V4Z
1 2
2
FOX_ASOA426-M2RN-7F
CONN@
SO-DIMM B STANDARD
DDR_B_BS#2 DDR_CKE2_DIMMB
DDR_B_DM1 M_CLK_DDR3 M_CLK_DDR#3
M_CLK_DDR3 <7> M_CLK_DDR#3 <7>
DDR_B_D14 DDR_B_D15
DDR_B_D16 DDR_B_D17 DDR_THERM#
DDR_B_DM2
<7,13>
DDR_B_D18 DDR_B_D19 DDR_B_D26 DDR_B_D28 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D29 DDR_B_D27
C
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB
<7>
DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS#1 DDR_B_RAS# DDR_CS2_DIMMB#
DDR_B_BS#1 <8> DDR_B_RAS# <8> DDR_CS2_DIMMB# <7>
M_ODT2 DDR_B_MA13
M_ODT2
<7>
DDR_B_D33 DDR_B_D32 DDR_B_DM4 DDR_B_D38 DDR_B_D39 DDR_B_D44 DDR_B_D45
B
DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D43 DDR_B_D46 DDR_B_D49 DDR_B_D52 M_CLK_DDR2 M_CLK_DDR#2
M_CLK_DDR2 <7> M_CLK_DDR#2 <7>
DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 R84 1
2
+3VS
10K_0402_5%
Compal Secret Data
Security Classification
56_0404_4P2R_5%
2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
2
A
Bottom side
RP26 4 3
1
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204
VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1 GND
2
1
D
R85
A
DDR_B_D48 DDR_B_D53
Layout Note: Place these resistor closely JP10,all trace length Max=1.5"
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND
1
DDR_B_D12 DDR_B_D13
10K_0402_5%
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203
DDR_B_D21 DDR_B_D20
1
C154
C153
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C152
2
0.1U_0402_16V4Z
2
1
C151
C150
2
1
0.1U_0402_16V4Z
C149
2
1
2.2U_0805_16V4Z
C148
2.2U_0805_16V4Z
2
2.2U_0805_16V4Z
C147
2.2U_0805_16V4Z
C146
2.2U_0805_16V4Z
2
1
DDR_B_D6 DDR_B_D2
1
DDR_B_D8 DDR_B_D9
DDR_B_DM0
2
Layout Note: Place near JP34
1
<7,13>
C145
DDR_B_D7 DDR_B_D3
DDR_B_D4 DDR_B_D1
C144
DDR_B_DQS#0 DDR_B_DQS0 D
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS
0.1U_0402_16V4Z
DDR_B_D0 DDR_B_D5
<8> DDR_B_MA[0..13]
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
2.2U_0805_16V4Z
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
<8> DDR_B_DQS[0..7]
1
V_DDR_MCH_REF
JP5
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. DDRII-SODIMM SLOT2
Document Number
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
14
of
47
5
4
3
2
1
+CK_VDD_MAIN1
FSLA
CLKSEL1
CLKSEL0
CPU MHz
SRC MHz
PCI MHz
0
0
1
133
100
33.3
0
1
1
166
100
33.3
+3VS
2 0_0805_5%
1
2
1 R87
2 0_0805_5%
1
FSB Frequency Selet: CPU Driven
*(Default) 533MHz
667MHz
2
Stuff
CLK_Ra
CLK_Rb
CLK_Rc
No Stuff
CLK_Rd
CLK_Re
CLK_Rf
Stuff
CLK_Rd
CLK_Re
CLK_Rf
No Stuff
CLK_Ra
CLK_Rb
CLK_Rc
Stuff
CLK_Rd
No Stuff
CLK_Ra
CLK_Rb
CLK_Rc
1 R103 0_0402_5%
@ 0.1U_0402_16V4Z
MCH_CLKSEL0
1
10U_0805_10V4Z
41
1
CK_VDD_REF
2 1
CLK_Re
R122
2
R88 1 2 1_0805_1%
CK_VDD_REF
1
CK_VDD_48
C179 2 R89 2.2_0805_1%
0.1U_0402_16V4Z
FSB
15
2 R104
B
<4,13,14,20,25>
+VCCP
59
CLKIREF 910_0402_1%
46
8 9
1 R117
0.1U_0402_16V4Z
2
VDD
X1
VDD48
X2
VDDPCI SATACLKT VDDSRC SATACLKC
PCI_MINI
1 R2209 PCI_CLK3 PCI_EC 1 33_0402_5% PCI_CBS 1 33_0402_5% PCI_LPC 1 33_0402_5%
VDDSRC
CPUCLKT0
VDDCPU
CPUCLKC0
VDDREF FSLA/USB_48MHz
7 60 62 1 2 3 6
CPUCLKC1
FSLC/TEST_SEL/REF1 LCDCLK_SST/SRCCLKT0 IREF
54
ICH_SMBCLK
53
LCDCLK_SSC/SRCCLKC0 PCI/SRC_STOP#
SRCCLKT2
Vtt_PwrGd#/PD
SRCCLKC2
**SEL_LCDCLK#/PCICLK_F1 REF0/PCICLK1
CPU_BSEL2
1 R133 0_0402_5%
1
R130 1K_0402_5%
2
MCH_CLKSEL2
<7> CLK_MCH_REF# <7>
CLK_MCH_REF
24_0402_5% 2
1R127
MCH_REF
CLK_MCH_REF#
24_0402_5% 2
1R131
MCH_REF# 14
SATA1/SRCCLKC4
*SEL_PCI1/PCICLK3
*CLKREQB#
**SEL_SATA1/PCICLK4
SRCCLKT1
**SEL_SATA2/PCICLK5
SRCCLKC1
PCICLK6
CLK_Rc
@ R136
NOXDP@ : means just build when XDP function disable.
1
+3VS
XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work. Pin44/45 function select
+3VS 1
SRCCLKC3 SCLK
SATA2/SRCCLKT5
C180
2
C185
2
C1456
2
C1457
2
Place close to U4
D
C186 2
1 33P_0402_50V8J
Y1 14.31818MHZ_16P
57
CLK_XTAL_IN
56
CLK_XTAL_OUT
C187 2
Routing the trace at least 10mil
1 33P_0402_50V8J
28
R92
1
2
LP@ 0_0402_5%
29
R94
1
2
LP@ 0_0402_5%
12/25
52
CPU_BCLK
51
CPU_BCLK#
49
MCH_BCLK
48
MCH_BCLK#
1 R98 1 R102
CLK_CPU_BCLK 2 24_0402_5% CLK_CPU_BCLK# 2 24_0402_5%
1 R95 1 R96
CLK_MCH_BCLK 2 24_0402_5% CLK_MCH_BCLK# 2 24_0402_5%
CLK_CPU_BCLK
<4>
CLK_CPU_BCLK# CLK_MCH_BCLK
Place near U4 Place these components near each pin within 40 mils.
<4> <7>
CLK_MCH_BCLK#
<7>
64 18
PAD
T32
SSCDREFCLK
MCH_SSCDREFCLK 24_0402_5% MCH_SSCDREFCLK# 2 24_0402_5%
1 R106 SSCDREFCLK# 1 R108
2
30
PCIE_SATA
2
31
PCIE_SATA#
19
MCH_SSCDREFCLK MCH_SSCDREFCLK#
<7>
CLKREQD#
1
CLKREQC#
1
R147
@ 10K_0402_5%
@ 10K_0402_5%
DOTC_96MHz
*CPUCLKT2_ITP/CLKREQC#
SRCCLKC6
<7>
22 23
63
1 R113 1 R115
CLK_PCIE_SATA 24_0402_5% CLK_PCIE_SATA# 24_0402_5%
2
12/25 CLK_PCIE_SATA
<19>
CLK_PCIE_SATA#
<19>
PAD
T33
20 21 26 27 35 34
45 37 36
GND GND
SRCCLKT8
GND
B
SRCCLKC8
GNDCPU
*CPUCLKC2_ITP/CLKREQD#
GNDSRC
SRCCLKT7
GNDSRC
SRCCLKC7
PCIE_ICH
1 R123 1 R124
CLK_PCIE_ICH 2 CLK_PCIE_ICH <20> 24_0402_5% PCIE_ICH# CLK_PCIE_ICH# 2 CLK_PCIE_ICH# <20> 24_0402_5% R126 1 NOXDP@ 10K_0402_5% 2 +3VS NOXDP@ CLKREQC# 2 R128 1 CLKREQC# <7> CPU_XDP CLK_CPU_XDP 0_0402_5% 1 2 CLK_CPU_XDP <4> R1133 XDP@ 24_0402_5% MCH_3GPLL CLK_MCH_3GPLL 1 2 CLK_MCH_3GPLL <7> R134 24_0402_5% MCH_3GPLL#
1 R135
2
CLK_MCH_3GPLL# 24_0402_5%
CLK_MCH_3GPLL#
<7>
43 42
GND 44 39 38
12/25
R2226 1 NOXDP@ 10K_0402_5% 2 +3VS NOXDP@ 0_0402_5% CLKREQD# 2 R2227 1 CLKREQD# <25> CPU_XDP# CLK_CPU_XDP# 1 2 CLK_CPU_XDP# <4> R2206 XDP@ 24_0402_5% PCIE_MCARD 1 CLK_PCIE_MCARD 2 CLK_PCIE_MCARD <25> R140 24_0402_5% PCIE_MCARD# 1 CLK_PCIE_MCARD# 2 CLK_PCIE_MCARD# <25> R141 24_0402_5%
GNDSATA
A
ICS9LP306_TSSOP64 * Internal Pull-Up Resistor ** Internal Pull-Down Resistor
High:Pin44/45 = CLKREQ
4
Compal Secret Data
Security Classification 2006/10/26
Issued Date
*Low:Pin44/45 = CPUCLK2_ITP
C
2 C191 @ 1000P_0402_50V4Z 2 C1461 @ 1000P_0402_50V4Z
1
1 R146
= 100MHz *High:Pin18/19 Low:Pin18/19 = 96MHz 5
PCI_MINI
2
0.1U_0402_16V4Z
DOTT_96MHz
2
J1 NO SHORT PADS
2
1 2
300_0402_5%
2
10K_0402_5%
2
2
R144
10K_0402_5% PCI_ICH
25
32
R143
R145
58
40
1
CLK_ENABLE#
17
+3VS
2
A
12
47
LCD(Low)/SRC(High) clock select
R142 @ 10K_0402_5%
4
1
2
0_0402_5%
CLK_Rf
13
2
C176
SDATA
SRCCLKT6
1
<5>
<7> CLK_MCH_REF
2
C175
1 CLK_48M_ICH @ 5P_0402_50V8C 1 CLK_14M_ICH @ 4.7P_0402_50V8C 1 CLK_PCI_ICH @ 4.7P_0402_50V8C 1 CLK_14M_KBC @ 4.7P_0402_50V8C 1 CLK_PCI_EC @ 4.7P_0402_50V8C 1 CLK_DEBUG_PORT @ 5P_0402_50V8C 1 CLK_33M_LPC @ 4.7P_0402_50V8C 1 CLK_33M_CBS @ 4.7P_0402_50V8C
*REQ_SEL/PCICLK2
SATA2/SRCCLKC5
1K_0402_5% 1
2
C1469
CPU_STOP#
SRCCLKT3
ICH_SMBDATA
2
C174
FSLB/TEST_MODE
R125 R129 8.2K_0402_5% CLKREF1 2 1
Place crystal within 500 mils of CK410
C169
VDDSATA
SATA1/SRCCLKT4
1 CLKREF0 33_0402_5%
2 R114
2
2
ICH_SMBCLK
PCI_ICH
0.1U_0402_16V4Z
1
C184
*CLKREQA#
61
CLK_14M_KBC
ICH_SMBDATA
<4,13,14,20,25>
1 CLKREF1 33_0402_5%
2 R111 1 33_0402_5%
2
1
C183
CPUCLKT1 11
CLK_DEBUG_PORT 2 DEBUG@ 33_0402_5% 10K_0402_5% 2 2 <30> CLK_PCI_EC R119 CLK_33M_CBS2 <24> CLK_33M_CBS R121 CLK_33M_LPC2 <31> CLK_33M_LPC R2171 1@ 10K_0402_5% PCI_EC
+3VS
50
R101 33_0402_5% 2 1 FSA
CLK_PCI_ICH
<30> CLK_14M_KBC
@ R120 0_0402_5%
C173 0.01U_0402_16V7K
2
U4
10
CLK_ENABLE#
2 1
+CK_VDD_MAIN1
33
MCH_CLKSEL1 <7> <25> CLK_DEBUG_PORT
R116 1K_0402_5%
2
0.1U_0402_16V4Z
H_STP_CPU# H_STP_PCI#
<18> CLK_PCI_ICH
1K_0402_5%
2
1
24
2
CLK_14M_ICH
<40> CLK_ENABLE# R112
CLK_Rb
2
1
CLK_48M_ICH
<20> H_STP_CPU# <20> H_STP_PCI#
2
2
C182
5
Must fine tune12/08
+VCCP
1 R118 0_0402_5%
1
C181
R107
1
0.1U_0402_16V4Z
55
<20> CLK_14M_ICH R105
FSB
2
1
C178
2
R100 1K_0402_5%
2
2
2
0.1U_0402_16V4Z
<20> CLK_48M_ICH
<7>
1K_0402_5%
CPU_BSEL1
10U_0805_10V4Z
CLK_Rd
CLK_Ra
<5>
C177
1
0.1U_0402_16V4Z 2 R93 1 CLKIREF @ 0_0402_5% C189
2 CPU_BSEL0
1
C188
+CK_VDD_DP
1
<5>
1
+CK_VDD_DP
CLK_Rf
2
1 C172 0.01U_0402_16V7K
12/05 ICS recommend
2 0_0805_5%
2
C190
1
2
16
@ R97 56_0402_5% R99 8.2K_0402_5% 2 1
1 C171 0.01U_0402_16V7K
+CK_VDD_DP R90 1
+3VS
+VCCP
FSA
10U_0805_10V4Z
CK_VDD_48
CLK_Re
C
1
C170
+CK_VDD_MAIN2 +3VS
Table : ICS954306 D
1 R86
1
FSLB
CLKSEL2
2
FSLC
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Document Number
Clock generator
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
15
of
47
A
B
C
D
CRT CONNECTOR
E
D7
1
D6
1
D5
1
+2.5VS
1
1
@
@
3
2
3
2
3
2
DAN217_SC59 DAN217_SC59 DAN217_SC59
CRT_VCC
12/26
@ JP6
<9>
CRT_RED
<9>
CRT_GRN
<9>
CRT_BLU
CRT_RED
L4 1
2 BK2125LL121_0805
CRTL_R
CRT_GRN
L5 1
2 BK2125LL121_0805
SMBDAT CRTL_G
L6 1
2 BK2125LL121_0805
1 1 C195 C196 C197 R148 R149 R150 75_0402_1% 75_0402_1% 75_0402_1% 2 2 2
A
10P_0402_50V8J
10P_0402_50V8J
R151
2
1
0_0402_5%
74AHCT1G125GW_SOT353-5 R152
2
1
0_0402_5%
Y
4
3 1 C201 0.1U_0402_16V4Z
P
VSYNC
1
C199
2
C200 SMBCLK
2
10P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J L7 1 2 FBMA-L11-160808-800LMT_0603
16 17
SUYIN_070912FR015S207CR CRT_HSYNCRFL
L8 1 2 FBMA-L11-160808-800LMT_0603
CRT_VSYNCRFL 2
2
A
D8
2
3
2
3
1
U6 Y
C202
1
1
2
10P_0402_50V8J 2
C203
D9 10P_0402_50V8J
4
@ DAN217_SC59 1
@ DAN217_SC59
+5VS
+3VS R_CRT_VCC F1 1
1
RB411D_SOT23
0119 HSYNC
VSYNC refernece +5VS
2
3
1A_6VDC_MINISMDC110 1
C205 0.1U_0402_16V4Z
1
D10 2
3
CRT_VCC
R153
R154
R155 2.2K_0402_5%
2
R156
4.7K_0402_5% Q3 2N7002_SOT23
4.7K_0402_5%
SMBDAT
1
SMBCLK
3
CRT_SMBCLK
CRT_SMBDAT
<9>
CRT_SMBCLK
<9>
2 G
S
3
D
1
CRT_SMBDAT
2 G
Q4 2N7002_SOT23
2.2K_0402_5% 2
+5VS
C1482 close to U6, C1483 close to JP6
1
2
2
2
S
1
D
1
C1483 0.1U_0402_16V4Z
C1482 0.1U_0402_16V4Z
+5VS
74AHCT1G125GW_SOT353-5
1
3
G
VSYNC
2
1
+5VS
5 <9>
C198
2
OE#
2
1
2
2
1
5 P 2
U5
OE#
HSYNC
HSYNC
2
1
G
<9>
CRTL_B
1
1
1
CRT_BLU +5VS
6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
1 C206 220P_0402_25V8K
2
C207
1
2
220P_0402_25V8K
+3VS 4
4
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
www.vinafix.vn C
D
Title Size Date:
Compal Electronics, Inc. CRT Connector
Document Number
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet E
16
of
47
5
4
LVDS CONN
3
2
1
+LCDVDD
C208
1
1
2
2
LCD/PANEL BD. CONN. C209
+LCDVDD +LCDVDD
0.1U_0402_16V4Z
+3VS
+5VALW 1
1
3
D
S
0.1U_0402_16V4Z
2
LVDS connector
1
Q6 2N7002_SOT23
D
1
D JP7
Q5 SI2301BDS_SOT23
R158 47K_0402_5%
2 G
D
2
R157 100_0402_5%
2 G
LVDSBC+ LVDSBCLVDSB0+ LVDSB0-
<9> <9>
LVDSB1+ LVDSB1-
<9> <9>
LVDSB2+ LVDSB2-
LVDSB0+ LVDSB0LVDSB1+ LVDSB1LVDSB2+ LVDSB2-
LVDSAC+ LVDSACINVTPWM DISPLAYOFF# DAC_BRIG LCD_CLK LCD_DAT
ACES_88107-4000G CONN@
+3VS
LVDSA0+ <9> LVDSA0- <9>
R2247 100K_0402_5%
2 G 2N7002LT1G_SOT23 2
1 LVDSAC+ <9> LVDSAC- <9>
R2189 1.8K_0603_1% DAC_BRIG
LCD_CLK LCD_DAT
<9> <9>
1
D C212
3
47K_0402_5%
2
LVDSA1+ <9> LVDSA1- <9>
2
2
0.047U_0402_16V7K
S
C211 C210 4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
C213 0.1U_0402_16V4Z
12/28 R2190 1K_0402_1%
@ R160 1
<30> INV_PWM
11/21
@
2 +3VS
0_0402_5%
C
U7
P
<9> <9>
LVDSBC+ LVDSBC-
LVDSA0+ LVDSA0-
Q7
R159 1
<9> ENAVDD
5
C216
C215 2
680P_0402_50V7K
1
680P_0402_50V7K 2 1
1 2 C
680P_0402_50V7K
C214
<9> <9>
LVDSA1+ LVDSA1-
LVDSA2+ <9> LVDSA2- <9>
1
+3VS
LVDSA2+ LVDSA2-
1
+LCDVDD
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
2
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 1 C217 680P_0402_50V7K 2 1 C218 680P_0402_50V7K
INVPWR_B+
1
3
S
2
BKLT_CTL
A
Y
4
2 R162
3
G
<9>
INVTPWM
1 @ 100K_0402_5%
@ NC7SZ14M5X_SOT23-5
R161 1 B+
INVPWR_B+ L9
1
2 0_0402_5%
2 0_0805_5%
@ L10 1 2 FBMA-L11-201209-221LMA30T_0805
2
+3VS
1
R163 3.3K_0402_5% @ R166 <9,30>
1
ENABLT
DISPLAYOFF#
2
DISPLAYOFF#
<30>
0_0402_5% +3VS B
2
B
Y 3
A
4
G
1 <30,32> LID_SW#
U29 @
P
5
B
TC7SH08FU_SSOP5
A
A
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Document Number
LCD CONN.
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
17
of
47
5
4
3
2
1
D
D
+3VS
2 8.2K_0402_5%
PCI_PLOCK#
R172 1
2 8.2K_0402_5%
PCI_IRDY#
R173 1
2 8.2K_0402_5%
PCI_SERR#
R174 1
2 8.2K_0402_5%
PCI_PERR#
R175 1
2 8.2K_0402_5%
PCI_REQ4#
R176 1
2 8.2K_0402_5%
PCI_REQ3#
R2228 1
2 8.2K_0402_5%
ICH_GPIO48
<24> PCI_AD[0..31]
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
Change to RP before SI phase +3VS R178 1
2 8.2K_0402_5%
PCI_PIRQA#
R179 1
2 8.2K_0402_5%
PCI_PIRQB#
R180 1
2 8.2K_0402_5%
PCI_PIRQC#
R181 1
2 8.2K_0402_5%
PCI_PIRQD#
R182 1
2 8.2K_0402_5%
PCI_PIRQE#
R183 1
2 8.2K_0402_5%
PCI_PIRQF#
R185 1
2 8.2K_0402_5%
PCI_PIRQG#
R186 1
2 8.2K_0402_5%
PCI_PIRQH#
R187 1
2 8.2K_0402_5%
PCI_REQ0#
R188 1
2 8.2K_0402_5%
PCI_REQ1#
R189 1
2 8.2K_0402_5%
PCI_REQ2#
R190 1
2 8.2K_0402_5%
PCI_REQ5#
<24> PCI_PIRQC#
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
+3VS
U8B E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10 E9 D9 B9 A8 A6 C7 B6 E6 D6
A3 B4 C5 B5 AE5 AD5 AG4 AH4 AD9
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# REQ4# / GPIO22 GNT4# / GPIO48 GPIO1 / REQ5# GPIO17 / GNT5#
PCI
C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME#
Interrupt
PIRQA# PIRQB# PIRQC# PIRQD#
RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5]
I/F
GPIO2 / PIRQE# GPIO3 / PIRQF# GPIO4 / PIRQG# GPIO5 / PIRQH#
MISC
RSVD[6] RSVD[7] RSVD[8] RSVD[9] MCH_SYNC#
D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8
PCI_REQ0#
B15 C12 D12 C15
PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3
A7 E10 B18 A12 C9 E11 B10 F15 F14 F16
PCI_IRDY# PCI_PAR PCI_PCIRST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#
C26 A9 B19
PCI_PLTRST# CLK_PCI_ICH
G8 F7 F8 G7
PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
5
PCI_FRAME#
R171 1
PCI_REQ1# PCI_PCIRST# PCI_REQ2# PCI_GNT2# PCI_REQ3#
PCI_REQ2# PCI_GNT2#
2
PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3
Y A
R177 0_0402_5% 1
PCI_PLTRST#
1
PCI_IRDY# <24> PCI_PAR <24>
B
4
PCI_RST#
PCI_RST#
<24>
TC7SH08FU_SSOP5
U31 @ Y
2
PCI_DEVSEL# <24> PCI_PERR# <24> PCI_SERR# <24,30> PCI_STOP# <24> PCI_TRDY# <24> PCI_FRAME# <24>
MCH_ICH_SYNC#
U30 @
+3VS
<24> <24> <24> <24>
CLK_PCI_ICH
B
2
PCI_REQ4# ICH_GPIO48 PCI_REQ5# GNT5#
AE9 AG8 AH8 F21 AH20
1
<24> <24>
P
2 8.2K_0402_5%
G
PCI_TRDY#
R170 1
3
2 8.2K_0402_5%
5
PCI_STOP#
R169 1
P
PCI_DEVSEL#
2 8.2K_0402_5%
A
2
4
PLT_RST#
PLT_RST# <7,20,22,24,25,30,31>
C
G
2 8.2K_0402_5%
R168 1
TC7SH08FU_SSOP5
3
C
R167 1
R184 0_0402_5% 1
<15>
<7>
ICH7_BGA652~D
1
B
B
Place closely pin A9
2
CLK_PCI_ICH R191
1
@ 10_0402_5%
GNT5# and GNT4# have internal pull high 20K
Boot BIOS destination
2
1
@ 8.2P_0402_50V
GNT4#
0
1
SPI@ (Default)
1
0
PCI@
1
1
LPC@
R1290 1K_0402_5% 2
GNT5#
1
C219
GNT5#
A
A
The pad must be placed on PCB easily contact space for BIOS team setting. Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Document Number
ICH7-M(1/4)
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
18
of
47
5
4
3
2
1
C220 ICH_RTCX1
2 15P_0402_50V8J 4
3
1
1
R192
Y2
+3VS +3VALW
JOPEN1 1 2
INTVRMEN INTRUDER#
CS SK DI DO
EEP_CS EEP_SK EEP_DOUT EEP_DIN
W1 Y1 Y2 W3
1
<23> LAN_RXD0 <23> LAN_RXD1 <23> LAN_RXD2
0.1U_0402_16V4Z 2
<23> LAN_TXD0 <23> LAN_TXD1 <23> LAN_TXD2
12/26
EMI
2 1
12/26
U5 V4 T5
LAN_TXD0 LAN_TXD1 LAN_TXD2
U7 V6 V7
1
R2213
+3VS
2
AC97RST# R5 T2 T3 T1
AC97_SDOUT 33_0402_5% 1 10K_0402_5%
2
U1 R6
AF18 AF3 AE3 AG2 AH2 AF7 AE7 AG6 AH6
+3VS CLK_PCIE_SATA# CLK_PCIE_SATA
<15> CLK_PCIE_SATA# <15> CLK_PCIE_SATA 1 R207 1 R208
2 2
PD_IORDY PD_IRQ
R209 1
2
AF1 AE1 AH10 AG10
EE_CS EE_SHCLK EE_DOUT EE_DIN LAN_CLK
LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2
+RTCVCC
1
1
B
R210
R211
FERR#
ACZ_BCLK ACZ_SYNC ACZ_RST# ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2
IGNNE# INIT3_3V# INIT# INTR
PD_IORDY PD_IRQ PD_DACK# PD_IOW# PD_IOR#
PD_IORDY PD_IRQ PD_DACK# PD_IOW# PD_IOR#
332K_0402_1%
AG16 AH16 AF16 AH15 AF15
RCIN# SMI# NMI STPCLK#
THERMTRIP#
ACZ_SDOUT
DA0 DA1 DA2
SATALED# SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP
DCS1# DCS3#
SATA_CLKN SATA_CLKP SATARBIASN SATARBIASP
IORDY IDEIRQ DDACK# DIOW# DIOR#
IDE
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 DDREQ
<25,30,31>
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
AA6 AB5 AC4 Y6
D
LPCRQ0# Delete(For SIO Request pin) 11/20
AC3 AA5
T15
PAD LPC_FRAME#
AB3
LPC_FRAME#
GATEA20 H_A20M#
AG27
H_CPUSLP_R#
AF24 AH25
DPRSLP# DPSLP#
AG26
H_FERR#
AG24
H_PWRGOOD
AG22 AG21 AF22 AF25
H_IGNNE#
AG23
KB_RST#
AF23 AH24
H_SMI# H_NMI
GATEA20 H_A20M#
1 0_0402_5% 1 0_0402_5% 1 56_0402_5% H_FERR#
H_IGNNE# H_INIT# H_INTR R200 2
PD_CS#1 PD_CS#3
AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15
PD_D0 PD_D1 PD_D2 PD_D3 PD_D4 PD_D5 PD_D6 PD_D7 PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15
AE15
PD_DREQ
H_DPRSTP# <4,40> H_DPSLP# <4> +VCCP
<4>
<4> <4> <4>
FWH_INIT# Delete 11/20 +3VS +VCCP
1 10K_0402_5% KB_RST#
<30>
H_SMI# H_NMI
<4> <4>
2 1 H_STPCLK# R203 0_0402_5% THRMTRIP_ICH# AF26
AE16 AD16
+3VS
<4>
H_PWRGOOD
AH22
PD_A0 PD_A1 PD_A2
10K_0402_5%
<30> <4>
T16
PAD
R196 2 R197 2 R198 2
H_INIT# H_INTR
AH17 AE17 AF17
<25,30,31>
1 R195
2
AE22 AH28
R202
H_STPCLK#
<4>
R204
56_0402_5%
1 2 24.9_0402_1%
C
PD_A0 PD_A1 PD_A2
<22> <22> <22>
PD_CS#1 PD_CS#3
<22> <22>
PD_DREQ
<22>
H_THERMTRIP#
<4,7>
Place close to ICH7
B
ICH7_BGA652~D
2
@ 332K_0402_1% 2
<22> <22> <22> <22> <22>
CPUSLP#
GPIO49 / CPUPWRGD LAN_TXD0 LAN_TXD1 LAN_TXD2
24.9_0402_1% +3VALW
A20GATE A20M#
TP1 / DPRSTP# TP2 / DPSLP#
SATA
SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C
<22> SATA_RXN0_C <22> SATA_RXP0_C <22> SATA_TXN0_C <22> SATA_TXP0_C
T4
LFRAME#
AC-97/AZALIA
1 R205
<26> ACZ_SDOUT C224 10P_0402_25V8K @
LAN_RXD0 LAN_RXD1 LAN_RXD2
AC97_SDIN0
<26> ACZ_SDIN0
1
U3
33_0402_5% 2 R201
<26> ACZ_RST# R199 10_0402_5% @
V3
LAN_RSTSYNC
R2210 33_0402_5% 1 2 AC97_SYNC
AC97_BITCLK
<26> ACZ_BITCLK <26> ACZ_SYNC
AC97_BITCLK
LAN_JCLK
LAD0 LAD1 LAD2 LAD3
LDRQ0# LDRQ1# / GPIO23
CPU
1
1 C223
VCC NC NC GND
1 2 3 4
AT93C46-10SI-2.7_SO8 <23> LAN_JCLK @ R2231 <23> LAN_RSTSYNC 0_0402_5%
2
2
R2230
8 7 6 5
0_0402_5%
4.7K_0402_5% 8.2K_0402_5%
RTCRST#
LAN
C222 1U_0603_10V4Z 1 2
2
LPC_AD[0..3]
U10
SHORT PADS
C
AA3
ICH_INTVRMEN W4 SM_INTRUDER# Y5
1 2 1M_0402_5%
+RTCVCC
ICH_RTCRST#
RTXC1 RTCX2
1
R194
AB1 AB2
2
2
ICH_RTCX2
LPC
C221 2 15P_0402_50V8J
RTC
R193 1 20K_0402_5%
+RTCVCC
U8A
2
32.768KHZ_12.5P_MC-146 1
D
1
2
10M_0402_5%
Change to LAN power plane 12/11
PD_D[0..15]
PD_D[0..15]
<22>
1
ICH_INTVRMEN R212
2
@ 0_0402_5%
LAN_TXD0 LAN_TXD1 LAN_TXD2
+3VL 33_0402_5%
R2197 2
1 1
1 C1449
2
33P_0402_50V8J
2 1R2196 2
JP8
2
C225
+
D11
R213
1 33P_0402_50V8J
C1448
2
1 33P_0402_50V8J
A
C1447
1
33_0402_5%
33_0402_5%
1
R2195
2
+RTCVCC
3 2
1
-
RTC_R 1 2 1 W=20mils + R214 DAN202U_SC70 1K_0402_5% 2
100_0402_5%
1U_0603_10V4Z
-
2 BATT1
A
SUYIN_060003FA002TX00NL~D
CR2032 RTC BATTERY PCB_MB_rev10
11/21
BATT@
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
ZZZ1
W=20mils
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Document Number
ICH7-M(2/4)
Rev 1.0
LA-3491P
Thursday, April 12, 2007
Sheet 1
19
of
47
5
4
3
2
1
Place closely pin B2
2
1
<7> PM_BMBUSY#
ICH_SMB_CLK
D
S 3
1
2
G
<4,30,42>
A28
SB_SPKR LPC_PD# XDP_DBRESET#
A19 A27 A22
2
OCP#
<15> H_STP_PCI# <15> H_STP_CPU#
+3VS
PM_BMBUSY# OCP#
10K_0402_5% R234 1 2 SIRQ
R231 1K_0402_5% 1 2
+3VALW
<24,30> PM_CLKRUN#
<24,30> SIRQ <4> THERM_SCI#
12/05 Change to +3VS <30> RUNSCI_EC#
+3VALW
T18 T19
PM_CLKRUN#
GPIO18 / STPPCI# GPIO20 / STPCPU# GPIO26
B21 E23
GPIO27 GPIO28
AG18
PWROK_ICH7
AD22
RUNSCI_EC#
AC21 AC18 E21
GPIO21 / SATA0GP GPIO19 / SATA1GP GPIO36 / SATA2GP GPIO37 / SATA3GP
CLK14 CLK48 SUSCLK SLP_S3# SLP_S4# SLP_S5#
GPIO11 / SMBALERT#
AC20 AF21
GPIO32 / CLKRUN#
PWROK GPIO16 / DPRSLPVR TP0 / BATLOW# PWRBTN# LAN_RST# RSMRST#
AF19 AH18 AH19 AE19
AC1 B2
VRMPWRGD
GPIO
GPIO6 GPIO7 GPIO8
GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 GPIO24 GPIO25 GPIO35 / SATAREQ# GPIO38 GPIO39
1 R223 CLK_14M_ICH CLK_48M_ICH
<7,30>
PM_POK
R239
1
2
0_0402_5%
R240
1
2 @ 0_0402_5%
ICH_SUSCLK SLP_S3# SLP_S4# SLP_S5#
AA4
PM_POK
AC22
DPRSLPVR
C21
ICH_LOW_BAT#
C23
ON/OFFBTN#
C19
LAN_RST_R#
PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2
WLAN@ 0.1U_0402_16V4Z 2 WLAN@ 0.1U_0402_16V4Z 2
1 C228 1 C229
PCIE_RXN2 PCIE_RXP2 PCIE_C_TXN2 PCIE_C_TXP2
PERn1 PERp1 PETn1 PETp1
H26 H25 G28 G27
PERn2 PERp2 PETn2 PETp2 PERn3 PERp3 PETn3 PETp3
M26 M25 L28 L27
B
PERn4 PERp4 PETn4 PETp4
P26 P25 N28 N27
R246 should be placed less than 100 mils from U8
SPI_SI SPI_SO
SPI_SI SPI_SO
47_0402_5% 2
R2219 1
47_0402_5% 2
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7
+3VALW
A
R246 1
1 R249
2SPI_CS# 10K_0402_5%
1 R250
2 SPI_SI 10K_0402_5%
1 R251
2 SPI_SO 10K_0402_5%
T25 T24 R28 R27
PERn6 PERp6 PETn6 PETp6
R2 P6 P1
SPI_CLK SPI_CS# SPI_ARB
P5 P2
SPI_MOSI SPI_MISO
D3 C4 D5 D4 E5 C3 A2 B3
OC0# OC1# OC2# OC3# OC4# OC5# / GPIO29 OC6# / GPIO30 OC7# / GPIO31
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DMI_CLKN DMI_CLKP
DMI_ZCOMP DMI_IRCOMP
SPI
<31> <31>
SPI_CLK SPI_CS#
PERn5 PERp5 PETn5 PETp5
PCI-EXPRESS
K26 K25 J28 J27
SPI_CLK SPI_CS#
1 2 @ 4.7P_0402_50V8C
2
C227
D
@ 4.7P_0402_50V8C
<15> <15>
SLP_S3# SLP_S4# SLP_S5#
<30,33,39> <38> <33,38> R227 2 10K_0402_5%
1 DPRSLPVR
<7,40>
ON/OFFBTN#
<32>
PM_RSMRST#
<24,30>
<30>
1
R229 10K_0402_5% 2 1
1 R2232
2 0_0402_5%
1 R2233
2 @ 0_0402_5%
T21 PAD XMIT_OFF# <25,31>
XMIT_OFF#
LOW_BAT# <30>
CH751H-40_SC76
LAN_RST_R#
LID_OUT#
+3VALW
D12 2
T20 PAD LID_OUT#
R228 8.2K_0402_5% 2 1
+3VL
PLT_RST# <7,18,22,24,25,30,31> C
LAN_RST# <30>
12/26
T22 PAD
U8D
12/26
<31> <31>
C226
T17 PAD
PM_RSMRST# R233 10K_0402_5% 1 2
E20 A20 F19 E19 R4 E22 R3 D20 AD21 AD20 AE20
1
PWROK_ICH7
F26 F25 E28 E27 <25> <25> <25> <25>
CLK_14M_ICH CLK_48M_ICH
B24 D23 F22
Y4
2
2 100_0402_5%
C20
GPIO33 / AZ_DOCK_EN# GPIO34 / AZ_DOCK_RST# WAKE# SERIRQ THRM#
1
ICH7_BGA652~D <7,40> VGATE_INTEL
@ 10_0402_5%
2
GPIO0 / BM_BUSY#
ICH_PCIE_WAKE# F20 SIRQ AH21 THERM_SCI# AF20
10K_0402_5% R237 1 2 LINKALERT#
10K_0402_5% R241 1 2 OCP#
AB18
AC19 U2
<25> ICH_PCIE_WAKE#
10K_0402_5% R242 1 2 LID_OUT#
SPKR SUS_STAT# SYS_RST#
B23
H_STP_PCI# H_STP_CPU#
PAD PAD
8.2K_0402_5% R235 1 2 PM_CLKRUN#
RI#
A21
@ 10K_0402_5% R230 1 2 THERM_SCI#
10K_0402_5% R238 1 2 XDP_DBRESET#
SATA GPIO
ICH_RI#
SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1
GPIO
G
Q11 RHU002N06_SOT323
+3VS
C
C22 B22 A26 B25 A25
SYS
<26> SB_SPKR <30> LPC_PD# <4> XDP_DBRESET# ICH_SMB_DATA
D
3
ICH_SMBCLK
ICH_SMBCLK
ICH_SMB_CLK ICH_SMB_DATA LINKALERT# ICH_SMLINK0 ICH_SMLINK1
DIRECT MEDIA INTERFACE
2
2.2K_0402_5% Q10 RHU002N06_SOT323 S
<4,13,14,15,25>
ICH_SMBDATA
ICH_SMBDATA
R226 1 2 8.2K_0402_5%
R225
2.2K_0402_5%
<4,13,14,15,25>
2 0_0402_5% 2 0_0402_5%
U8C
+3VALW
1
1
+3VS
4.7K_0402_5%
SMB
@ R221 1 1 @ R222
ICH_SMBCLK ICH_SMBDATA
1
1
10K_0402_5%
R216
@ 10_0402_5%
Clocks
4.7K_0402_5%
R224
R215
R220
10K_0402_5% D
R217,R218 change from 2.2Kohm to 10Kohm when Q23,Q24,R206,R204 stuffed.
R218
POWER MGT
R219
R217
CLK_14M_ICH
1
+3VALW
2
2
+3VALW
Place closely pin AC1
CLK_48M_ICH
USB
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBRBIAS# USBRBIAS
V26 V25 U28 U27
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
Y26 Y25 W28 W27
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
AB26 AB25 AA28 AA27
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
AD25 AD24 AC28 AC27
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
AE28 AE27
CLK_PCIE_ICH# CLK_PCIE_ICH
C25 D25 F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3 D2 D1
DMI_IRCOMP
R232 need be removed when ICH7M ES2 samples used, but need be stuffed when ICH7M ES1 samples used. DMI_RXN0 <7> DMI_RXP0 <7> DMI_TXN0 <7> DMI_TXP0 <7>
DPRSLPVR
2 1 R232 @ 100K_0402_5%
DMI_RXN1 <7> DMI_RXP1 <7> DMI_TXN1 <7> DMI_TXP1 <7> DMI_RXN2 <7> DMI_RXP2 <7> DMI_TXN2 <7> DMI_TXP2 <7> USB_OC#0 1 R243 USB_OC#1 1 R244
DMI_RXN3 <7> DMI_RXP3 <7> DMI_TXN3 <7> DMI_TXP3 <7>
2 @ 0_0402_5% 2 @ 0_0402_5%
USB_OC#
<29>
B
CLK_PCIE_ICH# <15> CLK_PCIE_ICH <15> R245 1
USB20_N0 USB20_P0 USB20_N1 USB20_P1
24.9_0402_1% 2
Within 500 mils +1.5VS
USB20_N0 <29> USB20_P0 <29> USB20_N1 <29> USB20_P1 <29> +3VALW
12/26 RP33 USB_OC#1 USB_OC#3 USB_OC#0 USB_OC#5
1 2 3 4
USB_OC#2 USB_OC#4 USB_OC#6 USB_OC#7
1 2 3 4
8 7 6 5
10K_1206_8P4R_5% RP34
USBRBIAS
R248 22.6_0402_1% 1 2
Within 500 mils
8 7 6 5
10K_1206_8P4R_5%
A
ICH7_BGA652~D
R249,R250 and R251 should be placed close to U8.
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Document Number
ICH7-M(3/4)
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
20
of
47
5
4
3
2
1
+VCCP U8F
ICH_V5REF_SUS
F6
0.1U_0402_16V4Z
R252
D13 CH751H-40_SC76
+
C235
2
1
C236
2
1
C237
2
0.1U_0402_16V4Z
1
2 0.1U_0402_16V4Z
1
2
100_0402_5%
1
C234 220U_D2_2VM_R9
+3VS 2
1
+5VS
AA22 AA23 AB22 AB23 AC23 AC24 AC25 AC26 AD26 AD27 AD28 D26 D27 D28 E24 E25 E26 F23 F24 G22 G23 H22 H23 J22 J23 K22 K23 L22 L23 M22 M23 N22 N23 P22 P23 R22 R23 R24 R25 R26 T22 T23 T26 T27 T28 U22 U23 V22 V23 W22 W23 Y22 Y23
ICH_V5REF_RUN 1
2
1
C238 0.1U_0402_16V4Z
2
C239
Place closely pin D28,T28,AD28.
@
0.1U_0402_16V4Z
2
1
+5VALW +3VALW
R253
D14
C
1
CH751H-40_SC76 2
10_0402_5%
1
2
ICH_V5REF_SUS C245 0.1U_0402_16V4Z
+3VS
C249 0.1U_0402_16V4Z
1
2
Place closely pin AG28 within 100mlis. +1.5VS_DMIPLLR
+1.5VS_DMIPLL
B27
R255 1
0.5_0805_1%
2 0_0805_5%
B
C259
1
2
+3VALW C263 0.1U_0402_16V4Z
2
1
AG28 AB7 AC6 AC7 AD6 AE6 AF5 AF6 AG5 AH5
+1.5VS
2
C258 0.1U_0402_16V4Z
1
2
Place closely pin AG5.
0.1U_0402_16V4Z
+1.5VS
1
+1.5VS_DMIPLL
C257 0.01U_0402_16V7K
2
AD2 AH11
+3VS 1
2
C260 0.1U_0402_16V4Z
R254 1
C256 10U_0805_10V4Z
+1.5VS
AB10 AB9 AC10 AD10 AE10 AF10 AF9 AG9 AH9
+1.5VS C262 1U_0603_10V4Z
1
2
Place closely pin AG9.
1
C1
+1.5VS C265
2
0.1U_0402_16V4Z
+3VS +3VALW
E3
1 T26 T27
PAD PAD
ICH_AA2 ICH_Y7
AA2 Y7
2
0_0402_5%
2
1
R2236 VCCLAN3_3
0_0402_5%
@2
1
R2237
V5 V1 W2 W7 1
A
12/25
2
V5REF[2] V5REF_Sus Vcc1_5_B[1] Vcc1_5_B[2] Vcc1_5_B[3] Vcc1_5_B[4] Vcc1_5_B[5] Vcc1_5_B[6] Vcc1_5_B[7] Vcc1_5_B[8] Vcc1_5_B[9] Vcc1_5_B[10] Vcc1_5_B[11] Vcc1_5_B[12] Vcc1_5_B[13] Vcc1_5_B[14] Vcc1_5_B[15] Vcc1_5_B[16] Vcc1_5_B[17] Vcc1_5_B[18] Vcc1_5_B[19] Vcc1_5_B[20] Vcc1_5_B[21] Vcc1_5_B[22] Vcc1_5_B[23] Vcc1_5_B[24] Vcc1_5_B[25] Vcc1_5_B[26] Vcc1_5_B[27] Vcc1_5_B[28] Vcc1_5_B[29] Vcc1_5_B[30] Vcc1_5_B[31] Vcc1_5_B[32] Vcc1_5_B[33] Vcc1_5_B[34] Vcc1_5_B[35] Vcc1_5_B[36] Vcc1_5_B[37] Vcc1_5_B[38] Vcc1_5_B[39] Vcc1_5_B[40] Vcc1_5_B[41] Vcc1_5_B[42] Vcc1_5_B[43] Vcc1_5_B[44] Vcc1_5_B[45] Vcc1_5_B[46] Vcc1_5_B[47] Vcc1_5_B[48] Vcc1_5_B[49] Vcc1_5_B[50] Vcc1_5_B[51] Vcc1_5_B[52] Vcc1_5_B[53]
Vcc3_3 / VccHDA VccSus3_3/VccSusHDA V_CPU_IO[1] V_CPU_IO[2] V_CPU_IO[3] Vcc3_3[3] Vcc3_3[4] Vcc3_3[5] Vcc3_3[6] Vcc3_3[7] Vcc3_3[8] Vcc3_3[9] Vcc3_3[10] Vcc3_3[11] Vcc3_3[12] Vcc3_3[13] Vcc3_3[14] Vcc3_3[15] Vcc3_3[16] Vcc3_3[17] Vcc3_3[18] Vcc3_3[19] Vcc3_3[20] Vcc3_3[21] VccRTC VccSus3_3[1] VccSus3_3[2] VccSus3_3[3] VccSus3_3[4] VccSus3_3[5] VccSus3_3[6]
Vcc3_3[1]
VccSus3_3[7] VccSus3_3[8] VccSus3_3[9] VccSus3_3[10] VccSus3_3[11] VccSus3_3[12] VccSus3_3[13] VccSus3_3[14] VccSus3_3[15] VccSus3_3[16] VccSus3_3[17] VccSus3_3[18]
VccDMIPLL Vcc1_5_A[1] Vcc1_5_A[2] Vcc1_5_A[3] Vcc1_5_A[4] Vcc1_5_A[5] Vcc1_5_A[6] Vcc1_5_A[7] Vcc1_5_A[8] Vcc1_5_A[9]
Vcc1_5_A[19] Vcc1_5_A[20]
VccSATAPLL Vcc3_3[2]
Vcc1_5_A[21] Vcc1_5_A[22] Vcc1_5_A[23]
Vcc1_5_A[10] Vcc1_5_A[11] Vcc1_5_A[12] Vcc1_5_A[13] Vcc1_5_A[14] Vcc1_5_A[15] Vcc1_5_A[16] Vcc1_5_A[17] Vcc1_5_A[18]
Vcc1_5_A[24] Vcc1_5_A[25] VccSus1_05[1] VccSus1_05[2] VccSus1_05[3]
VccSus3_3[19] VccUSBPLL VccSus1_05/VccLAN1_05[1] VccSus1_05/VccLAN1_05[2]
Vcc1_5_A[26] Vcc1_5_A[27] Vcc1_5_A[28] Vcc1_5_A[29] Vcc1_5_A[30]
1 1
C232
C233
2
1
1
+
2
2 C230
1U_0603_10V4Z
+
C231 @ 330U_D2E_2.5VM_R9
2
220U_D2_2VM_R9
12/25 VCCSUSHDA
R2234
1
2 @ 0_0402_5%
R2235
1
2
0_0402_5%
U6 1
+VCCP
VCCSUSHDA
R7
C241 1 2
AE23 AE26 AH26 AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19
2
A5 B13 B16 B7 C10 D15 F9 G11 G12 G16
1
2
1
2
+3VALW
+3VS C240 0.1U_0402_16V4Z
0.1U_0402_16V4Z 1 2
+3VS 1
2
+3VS
C242 0.1U_0402_16V4Z 1 2
C243 0.1U_0402_16V4Z
C244 4.7U_0805_10V4Z
1
2
+3VS
W5
+RTCVCC
P7 1
A24 C24 D19 D22 G19
2
K3 K4 K5 K6 L1 L2 L3 L6 L7 M6 M7 N7
1
2
1
C250 0.1U_0402_16V4Z
1
C254 0.1U_0402_16V4Z
AB17 AC17
2
2
+3VALW C251 0.1U_0402_16V4Z
1
1
2
2
C253 0.1U_0402_16V4Z
+1.5VS
0.1U_0402_16V4Z
L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
C252 0.1U_0402_16V4Z
Change 150uF to 220uF 12/04 D
Vcc1_05[1] Vcc1_05[2] Vcc1_05[3] Vcc1_05[4] Vcc1_05[5] Vcc1_05[6] Vcc1_05[7] Vcc1_05[8] Vcc1_05[9] Vcc1_05[10] Vcc1_05[11] Vcc1_05[12] Vcc1_05[13] Vcc1_05[14] Vcc1_05[15] Vcc1_05[16] Vcc1_05[17] Vcc1_05[18] Vcc1_05[19] Vcc1_05[20]
C248 0.1U_0402_16V4Z
AD17
U8E
V5REF[1]
C247 0.1U_0402_16V4Z
G10
C246 0.1U_0402_16V4Z
ICH_V5REF_RUN
+3VALW C255 0.1U_0402_16V4Z
+1.5VS
T7 F17 G17 AB8 AC8
1
2
K7
C261 0.1U_0402_16V4Z ICH_K7 PAD
T23
C28 G20
ICH_C28 ICH_G20
T24 T25
A1 H6 H7 J6 J7
PAD PAD +1.5VS 1
2
C264 0.1U_0402_16V4Z
VccSus3_3/VccLAN3_3[1] VccSus3_3/VccLAN3_3[2] VccSus3_3/VccLAN3_3[3] VccSus3_3/VccLAN3_3[4]
VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194]
P28 R1 R11 R12 R13 R14 R15 R16 R17 R18 T6 T12 T13 T14 T15 T16 T17 U4 U12 U13 U14 U15 U16 U17 U24 U25 U26 V2 V13 V15 V24 V27 V28 W6 W24 W25 W26 Y3 Y24 Y27 Y28 AA1 AA24 AA25 AA26 AB4 AB6 AB11 AB14 AB16 AB19 AB21 AB24 AB27 AB28 AC2 AC5 AC9 AC11 AD1 AD3 AD4 AD7 AD8 AD11 AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21 AE24 AE25 AF2 AF4 AF8 AF11 AF27 AF28 AG1 AG3 AG7 AG11 AG14 AG17 AG20 AG25 AH1 AH3 AH7 AH12 AH23 AH27
D
C
B
ICH7_BGA652~D
C266
A
0.1U_0402_16V4Z
Compal Secret Data 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97]
ICH7_BGA652~D
Security Classification
5
A4 A23 B1 B8 B11 B14 B17 B20 B26 B28 C2 C6 C27 D10 D13 D18 D21 D24 E1 E2 E4 E8 E15 F3 F4 F5 F12 F27 F28 G1 G2 G5 G6 G9 G14 G18 G21 G24 G25 G26 H3 H4 H5 H24 H27 H28 J1 J2 J5 J24 J25 J26 K24 K27 K28 L13 L15 L24 L25 L26 M3 M4 M5 M12 M13 M14 M15 M16 M17 M24 M27 M28 N1 N2 N5 N6 N11 N12 N13 N14 N15 N16 N17 N18 N24 N25 N26 P3 P4 P12 P13 P14 P15 P16 P17 P24 P27
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. Document Number
ICH7-M(4/4)
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
21
of
47
A
B
C
D
E
JP9 GND A+ AGND BB+ GND
SATA CONN
1
3900P_0402_50V7K SATA_TXP0 2
C268
1
V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12
Near ICH7(U26) side.
C272 SATA_RXN0_C
<19> SATA_RXN0_C
SATA_RXP0_C
<19> SATA_RXP0_C
1
3900P_0402_50V7K SATA_RXN0 2
1
3900P_0402_50V7K SATA_RXP0 2
C273
CONN@
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
+5VS 1
2
OCTEK_HDD-22SC1G_44P_RV
C269
1 C270 2
Near Device(JP45) side.
1 C271 2
1 + 2
C1450 @ 330U_D2E_2.5VM_R9
3900P_0402_50V7K SATA_TXN0 2
0.1U_0402_16V4Z
SATA_TXP0_C
<19> SATA_TXP0_C
1
SATA_RXN0 SATA_RXP0
0.1U_0402_16V4Z
C267 SATA_TXN0_C
<19> SATA_TXN0_C
SATA_TXP0 SATA_TXN0
10U_0805_10V4Z
1
1 2 3 4 5 6 7
11/21
2
2
CD-ROM Connector PD_D[0..15]
12/26 PLT_RST#
<19>
JP10 2 R256
3
2
1
PD_DACK# 1
R257 <19> 100K_0402_5% 2
+5VS
PD_A2 <19> PD_CS#3 <19>
1
2
1
2
1
2
10U_0805_10V4Z
2
PD_DREQ <19> PD_IOR# <19>
C1453
PDIAG# PD_A2 PD_CS#3
Placea caps. near ODD CONN.
C1452
PRI_CSEL
PD_DACK#
+5VS
1U_0603_10V4Z
+5VS
PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15 PD_DREQ PD_IOR#
C1451
PD_IOW# PD_IORDY PD_IRQ PD_A1 PD_A0 PD_CS#1 IDE_ACT#
<19> PD_IOW# <19> PD_IORDY <19> PD_IRQ <19> PD_A1 <19> PD_A0 <19> PD_CS#1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
0.1U_0402_16V4Z
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
1 33_0402_5% PD_D7 PD_D6 PD_D5 PD_D4 PD_D3 PD_D2 PD_D1 PD_D0
3
1
2
C1454 10U_0805_10V4Z
+5VS
11/21
C274 0.1U_0402_16V4Z
GND GND
<7,18,20,24,25,30,31>
PLT_RST#
PD_D[0..15]
53 54
OCTEK_CDR-50TA1
1
R258 470_0402_5%
+5VS
R259 IDE_ACT#
4
1
2
4
10K_0402_5%
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
www.vinafix.vn C
D
Title Size Date:
Compal Electronics, Inc. Document Number
HDD & ODD
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet E
22
of
47
4
3
2
close to U12chip(Intel rule) close to U12chip(Intel rule)
RDN
2
2 TDN
2 R260 110_0402_1%
1
LAN_RXD0 LAN_RXD1 LAN_RXD2
R262 110_0402_1%
1
D
C275
RDP
R261 @ 110_0402_1%
RDN
JP11 @ R263 300_0603_5% 1 2
2
ACTLED#
R267 300_0603_5% 1 2
+3VS
8 7 MDO1-
1
2
12 11
1
2 2
R266 33_0402_5%
33P_0402_50V8J
R265
33_0402_5%
1 C277
2
33_0402_5% 33P_0402_50V8J
R264
1 C276
2
1
1
68P_0402_50V8K
+3VALW
1
RJ45
close to U13
TDP
2
RDP
1
1
5
6
Support wake on LAN R263,R269 Don't Support wake on LAN R267 R268
C278 33P_0402_50V8J
2
+3VS
1
L11 FBMA-L11-160808-601LMT 0603
15 mil
@ R269 300_0603_5% 1 2
+3VALW
MDO1+
3
MDO0-
2
MDO0+
1
LINK_LED100#
10 9
1
Amber LED+ SHLD4 PR4-
SHLD3
16 15
PR4+ PR2PR3PR3+ PR2+ PR1-
SHLD2
PR1+ SHLD1
Green LED-
14 13
Green LED+ SUYIN_100073FR012S100ZL CONN@
C281
2 1 @ L20 FBMA-L11-160808-601LMT 0603
+3VALW
4
R268 300_0603_5% 1 2
+3VS
+3VLAN
5
D
Amber LED-
2 68P_0402_50V8K
+3VLAN
C
C
+3VLAN
2
12/28
2
2
2
B
1 R277
2 200_0402_5%
28 30 29 21 41
JTXD2 JTXD1 JTXD0 JCLK TOUT RBIAS100 RBIAS10
1
LAN_RXD2 LAN_RXD1 LAN_RXD0 LAN_RSTSYNC
45 44 43 39
LAN_TXD2 LAN_TXD1 LAN_TXD0 LANJCLK
LAN_RXD2 <19> LAN_RXD1 <19> LAN_RXD0 <19> LAN_RSTSYNC <19> LAN_TXD2 <19> LAN_TXD1 <19> LAN_TXD0 <19> 1 47_0402_5%
2 R270
1
37 35 34 42
ACTLED# LINK_LED100#
2
2 0_0603_5% 2 0_0603_5%
8 7 6
LAN_JCLK
@
LAN_JCLK
3 2 1
RDN RDP
1
2
0.1U_0402_16V4Z C284
VSS VSS VSS VSS VSS VSSP VSSP VSSA VSSA2 VSSR VSSR
U13 TDN TDP
TDTD+ CT
TXTX+ CT
9 10 11
MDO0MDO0+ MCT0
14 15 16
MCT1 MDO1MDO1+
R272 75_0402_5% 2 1
C282 RJ45_GND
2
1
1000P_1206_2KV7K R2208 1 R2207 1
C1458
JRXD2 JRXD1 JRXD0 JRSTSYNC
VCCR VCCR
31 32 27
0.1U_0402_16V4Z C283
8 13 18 24 48 33 38 3 6 20 22
1
SPDLED# ACTLED# LILED#
C1459 680P_0402_50V7K
1
10U_0805_6.3V4Z C1478
1
19 23
+3V_LAN
0.1U_0402_16V4Z C1477
0.1U_0402_16V4Z C1476
2
R2254 0_0603_5%
TDP TDN RDP RDN
680P_0402_50V7K 1 2
2
VCC VCC VCCP VCCP VCCA VCCA2 VCCT VCCT VCCT VCCT
TDP TDN RDP RDN
1
CT RDRD+
CT RXRX+
2 1 R273 75_0402_5%
NS0013_16P
2
<19>
26 5
R274
1
2 649_0402_1%
4
R275
1
2 619_0402_1%
B
02/07 Follow 82562GT design guide
ISOL_TI ISOL_TCK ISOL_EXEC TESTEN
X1
46
LAN1_XO
1 2
2
1
R271 @ 0_0402_5%
10 11 15 16
C279 2
JP12
22P_0402_50V8J
TIP RING
1 2
Y3 25MHZ_20P_1BG25000CK1A
ADV10
X2
47 LAN1_XI
82562GT_SSOP48
1
2
1
0.1U_0402_16V4Z C1475
2
1
0.1U_0402_16V4Z C1474
2
1
0.1U_0402_16V4Z C1473
2
1
0.1U_0402_16V4Z C1471
10U_0805_6.3V4Z C1470
1
+3VLAN
1
0.1U_0402_16V4Z C1472
U12
1 25 36 40 2 7 9 12 14 17
1
C280 1 2
C293 470P_1808_3KV
2
1
C294 470P_1808_3KV
3 4
RJ11
1 2 GND1 GND2
FOX_JM74613-P2002-7F~D CONN@
2
22P_0402_50V8J
8/18 for EMI
JP13 RING TIP A
@
Compal Secret Data
Security Classification Issued Date
2006/10/26
2006/07/26
Deciphered Date
Title
4
www.vinafix.vn 3
A
Compal Electronics, Inc. 82562EZ LAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
1 2 ACES_85205-0200 CONN@
RJ11 CABLE
Date:
2
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
23
of
47
A
B
C
D
E
S1_VCC
1
U14
6/02
9
VCC VCC VCC
12V
13 12 11
2
C295 4.7U_0805_10V4Z S1_VPP
S1_VCC
1
12/05 Follow IAT00 EMI Request
<18> <18> <18> <18>
PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0
<18> PCI_RST# <18> PCI_FRAME# <18> PCI_IRDY# <18> PCI_TRDY# <18> PCI_DEVSEL# <18> PCI_STOP# <18> PCI_PERR# <18,30> PCI_SERR# <18> PCI_PAR <18> PCI_REQ2# <18> PCI_GNT2# <15> CLK_33M_CBS
3
+3V_CB
Change to DAU00 PCI Devices ID
PCI_AD22
Cardbus ---->AD22
<20,30>
CLK_33M_CBS
20 28 29 31 32 33 34 35 36 1 2 21
SIRQ
2
PLT_RST#
1
4
2
<20,30> PM_RSMRST#
C309@
PLT_RST#
1 R287
2 0_0402_5%
PM_RSMRST# 1 @ R2250
2 0_0402_5%
+3VS
2
C306
59 70 43K_0402_5% 2 13 100_0402_5% 60 61 64 65 67 68 69 66
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 C/BE3# C/BE2# C/BE1# C/BE0#
2
63
2
+5VALW
2
+5VS
1 C307
2
@ L22
2
C308 0.1U_0402_16V7K
0_0805_5%
VCCI
138 122 102 86 50 30 14 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7
126 90 VCCSK0 VCCSK1
44 18
10U_1206_16V4Z
1
L13
CAD31/D10 CAD30/D9 CAD29/D1 CAD28/D8 CAD27/D0 CAD26/A0 CAD25/A1 CAD24/A2 CAD23/A3 CAD22/A4 CAD21/A5 CAD20/A6 CAD19/A25 CAD18/A7 CAD17/A24 CAD16/A17 CAD15/IOWR# CAD14/A9 CAD13/IORD# CAD12/A11 CAD11/OE# CAD10/CE2# CAD9/A10 CAD8/D15 CAD7/D7 CAD6/D13 CAD5/D6 CAD4/D12 CAD3/D5 CAD2/D11 CAD1/D4 CAD0/D3 CC/BE3#/REG# CC/BE2#/A12 CC/BE1#/A8 CC/BE0#/CE1#
RST# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR REQ# GNT# PCLK
CRST#/RESET CFRAME#/A23 CIRDY#/A15 CTRDY#/A22 CDEVSEL#/A21 CSTOP#/A20 CPERR#/A14 CSERR#/WAIT# CPAR/A13 CREQ#/INPACK# CGNT#/WE# CCLK/A16
RI_OUT#/PME# SUSPEND#
CSTSCHG/BVD1 CCLKRUN#/WP
IDSEL
CBLOCK#/A19
MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6
CINT#/READY
VCC/GRST#
1
+5V_CB
1
PQFP 144 22.2 X 22.2 X 1.60
S1_VCC
SPKOUT CAUDIO/BVD2 CCD2#/CD2# CCD1#/CD1# CVS2/VS2# CVS1/VS1#
144 142 141 140 139 129 128 127 124 121 120 118 116 115 113 98 96 97 93 95 92 91 89 87 85 82 83 80 81 77 79 76
S1_D10 S1_D9 S1_D1 S1_D8 S1_D0 S1_A0 S1_A1 S1_A2 S1_A3 S1_A4 S1_A5 S1_A6 S1_A25 S1_A7 S1_A24 S1_A17 S1_IOWR# S1_A9 S1_IORD# S1_A11 S1_OE# S1_CE2# S1_A10 S1_D15 S1_D7 S1_D13 S1_D6 S1_D12 S1_D5 S1_D11 S1_D4 S1_D3
125 112 99 88
S1_REG# S1_A12 S1_A8 S1_CE1#
119 111 110 109 107 105 104 133 101 123 106 108 135 136
S1_RST S1_A23 S1_A15 S1_A22 S1_A21 S1_A20 S1_A14 S1_WAIT# S1_A13 S1_INPACK# S1_WE# 1 2 R282 33_0402_5% S1_BVD1 S1_WP
103
S1_A19
132
S1_RDY#
62 134
S1_BVD2
137 75 117 131
S1_CD2# S1_CD1# S1_VS2 S1_VS1
S1_VCC
0_0805_5%
S1_A23 2 22K_0402 S1_WP 2 22K_0402
1 R279 1 R280
12/27
2
S1_VCC
1
12 27 37 48
<20,30> PM_CLKRUN# <7,18,20,22,25,30,31>
U15
PCI_CBE3# PCI_CBE2# PCI_CBE1# PCI_CBE0#
1
CLK_33M_CBS
2
2
Don't Support wake on LAN L12, L13 Support wake on LAN L?, L?
680P_0402_50V7K
3 4 5 7 8 9 10 11 15 16 17 19 23 24 25 26 38 39 40 41 43 45 46 47 49 51 52 53 54 55 56 57
R283 1 R284
+3VALW
0_0805_5%
1
PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0
<18> PCI_PIRQC#
R285 10_0402_5% @
1
RSVD/D14 RSVD/A18 RSVD/D2
2
2
C300 0.1U_0402_16V4Z
L12
2 0.1U_0402_16V7K
84 100 143
C1468 0.047U_0402_16V4Z
C1467 0.047U_0402_16V4Z
C1466 0.01U_0402_16V7K
C1465 0.01U_0402_16V7K
C1464 0.01U_0402_16V7K
C1463 0.01U_0402_16V7K
+5VALW +5VALW +5VALW +5VALW +5VALW +5VALW
2
1
1
1 C299 4.7U_1206_25VFZ
0_0805_5%
VCCP0 VCCP1
7
16
2
1
2
PCI_AD[0..31]
<18> PCI_AD[0..31]
@ L21
C304
VPPD0 VPPD1 VCCD0# VCCD1#
CP-2211_SSOP16
1
C298 0.1U_0402_16V7K
+3V_CB
8
2
R278 10K_0603_1%
OC
2
+3V_CB
1
72 71
2
1
C305 0.1U_0402_16V7K
3.3V 3.3V
1
VPPD1 VPPD0
1
GND
3 4
SHDN
+3V_CB
VCCD0# VCCD1# VPPD0 VPPD1
1 2 15 14
C297
2
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8
VCCD0 VCCD1 VPPD0 VPPD1
C296 0.1U_0402_16V7K
1
R281 47K_0402_5%
2
2
74 73
6/02
5V 5V
+3V_CB
VCCD1# VCCD0#
2
5 6
0.1U_0402_16V7K 1
6 22 42 58 78 94 114 130
VPP
1 C301 0.1U_0402_16V7K
1
10
C302 680P_0402_50V7K 2 1
1
C303 4.7U_0805_10V4Z
S1_VPP +5V_CB
JP14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 69 71 73 75 77 79 81 83
S1_D3 S1_D4 S1_D5 S1_D6 S1_D7 S1_CE1# S1_A10 S1_OE# S1_A11 S1_A9 S1_A8 S1_A13 S1_A14 S1_WE# S1_RDY# S1_VCC S1_VPP
S1_A16
S1_A16 S1_A15 S1_A12 S1_A7 S1_A6 S1_A5 S1_A4 S1_A3 S1_A2 S1_A1 S1_A0 S1_D0 S1_D1 S1_D2 S1_WP
CBS_SPK# <26>
GND GND S1_D3 S1_CD1# S1_D4 S1_D11 S1_D5 S1_D12 S1_D6 S1_D13 S1_D7 S1_D14 S1_CE1# S1_D15 S1_A10 S1_CE2# S1_OE# S1_VS1 S1_A11 S1_IORD# S1_A9 S1_IOWR# S1_A8 S1_A17 S1_A13 S1_A18 S1_A14 S1_A19 S1_WE# S1_A20 S1_RDY# S1_A21 S1_VCC S1_VCC S1_VPP S1_VPP S1_A16 S1_A22 S1_A15 S1_A23 S1_A12 S1_A24 S1_A7 S1_A25 S1_A6 S1_VS2 S1_A5 S1_RST S1_A4 S1_WAIT# S1_A3 S1_INPACK# S1_A2 S1_REG# S1_A1 S1_BVD2 S1_A0 S1_BVD1 S1_D0 S1_D8 S1_D1 S1_D9 S1_D2 S1_D10 S1_WP S1_CD2# GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 70 72 74 76 78 80 82 84
S1_CD1# S1_D11 S1_D12 S1_D13 S1_D14 S1_D15 S1_CE2# S1_VS1 S1_IORD# S1_IOWR# S1_A17 S1_A18 S1_A19 S1_A20 S1_A21 S1_A22 S1_A23 S1_A24 S1_A25 S1_VS2 S1_RST S1_WAIT# S1_INPACK# S1_REG# S1_BVD2 S1_BVD1 S1_D8 S1_D9 S1_D10 S1_CD2#
S1_VCC S1_VPP 3
FOX_WZ21131-G2-P4_LT CONN@
CB1410_LQFP144
2
15P_0402_50V8J
S1_D2 S1_A18 S1_D14
2 C310
1
1
C311 1000P_0402_50V7K
4
1000P_0402_50V7K
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
A
B
www.vinafix.vn C
Date:
D
CardBus CTRL CB714
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev 1.0
LA-3491P Monday, April 02, 2007
Sheet E
24
of
47
A
B
C
D
E
1
1
+3VS
2
C313 WLAN@ 4.7U_0805_10V4Z
1
2
C314 WLAN@ 0.01U_0402_16V7K
1
2
C315 WLAN@ 0.1U_0402_16V4Z
1
2
Mini-Express Card---WLAN ICH_PCIE_WAKE#
<15>
CLKREQD#
<15> CLK_PCIE_MCARD# <15> CLK_PCIE_MCARD <15> CLK_DEBUG_PORT <20> PCIE_RXN2 <20> PCIE_RXP2 <20> <20>
PCIE_TXN2 PCIE_TXP2
12/26 +3VL <30,31,32> STB_LED# <30,31> NUM_LED# <30,31> CAPS_LED#
1 3 5 WLAN@ R288 1 2 CLKREQD#_MC 7 0_0402_5% 9 CLK_PCIE_MCARD# 11 CLK_PCIE_MCARD 13 15 PLT_RST# 1 2 17 R294 DEBUG@ 0_0402_5% 19 R295 0_0402_5% 21 PCIE_RXN2 1 2 WLAN@ PCIE_C_RXN2 23 PCIE_RXP2 PCIE_C_RXP2 1 2 25 R297 0_0402_5% 27 WLAN@ 29 PCIE_TXN2 31 PCIE_TXP2 33 35 37 39 41 43 R299 1 2 DEBUG@ 0_0402_5% 45 R300 1 2 DEBUG@ 0_0402_5% 47 R301 1 2 DEBUG@ 0_0402_5% 49 R302 1 2 DEBUG@ 0_0402_5% 51 53
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
GND1 GND2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
1
2
+3V_MINI
+3VS
2
L14 1 2 FBMA-L11-201209-102LMA10T WLAN@ R289 R290 R291 R292 R293
1 1 1 1 1
2 2 2 2 2
LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
LPC_FRAME#
<19,30,31>
LPC_AD[0..3]
XMIT_OFF#
<19,30,31> XMIT_OFF# <20,31> PLT_RST# <7,18,20,22,24,30,31>
+3VALW
12/26
ICH_SMBCLK <4,13,14,15,20> ICH_SMBDATA <4,13,14,15,20> R2270 2 1WLAN@ 10K_0402_5% @ R2263 1 2 0_0402_5% R2271 1 2 0_0402_5% WLAN@
+3VS WL_LED# <31,32> WL_LED_EC# <30>
Mini Card STANDOFF 02/26 Add R2270 for WL_LED_EC# PU
54
02/26 Add R2271 for use EC detect WLAN active
MOLEX 67910-0002 52P CONN@
3
C317 WLAN@ 0.1U_0402_16V4Z
2
DEBUG@ 0_0402_5% DEBUG@ 0_0402_5% DEBUG@ 0_0402_5% DEBUG@ 0_0402_5% DEBUG@ 0_0402_5%
JP15
12/25
1
+1.5VS
2
<20> ICH_PCIE_WAKE#
C316 WLAN@ 4.7U_0805_10V4Z
H27 HOLEA
H28 HOLEA
1
1
+3VALW
1
C312 WLAN@ 0.1U_0402_16V4Z
+1.5VS
3
4
4
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
www.vinafix.vn C
D
Title Size Date:
Compal Electronics, Inc. Mini-Card
Document Number
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet E
25
of
47
A
B
C
D
E
CODEC POWER +VDDA_CODEC
3
11/30 Change to
VIN
OUT
R307
5 1
GND SHDN#
BP
1
U16
2 1 0.1U_0402_16V4Z 2
4
APE8805A-33Y5P_SOT23-5 C320 0.1U_0402_16V4Z +5VS
1
2
1
10K_0402_1%
C319
C321
0.1U_0402_16V4Z
2
1U_0603_10V4Z
R308
2
10K_0402_1% C326
2
AUDIO CODEC
MONO_IN
1
1U_0402_6.3V6K
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
2 B
C
Q15
E
2SC2411K_SOT23
10K_0402_5%
1
2
C1479
2
C325 1U_0402_6.3V6K
2 B
1
1
2
560_0402_5%
C
Q43
E
2SC2411K_SOT23
3
C324
2 0_0603_5%
R311
1
R2256
2 MONO_IN1 2 1 MONO_INR 20K_0402_5% @ R310 1U_0603_10V4Z 1 2
2/09 Fine tune PC Beep, Delete R310
1K_0402_5% 1
1
C323
+VDDA_CODEC
1
1 0.1U_0402_16V4Z 2
1
08/ 10 L16 1 2
AVDD_20549
2
CBS_SPK# @C328 0.1U_0402_16V4Z
DVDD_20549
08/ 10 2 0_0603_5% 2 C322
1 L15
C327 <24>
3
In order for the modem wake on ring feature to function, the CODEC must be powered by a rail that is not removed when the system is in standby.
R309
1
1U_0603_10V4Z
+3VS
1
1
1 C318
1
+VDDA_CODEC
2
+5VS
2
2
R316
<27>
DIB_P
2 R318
<27>
DIB_N
2 R319
33_0402_5%
1 DIBP_C 0_0402_5%
44
1 DIBN_C 0_0402_5%
43
MONO_INR
11
48
20 31 37
8 45
BIT_CLK SYNC SDI SDO
LINEOUT_L LINEOUT_R PORT-A_BIAS_L PORT-A_BIAS_R PORT-A_L PORT-A_R
DIBP DIBN
PORT-B_BIAS_L PORT-B_BIAS_R PORT-B_L PORT-B_R
PCBEEP
CD_L CD_GND CD_R
SPDIF
ACZ_BITCLK
DVDD_20549
1 C334 @ 100P_0402_25V8K
RCOSC 1 237K_0402_1%
41
NC_1 NC_2 NC_16 RCOSC
42 46
2
2 R327
2
1 2 16
SENSE
LINEOUT_L LINEOUT_R
LINE_OUTL <28> LINE_OUTR <28>
33 34 38 39
PORT_A_L PORT_A_R
HP_L HP_R
VREF_HI VREF_LO VC_REFA
1
1
R317
2
560_0402_5% MIC_L MIC_R
1U_0603_10V4Z
<28> <28>
@ R320 10K_0402_5%
D15 RB751V_SOD323
<28> <28>
14 15 23 24 17 18 19 13
SENSE
2 R3212 R3221 R323
EAPD
AVSS_12 AVSS_25 AVSS_32 AVSSHP
2
@ 100P_0402_25V8K
2 47 0_0603_5%
08/ 10
R325 @ 100_0402_5%
1 L17
12 25 32 40
1
DVSS
EAPD# C332
6
EAPD#
1
<28,30>
VSSIO_42 VSSIO_46
3
35 36
2
SB_SPKR
1
5 9 7 4
MIC_BIAS_L MIC_BIAS_R MIC_L MIC_R
2 2.2K_0402_5% 2 2.2K_0402_5% C329 1 2 10U_0805_10V4Z C330 1 2 10U_0805_10V4Z
2
ACZ_BITCLK ACZ_SYNC ACZ_SDIN0 ACZ_SDOUT
RESET#
R314 1 R315 1 MIC_INL MIC_INR
1
<19> <19> <19> <19>
C331 <20>
29 30 21 22
2
<19> ACZ_RST#
03/20 Add CBS de-pop circuit,Change Q43 from FET to BJT
AVDD_20 AVDD_31 AVDDHP
10
DVDD DVDDM
VDDIO
U17
3
03/10 Delete CBS de-pop circuit
26 27 28
1 AVDD_20549 5.11K_0402_5% 1 HP_SENSE <28> 5.11K_0402_5% 2 MIC_SENSE <28> 20K_0402_5% For Vista
VREF_HI VREF_LO VC_REFA C335
1U_0402_6.3V6K CX20549-12Z_LQFP48_9X9
3
1 R324
2 0_0402_5%
1 R326
2 0_0402_5%
1 @ R328
2 0_0402_5%
1 @ R329
2 0_0402_5%
03/21 ESD request C333 2
1
2 1U_0402_6.3V6K
1
1 @ R330 08/ 10 R331 @ R332
DIGITAL
R333
ANALOG
R334
2 0_0402_5% 1
2 0_1206_5%
1
2 0_1206_5%
1
2 0_1206_5%
1
2 0_1206_5% GNDA
<28>
4
4
GND
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
www.vinafix.vn C
GNDA
D
Title
CODEC CX20468-31
Size Document Number Custom Date:
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet E
26
of
47
5
4
3
2
5335R13-005
RAC1_RING MU1 CX20548
MMBD3004S MBR1
RAC 12
D
4
RAC1
MR3
AGND_LSD
1
2 1
2
D
TAC1
6.81M
DIBN
EIC
EIC
MC11
2 1 @
MBR2 MMBD3004S 5335R13-005
TAC1_TIP
11
MC8 @ 470 pF MC10
PWR+
15
MC7 Omit @
0.01uF
AVdd MC5 0.1uF cap_0402_01uf MC12
MJ4
GND 150pF CAP_0402_150PF MT1 2
DIBN_HS DIBP_HS
2 1
2
AVDD
RXI
6
RXI
MC3 0.1uF cap_0402_01uf
3
MC6 47pF CAP_0402_47PF
@
AGND_LSD
MR2
RX1_1
MC1
BRIDGE_CC
0.047uF 100.0V
237K
BRIDGE_CC2 DIBP
14
DIBP
EIO
MR13
10
MC13
100
MQ1 MMBTA42
RES_0402_100
150pF CAP_0402_150PF
EIF DVdd
GND
1
DVDD
TXO
MC4 0.1uF cap_0402_01uf AGND_LSD
B
8
TXO
7
TXF
QBASE
MQ2 MMBTA42
13
MQ3 MMBTA42
MQ4 MMBTA42
MR11 3.01 res_0402_301
MR12 3.01 res_0402_301
MR7 9.1 res_1206_91
AGND_LSD
Date
0
Initial Release
April 26, 2005
1
No changes to schematic. PCB updated to -003. Updated footprints and corrected via spacing errors.
August 18, 2005
2
Changed MC8 and MC9 pads. PCB updated to -005.
3
Added MR11 and MR12.
4
Added MR13.
4.01
AVL update only.
No schematic changes.
PCB updated to -007.
PCB updated to -009.
AGND_LSD
November 3, 2005
November 18, 2005
A
January 3, 2006
Compal Secret Data
Security Classification April 20, 2006
Issued Date
2006/10/26
Deciphered Date
2006/07/26
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
B
MC2 0.1uF cap_0402_01uf
Revision History Description
@ MR8 56 5% RES_0603_56
MR4 110 5%
VC_LSD
GND
EIF
17
3
@
GPIO
9
EP
1 2
TXF
VC
MJ5
C
MR9 MR5 MR6 MR10 280 280 280 280 RES_1206_280RES_1206_280 RES_1206_280 RES_1206_280
AGND_LSD
1 4 MODEM-SMAR
A
MJ3
Note: MC8 and MC9 can be optionally populated here or behind the RJ-11 connector. GND
DIB_P DIB_N
C
REV
2 1 @
MC9 @ 470 pF
cap_0603_001uf
R810 and C810 must be placed near pin 6 (RXI) and there should be no vias on the(RXI)net.
PWR
MJ1
TIP_1
MFB1
0.1uF cap_0402_01uf AGND_LSD
<26> <26>
MJ2 CONN@
MRV1
5
MR1
4 3 @ ML1 Optional
res_0805_681m
16
RING_1
MFB2
6.81M
TEST
TAC
DIBN
1
4
3
www.vinafix.vn
2
Compal Electronics, Inc. AMOM-CX20548
Document Number
Rev 1.0
LA-3491P Monday, April 02, 2007
Sheet 1
27
of
47
C
R335 0_1206_5% 1 2
0.1U_0402_16V4Z
+5VS
C339 47P_0402_50V8J
C336 10U_0805_10V4Z
1
JP16
SPKRSPKR+
1
1
E
1
C337
C338
2
2
2 0.1U_0402_16V4Z
1
2
@
10 dB
1 2 1
2
@ SM05_SOT23
<26> LINE_OUTL
C344 1
2 0.47U_0603_16V7K
9
C345 1
2 0.47U_0603_16V7K
5
RIN-
ROUT+ ROUT-
LIN+
LOUT+
2
LIN-
LOUT-
2
GAIN1
1
GAIN0
2
LINE_C_OUTR
RIN+
1
7
C342 0.47U_0603_16V7K 1 2 17
1
2 3 18
SPKR+
14
SPKR-
@ R338 100K_0402_5%
R339 100K_0402_5% 2
<26> LINE_OUTR
2 0.47U_0603_16V7K
@ R337 100K_0402_5%
2
C341 1
R2264 1K_0402_5% 2 1 R2265 1K_0402_5% 2 1
1
1
16 15 6
R336 100K_0402_5%
VDD PVDD1 PVDD2
02/07 Change to 1K Ohm
4
MIC_SENSE
<26> MIC_SENSE
MIC IN JP17
02/14 Change to AGND
2 R2255
A_SD#
C349
1 0_0402_5%
<26>
HP_R
HP_R
1
02/07 Change to 60 Ohm 0603
HP_L
1
+
C350 HP_L
2
1
U33
0.1U_0402_16V4Z 1 @ C1484
D
S
Q45 A_SD 2 G 2N7002_SOT23
D
S
1 R344
PL
2
0_0402_5% C351 47P_0402_50V8J
C352
10 9 8 7
3 6 2 1 FOX_JA6333L-B3S0-7F~N CONN@ 08/ 09
1K_0402_5% 47P_0402_50V8J
1
CH751H-40_SC76
Q44 A_SD 2 G 2N7002_SOT23
5
R346
1K_0402_5%
1 @ D35
1
2
3
3
NC7SZ04P5X_SC70-5
2INTSPK_CL+
2 A_SD
1
Y
4
R342 2 0_0402_5%
4
R345
3
A G
2
3
JP18 1
PR
60_0603_1%
P
5
R2269 0_0402_5% 2 1
2INTSPK_CR+
R343
100U_6.3V_M +3VALW
HP OUT
R341 1
60_0603_1%
100U_6.3V_M
<26>
@ SM05_SOT23 D17
HP_SENSE
2
+
<30>
FOX_JA6333L-B3S0-7F~N CONN@ 08/ 09
2
1
09/03
<26> HP_SENSE 3
1
3
S
10 9 8 7
3 6 2 1
2
1
1 2 L19 FBM-11-160808-601-T_0603
4
2
MIC_L
1
3
MIC_L
C347 1U_0603_10V4Z
L18 FBM-11-160808-601-T_0603 1 2
21
20 13 11 1 D Q16 @
2 G 2N7002LT1G_SOT23
<26>
MIC_R
1
EAPD#
MIC_R
TPA6017A2_TSSOP20 1
<26,30>
1 0_0402_5%
3
2 @ R2198
2
<26>
C348 47P_0402_50V8J
SHUTDOWN
Keep 10 mil width
10
2
19
GND1 GND2 GND3 GND4
2 10K_0402_5%
12
5
C346 47P_0402_50V8J
1
1 R340 @
+3VALW
THERMAL PAD
NC
2
08/ 10
8 2
BYPASS
1
ACES_85205-0200 CONN@ D16
@
+5VS U18
2
+5VAMP
D
3
B
C340 47P_0402_50V8J
A
@ SM05_SOT23 D18
02/14 Change to AGND
2
02/26 add HP de-pop circuit 4
4
Compal Secret Data
Security Classification 2006/10/26
Issued Date
Deciphered Date
2006/07/26
Title
AMP and Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
www.vinafix.vn
D
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet E
28
of
47
5
14"
4
3
2
1
+USB_VCCA
USB Port 1 +
C353 100U_6.3V_M
C354
D
2
1
1
2
2
C355 1000P_0402_50V7K D
0.1U_0402_16V4Z
@ JP20
2
USB20_N1 USB20_P1 3
<20> <20>
C356 @ 10P_0402_50V8J
1
2
2
C357 @ 10P_0402_50V8J
5 6
1
D19 @ PSOT24C_SOT23
1
1 2 3 4
For ESD
+USB_VCCA
VCC DD+ GND GND1 GND2
SUYIN_020173MR004G552ZR CONN@
1 C358 100U_6.3V_M
+
C359 2
1
1
2
2
C360 1000P_0402_50V7K
0.1U_0402_16V4Z JP21
C
2
USB20_N0 USB20_P0 3
<20> <20>
C365 @ 10P_0402_50V8J
1
2
2
C366 5 @10P_0402_50V8J 6
1
D21 @ PSOT24C_SOT23
1
1 2 3 4
VCC DD+ GND
C
GND1 GND2
SUYIN_020173MR004G552ZR CONN@
+5VALW
+USB_VCCA U19 C368
0.1U_0402_16V4Z 2 1 <33,38> SLP_S5
1 2 3 4
GND IN IN EN#
OUT OUT OUT FLG
8 7 6 5
USB_OC#
<20>
G528_SO8
B
B
A
A
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. USB Connector
Document Number
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
29
of
47
5
4
3
KSI0 KSI3 KSI2 KSI1
1
0.1U_0402_16V4Z KSI7 KSI6 KSI5 KSI4
Pin3 250 : KSO12/OUT8/KBRST RP37 1 2 3 4
8 7 6 5
KSO2 KSO4 KSO7 KSO8
@ 10K_1206_8P4R_5%
Note: R94 must be removed when R1354 stuff and R87 remove.
RP38 1 2 3 4
LPCPD#
8 7 6 5
KSO14 KSO11 KSO10 KSO15 <32>
02/26 Reserve KSO PU resistor
10K_0402_5%
35 36 38 40 41 42
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 IMCLK IMDAT KCLK KDAT EMCLK EMDAT
1
CLK_PCI_EC <20,24> PM_CLKRUN# <20,24> SIRQ <15> CLK_PCI_EC <20> RUNSCI_EC#
R363
PM_CLKRUN# SIRQ CLK_PCI_EC RUNSCI_EC#
55 57 54 76
LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
51 50 48 46
LPC_FRAME# PLT_RST#
52 53 45
CLKRUN# SER_IRQ PCI_CLK EC_SCI#
Power Mgmt/SIRQ
2
@ 10_0402_5%
<19,25,31> LPC_FRAME# <7,18,20,22,24,25,31> PLT_RST#
2
@ R2266 0_0402_5%
2
+3VL
4.7U_0805_10V4Z
0_0402_5% WLAN@ 0_0402_5%
VCC0
R2239 1 R2240 1
2 2
0_0402_5% 0_0402_5%
INT_KBD CONN. INT_KBD CONN. ACES_85201-2405 CONN@
CP5 8 7 6 5
@ 100P_1206_8P4C_50V8 CP6 KSI1 1 8 KSI7 2 7 KSI6 3 6 KSO9 4 5 @ 100P_1206_8P4C_50V8
5
GPIO20/PS2CLK GPIO21/PS2DAT GPIO24/KSO16 GPIO27
AB1A_DATA AB1A_CLK
EA Strap#/GPIO26/KSO17 CLOCKI 32KHZ_OUT/GPIO22 RESET_OUT#/GPIO06 PWRGD VCC1_PWRGD 24MHZ_OUT/GPIO19/WINDMON TEST PIN DMS_LED#/GPIO10 BAT_LED# PWR_LED#/8051TX FDD_LED#/8051RX
123 122 121 120 118
LAN_RST# KBRST# INV_PWM FAN_PWM CHGCTRL
107 79 80 81 83
FWP# ON/OFFBTN_KBC# LOW_BAT# KSO14 KSO15
85 86 87
PM_RSMRST# EC_GPIO8 EC_GPIO9
88 89 90 91 92 101 102
BATCON
103 105 4 74
NUM_LED# SLP_S3#
D22 1
INV_PWM <17> FAN_PWM <4> CHGCTRL <36> Pin82 250 -- nFWP ON/OFFBTN_KBC# LOW_BAT# <20>
2
KB_RST#
<19>
CH751H-40_SC76
<32>
R2267 02/07 0_0402_5%
,
109 110
BATCON
EC_GPIO13
2
<36>
ENABLT
1 2 10K_0402_5% +3VL
<9,17>
ADP_PRES
1 MODE R2246 1 R362
<36,37,42> EC_GPIO13
+3VL
2 0_0402_5% 2 0_0402_5%
SMB_EC_DA1 SMB_EC_CK1
SMB_EC_DA1 SMB_EC_CK1
1 R357 2 100K_0402_5%
02/07 Delete THM_MAIN# double PU GATEA20
<19> RP32 SMB_EC_CK1 SMB_EC_DA1 AB1B_DATA AB1B_CLK
1 2 3 4
PGM R364 1
108 59 75 60 78 77 61
EA# Pin83 250 -- nEA ( pull up !! ) CLK_14M_KBC CLK_14M_KBC <15> 32K_CLK PM_POK PM_POK <7,20> PWR_GD PWR_GD <33,34,40,42> VCC1_PWRGD VCC1_PWRGD <31,34> EC_GPIO19
2 0_0402_5%
TEST Pin52 250 -- XOSEL
1 R366
MODE
KBC1070_VTQFP128
A_SD#
2 300_0402_5%
EC_WL_LED# AMBER_BATLED# STB_LED# CAPS_LED#
4.7K_1206_8P4R_5%
<41> <41>
<28> @ CLK_14M_KBC 1
Pin56 250 -- PGM Pin58 250 -- 32KHz_OUT Pin49 250 -- Reset Out
Pin91 250 -- nDMS_LED
1
2
1
@ 2 1
@ R369 1
FWP#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 JP24
PGM
JP23
2/08 Delete NUM_LED# Double PU R374 1 R376 1
+3VL
2
VCC1_PWRGD NUM_LED# STB_LED# CAPS_LED#
2 100K_0402_5% 2 100K_0402_5%
03/10 BOM delete R2273 R2274(SMSC leakage issue)
+3VL
R379
J4 1
2
1
2
NO SHORT PADS
1K_0402_5%
FWP#
2 1 @ 1K_0402_5%
R380
AGND FILTER
TEST
2. For KBC internal ROM flash: 32K_CLK Install R377,R379
2006/10/26
2006/07/26
Deciphered Date
www.vinafix.vn 3
2
A
EC_GPIO9 2 1 @ R2276 4.7K_0402_5%
1 1K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2 1 @ R2273 4.7K_0402_5% 2 1 @ R2274 4.7K_0402_5%
EC_GPIO19 2 1 @ R2275 4.7K_0402_5%
02/27 Add PD resister
Compal Secret Data
Security Classification Issued Date
2
ACES_85201-0602 CONN@
EC_GPIO8
R382 EA#
1021@ R129 R131 R78
1 2 3 4 5 6
For KBC debugging used.
Un-install R377,R379
2 1 @ 1K_0402_5%
0.1U_0402_16V4Z
250@ R127 R128 R977 R62
1. For normal operation:
R381
C384 1 2
PM_POK
2
B
@ 1K_0402_5%
ADP_EN
2 10P_0402_25V8K
+3VL
2
R377 1
C378
10K_0402_5%
R62 250@
R372
R365
10_0402_5%
EC_WL_LED# <31> AMBER_BATLED# <31> STB_LED# <25,31,32> CAPS_LED# <25,31>
@ 10K_0402_5%
0_0402_5%
8 7 6 5
AB1B_DATA AB1B_CLK
FWP#
2
C
+3VL
NUM_LED# <25,31> SLP_S3# <20,33,39> DISPLAYOFF# <17> Pin1 250 -- TEST Pin ( NC !! ) EAPD# <26,28> Pin57 250 -- MODE
73
116 113 115 114
1
CH751H-40_SC76 2 R359 1 10K_0402_5% D24 1 2 CH751H-40_SC76
LID_SW# <17,32> PCI_SERR# <18,24> THM_MAIN# <41>
PCI_SERR# THM_MAIN# A20M
Reserve VCC0 to +3VL Add R2267 to GND
@ R378 1
+3VS
R2253 LID_SW#
PM_RSMRST# <20,24> R2245 10_0402_5% 1 2
1 4
10K_0402_5%
LAN_RST# <20>
D23
111 112
69
R353
KBC_PWR_ON <37> GREEN_BATLED# <31> 2
KBC_PWR_ON GREEN_BATLED#
D
ACES_85201-0602 CONN@
+3VL
2
15
49
119
93 98 99 100 126 GPIO11/AB2A_DATA GPIO12/AB2A_CLK GPIO13/AB2B_DATA GPIO14/AB2B_CLK GPIO15/FAN_TACH1 GPIO16/FAN_TACH2 GPIO17/A20M
124 125
1 2 3 4 5 6
EC_GPIO9 EC_GPIO8
@ 1K_0402_5%
32K_CLK KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1
JP22 VCC1_PWRGD
WL_BTN# <31,32> OCP# <4,20,42> WL_LED_EC# <25> 4C#_6C8C <42> LID_OUT# <20>
R375
1
03/19 Reserve VCC0 to +RTCVCC
@ 100P_1206_8P4C_50V8
1 2 3 4
C377
2 2
1
32.768KHZ_12.5P_Q13MC30610018
8 7 6 5
@ 100P_1206_8P4C_50V8 CP4 1 8 2 7 3 6 4 5
KSI4 KSI5 KSO0 KSI2
2
R2238 1 R2268 1
PGM @ C382 1U_0603_10V4Z
CP3
XTAL1 XTAL2
NC NC NC NC NC NC NC NC NC NC
2
2
LPC Bus
GPIO07/PWM3 GPIO08/RXD GPIO09/TXD
PGM Strap/GPIO25
VSS VSS VSS VSS VSS VSS VSS
68
18P_0402_50V8J C381
LFRAME# LRESET# LPCPD#/GPIO23
GPIO01 GPIO02 GPIO03 GPIO04/KSO14 GPIO05/KSO15
AB1B_DATA AB1B_CLK
+3VL
1
1
4
1 IN 2
OUT
2
1
70 71
R371 120K_0402_5% @ R2277 0_0402_5%
NC
Y4 1
NC
18P_0402_50V8J C380
KSI3 KSO5 KSO1 KSI0
A
0.1U_0402_16V4Z
R2220 10K_0402_5%
OUT7/SMI# OUT8/KBRST OUT9/PWM2 OUT10/PWM0 OUT11/PWM1
Access Bus Interface
11 37 47 56 104 82 117
+RTCVCC
R370 @ 2M_0402_5% 2
@ 100P_1206_8P4C_50V8 1 2 3 4
CRY1 CRY2
LAD[3] LAD[2] LAD[1] LAD[0]
1 2 3 30 31 32 33 34 43 44
EMI Add
LPCPD#
2 @ 0_0402_5%
2
1
8 7 6 5
@ 100P_1206_8P4C_50V8 CP2 KSO6 1 8 KSO3 2 7 KSO12 3 6 KSO13 4 5
KSO2 KSO4 KSO7 KSO8
R367 1
LPC_PD#
3
CP1 1 2 3 4
C376
2
Pin34 250 -- LPCPD#
KSO14 KSO11 KSO10 KSO15
LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
AGND
<19,25,31> <19,25,31> <19,25,31> <19,25,31>
@ 10P_0402_25V8K
72
C379
<20>
B
2
02/14 Reserve R2268 for OCP#
GPIO28 GPIO29 GPIO30 GPIO31 GPIO32
29 28 27 26 25 24 23 22
VCC2
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 TP_CLK TP_DATA KBD_CLK KBD_DATA PS2_CLK PS2_DATA
TP_CLK TP_DATA
<32> @ 10K_1206_8P4R_5%
10K_0402_5% R361 1 2 RUNSCI_EC#
1
0.1U_0402_16V4Z
1 @ 10K_1206_8P4R_5%
10K_1206_8P4R_5%
2
C375
OUT0 OUT1/IRQ8#
General Purpose I/O Interface
KSO9 KSO0 KSO5 KSO1
KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12/GPIO00/KBRST KSO13/GPIO18
Miscellaneous
+3VL
KBD_CLK KBD_DATA PS2_CLK PS2_DATA
8 7 6 5
21 20 19 18 17 16 13 12 10 9 8 7 6 5
Keyboard/Mouse Interface
1 2 3 4
KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13
VCC1
U20
RP36
RP31
2
KSO6 KSO3 KSO12 KSO13
@ 10K_1206_8P4R_5%
10K_0402_5%
R360
2
1
NC NC NC NC NC NC
TP_CLK
8 7 6 5
VCC1 VCC1 VCC1 VCC1 VCC1
1 2 3 4
10K_0402_5% R355 2 TP_DATA
8 7 6 5
0.1U_0402_16V4Z
2 C1460 10U_0805_10V4Z
2
39 58 84 106 14
RP35
1
1 2 3 4
2
C1446 0.1U_0402_16V4Z
62 63 64 65 66 67
2
2
C373 4.7U_0805_10V4Z
1
SMSC_1070_TQFP-128P
1
2
C372 0.1U_0402_16V4Z
1
C374
1
1
02/07 Delete KSI PU, 1070 had internal PU R354
2
C371 0.1U_0402_16V4Z
1
2
1
+3VL
10K_1206_8P4R_5%
+5VS
2
1
94 95 96 97 127 128
8 7 6 5
C370 0.1U_0402_16V4Z
1
NC NC NC NC NC NC
1 2 3 4
1
1
C369
RP30
+3VS
BIOS debug port Place under KB area
+3VL 8 7 6 5
10K_1206_8P4R_5%
C
1
1
RP29 1 2 3 4
D
2
+3VS
03/10 Add Keyboard scan input PU resistor
CAP
+3VL
Title Size Date:
Compal Electronics, Inc. Document Number
LPC47N1021
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet 1
30
of
47
5
4
3
2
1
BIOS ROM If use System SPI ROM, R2217 should be placed If use LPC Debug Port , R2217 should be delete, and R2216 must pull high
+3VALW
+3VALW
1
R384
0.1U_0402_16V4Z
1
<20>
SPI_CS#
<20>
SPI_CLK
<20>
SPI_SI
SPI_CS#
1
R2217 2 0_0402_5%
1
3
SPI_HOLD#
7 1
SPI_CLK
6
SPI_SI
5
VCC
VSS
4
R383 27_0402_5% WLAN14@
W 1
@
SPI_WP#
HOLD 2
2
8
R2216 1K_0402_5%
D
BLUE
U21
02/06 change XMIT_OFF#
S C D
Q
2
SPI_SO_L 1
R386 2 47_0402_5%
SPI_SO
SPI_SO
<20>
XMIT_OFF#
LED
0
1
1
0
SST25LF080A_SO8-200mil
R1291 place cloe to U66
WLAN14@ D25 S LED HT-170NBQA 0805 BLUE
1
2 SPI_WP# 3.3K_0402_5% R385 1 2 SPI_HOLD# 3.3K_0402_5%
+3VS
Wireless LED
2
2
C385
+3VALW D
WL_LED#
NUM_LED#
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
NUM_LED# SPI_CLK SPI_CS# SPI_SI SPI_SO SPI_HOLD#
Connect pin3 & 23 together and pin 24 to GND in 6/29.
B
1 2
EC_WL_LED#
<30>
@ Q47 RHU002N06_SOT323
02/26 Add R2272 for EC output and driver WLAN LED C
1
PLT_RST#
<25,30,32> STB_LED# <25,30> CAPS_LED# <25,30> NUM_LED# <30,34> VCC1_PWRGD
S
2 0_0402_5%
*WLAN LED Control note
JP27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
<19,25,30> LPC_FRAME#
<19,25,30> <19,25,30> <19,25,30> <19,25,30>
D
2 G
@ R388 100K_0402_5%
B+
<15> CLK_33M_LPC
<7,18,20,22,24,25,30>
XMIT_OFF#
<20,25> XMIT_OFF#
Change from +3VL to +3VS. 6/9 Removed +3VS. 6/13
Add in 7/24.
1 2
R741
C
100K_0402_5%
+3VL
3
1
LPC Debug Port
<25,32>
R2272
Ground LPC_PCI_CLK Ground LPC_FRAME# +V3S LPC_RESET# +V3S LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 VCC_3VA PWR_LED# CAPS_LED# NUM_LED# VCC1_PWRGD SPI_CLK SPI_CS# SPI_SI SPI_SO SPI_HOLD# Reserved Reserved Reserved
WLAN have 3 ways control , the table list componet must be stuff
1 2 3
WLAN Card
R2263
XMIT_OFF#
R388
EC control
R2270
CAP LED Q47 R2271
+3VS
R2272 D26 CAPS_LED#
1
R389 2
1
17-21SYGC/S530-E1/TR8_GRN
2 200_0402_5%
GREEN
B
ACES_87216-2404_24P CONN@ +3VALW
WL ON/OFF Charge LED
WLAN14@ R735 10K_0402_5%
1 R391 200_0402_5%
<30,32> WL_BTN#
4
GREEN
17-21SYGC/S530-E1/TR8_GRN 14@ D28
2
1 STB_LED#
D34 @ SF10402ML080C_0402
2
R390 200_0402_5%
WL_BTN#
WLAN14@ SW1 1BT002-01210_4P 1
5 6
1
3
2
1 2
+3VL
2
+3VL
R392 200_0402_5% 14@
+3VS
1
02/06 change Battery LED to +3VL
POWER LED
Battery LED
3
2
2 A
A
D27
<30> AMBER_BATLED# <30> GREEN_BATLED#
5
AMBER_BATLED# GREEN_BATLED#
4
AMBER
1
19-22UYSYGC/S530-A2/TR8_ G/Y
GREEN Compal Secret Data
Security Classification 2006/10/26
Issued Date
Deciphered Date
2006/07/26
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
www.vinafix.vn 3
2
Title Size Date:
Compal Electronics, Inc. BIOS ROM/PS2/LED/SW
Document Number
Rev 1.0
LA-3491P
Thursday, April 12, 2007
Sheet 1
31
of
47
LID_SW
POWER SWITCH 2
SW3 14@ 1BT002-01210_4P 3 1 2
SPPB530600_4P
1
3
1
4
2
LID_SW#
@ SW2
ON/OFF#
5 6
4
D29 SF10402ML080C_0402 @
SPPB530600_4P 3
1
4
2
LID_SW#
SW4 14@
3
Power button
+5VS
1
R393
2
7
D
S
ON/OFFBTN_KBC#
2
<30>
6 5 4 3 2 1
+3VALW R396 1 2 100K_0402_5%
2 G
100K_0402_5% 1 C388 1U_0603_10V4Z
JP25
ON/OFFBTN_KBC#
1
G
I
U22A SN74LVC14APWLE_TSSOP14 R395 2 1 2 O
3
14 P
2 1
1 C387 1U_0603_10V4Z
1
100K_0402_5% 2
R394
ON/OFF#
1
+3VL
+3VL
100K_0402_5%
D30 @ PSOT24C_SOT23
T/P Board 1
+3VL
2
TP_DATA TP_CLK
2/16 Co lay for 14" assembly issue
Q21 RHU002N06_SOT323
1
2
ON/OFFBTN#
ON/OFFBTN#
2
C386 0.1U_0402_16V4Z
TP_DATA <30> TP_CLK <30>
ACES_87151-06051 CONN@ @ C389 100P_0603_50V8J
<20>
D31 CH751H-40_SOD323
1
1
2
2
EMI C390 @ 100P_0603_50V8J
12/25
+3VS
+3VALW JP26
<25,30,31> STB_LED# <25,31> WL_LED# <30,31> WL_BTN# <17,30> LID_SW#
ON/OFF# STB_LED# WL_LED# WL_BTN# LID_SW#1 R397
2 LID_SW#_R 1K_0402_5%
1 2 3 4 5 6 7 8
ACES_85201-0805_8P CONN@
Compal Secret Data
Security Classification Issued Date
2006/10/26
Deciphered Date
2006/07/26
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
www.vinafix.vn
Title Size Date:
Compal Electronics, Inc. ON_OFF/LID/TP
Document Number
Rev 1.0
LA-3491P
Thursday, April 12, 2007
Sheet
32
of
47
A
B
C
D
E
1
1
1
+5VALW
C394
R398
2
+VCCP
100K_0402_5% 2
0.1U_0402_16V4Z <29,38>
C395 +VCCP
1
2
<20,38> SLP_S5#
0.1U_0402_16V4Z C396 +1.5VS
1
SLP_S5
SLP_S5
+1.5VS
2
1
1
D
3
+VCC_CORE
S
SLP_S5#
2 G Q22 RHU002N06_SOT323
+1.8V
0.1U_0402_16V4Z
+3VALW to +3VS Transfer
+5VALW to +5VS Transfer
+3VALW +5VALW
+5VS
+3VS
B+
2
2
U24
AO4422_SO8 2 10U_0805_10V4Z
1
C401
2
2
1
330K_0402_5% C402
C397
S S S G
10U_0805_10V4Z
1
AO4422_SO8 2 10U_0805_10V4Z
10U_0805_10V4Z
C399
1
+3VL
C400
R400 2
2
100K_0402_5%
RUNON 1
RUNON J5
2
1
D D D D
1
R399
R401
<38>
SLP_S3
SLP_S3
470_0402_5%
D 2
SLP_S3 2 G Q23 RHU002N06_SOT323
1 3
SHORT PADS
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
S 2
<20,30,39>
C403
SLP_S3#
SLP_S3#
D
S
2 G
Q24 RHU002N06_SOT323
0.01U_0402_25V7Z
1
1 2 3 4
1 2 3 4
3
S S S G
8 7 6 5
1
C398
D D D D
2
1
8 7 6 5
1
U25
3
3
Discharge circuit +2.5VS 1
<30,34,40,42>
+3VS
+1.5VS
+5VS R402
R403
R404
R406
470_0402_5%
470_0402_5%
470_0402_5%
1
1
1
1
+1.8V 1
+0.9V
PWR_GD
R407
R408
R410
S
470_0402_5%
SLP_S3 2 G Q31 RHU002N06_SOT323
1 2
SLP_S3 2 G Q30 RHU002N06_SOT323
D
D
3
S
1 2
D
3
2 SLP_S3 2 G Q29 RHU002N06_SOT323
1
S
470_0402_5%
3
SLP_S3 2 G Q28 RHU002N06_SOT323
1 2
S
D
3
2 0_0402_5%
SLP_S5 2 G Q26 RHU002N06_SOT323
1 2
1
S
2 G
D
3
2 @ 0_0402_5%
1 2 SLP_S5 1 R409 SLP_S3
D
3
470_0402_5%
S
Q25 RHU002N06_SOT323
4
4
Compal Secret Data
Security Classification 2006/10/26
Issued Date
2006/07/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
www.vinafix.vn C
D
Title Size Date:
Compal Electronics, Inc. Document Number
DC/DC Circuits
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet E
33
of
47
+3VS
+3VS
+3VL
+3VL
1
+3VL +VCCP
+3VL
3
E
2 D
9 1 +3VS
0.1U_0402_16V4Z
2
I
O
8
S
2 G
C405
SN74LVC14APWLE_TSSOP14
<30,31>
Q33 RHU002N06_SOT323
0.1U_0402_16V4Z
1
2
C404
1
O
SN74LVC14APWLE_TSSOP14
G
1
VCC1_PWRGD U22D
P
I
100K_0402_5%
14
D32 CH751H-40_SOD323 1 2
6
3
Q40 MMBT3904_SOT23
7
1 2 B
SN74LVC14APWLE_TSSOP14
U22C
7
O G
I
C
5
2
R415 1 2 47K_0402_5%
4
P
1
3
1
1
U22B
P
330_0402_5% 330_0402_5%
G
14
R2242 1K_0402_5%
10K_0402_5%
R416 14
R413
7
R2241
1
2 2
2
R414 +3VL
C
E
1
Q41 MMBT3904_SOT23
+5VS
3
2 B
+3VL
R417
@
10K_0402_5% J6 2
0.1U_0402_16V4Z
1
1
D
3
U22E
S
O
10
G
I
2
2
7
1 560K_0402_5%
PWR_GD
PWR_GD
<30,33,40,42>
C407
2 G
SN74LVC14APWLE_TSSOP14
1
+3VL
VDD
VCC1_PWRGD
3
RESET#
2
P
2
11 1
2
SHORT PADS 14
180K_0402_5%
R419
@ U32 TCM809TENB_SOT23-3
2
C406
GND
1
1 R418
Q35 RHU002N06_SOT323
0.1U_0402_16V4Z
02/07 Reserve RESET IC U32 for VCC1_PWRGD
2
Q36 RHU002N06_SOT323
1
1
1
H1 HOLEA
H2 HOLEA
H3 HOLEA
H4 HOLEA
H5 HOLEA
H6 HOLEA
H7 HOLEA
H8 HOLEA
H9 HOLEA
H14 HOLEA
1
1
CF10
1
CF9
1
CF8
1
1
CF7
1
CF6
1
CF5
1
CF4
1
CF3
1
PMST3904_SOT323
CF2
1
CF1
+3VS
PMST3904_SOT323
1
S
1
SN74LVC14APWLE_TSSOP14
1
D
2 G
1
E
E
12
1
Q38
O
R2244
12/27
FM1 10K_0402_5%
FM2 1
FM3 1
FM4 1
FM5 1
FM6 1
2
1
H21 HOLEA
H23 HOLEA
H24 HOLEA
H25 HOLEA
H26 HOLEA
1
H20 HOLEA
1
H19 HOLEA
1
H18 HOLEA
1
H17 HOLEA
1
H16 HOLEA
1
H15 HOLEA
1
12/27
1
Q42 RHU002N06_SOT323
1
S
<39>
1
1 3
VCCP_ON D
2 G
1
2 B
I
1
1 2 @ R2243 0_0402_5%
3
VCCP_POK
Q37 3
1
C <39>
1
C 2 B
U22F
P
1
13
1
1
1
330_0402_5%
3
R422
330_0402_5%
14
R421
1K_0402_5%
+3VL
G
R420
+2.5VS
2
2
+2.5VS
7
+1.5VS
12/27 Compal Secret Data
Security Classification Issued Date
2006/10/26
Deciphered Date
2006/07/26
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
www.vinafix.vn
Title Size Date:
Compal Electronics, Inc. Document Number
POK CKT
Rev 1.0
LA-3491P
Monday, April 02, 2007
Sheet
34
of
47
A
B
C
D
1
1
VIN
1
PC4 100P_0402_50V8J 2 1
PC2 100P_0402_50V8J
PC3 1000P_0402_50V7K
2
4 2 PCN1 SINGATRON_2DC_S736I201
1
2
PR3 15K_0402_5% 2
1
2
PC5 1000P_0402_50V7K 2 1
1
1
4
ADPIN
2
3
3 1
2
PL1 SMB3025500YA_2P
6
5
2
3
3
4
4
Compal Secret Data
Security Classification Issued Date
2006/10/26
Deciphered Date
2006/07/26
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
www.vinafix.vn
DC CONN
Rev
LA-3491P
Monday, April 02, 2007
Sheet D
35
of
47
B
C
D
B+
P5
P2 VIN
4
1 3
1 3
1 2 3
1 1
PC15 10U_1206_25V6M
1 PR23 3K_0402_1% 2 1
PC14 4.7U_1206_25V6K 2 1
2
2
1
PR22 3K_0402_1%
5 6 7 8 2 1 2
1 2
3
PR32 10K_0603_0.1%
+3VALW
1
1
2 1
PR155 47K_0402_5%
D
1
1
2
2
2
PR154 100K_0402_5%
PQ33 2
Batt_Det
1
G D PR156 S RHU002N06_SOT323-3 17.4K_0603_0.1% 2 G PQ34 S RHU002N06_SOT323-3
<41>
"Lo": 4/8 CELLS LI-ION "Hi": 6 CELLS LI-ION
3
@15K_0402_1%
PR37 47K_0603_0.1%
3
2
RLZ4.3B_LL34
PR39
2 1 PC24 470P_0402_50V7K
2
P2 PR38
ADP_PRES <30,37,42>
PR36 10K_0402_5%
2
ADP_PRES
PR35 @75K_0402_1%
1
1
1
LM393DG_SO8
2 1 PC23 @100P_0402_50V8J
3.2V
PD6
PC25 22P_0402_50V8J 2 1
2
1 PR29 10K_0402_1%
PU2A
O
PC18
PR27 604K_0603_0.1%
1
2 -
2
CV=16.8V (4/8 CELLS LI-ION) =12.6V (6 CELLS LI-ION) CC=1.54A (4 CELLS LI-ION) =3A (6/8 CELLS LI-ION)
BATT
2
1 PR60
47_1206_5%
P
2
+
G
3
1 PC168 @10U_0805_6.3V6M 2 1
PC107 0.1U_0603_25V7K 2
8
1
4
1
133K_0603_1%
PR30
2 1 PR34
2
PR33 2.15K_0402_1% 1 2 10K_0603_0.1%
PC22 0.047U_0402_16V7K 2 1
2 1
VIN
VIN
RLS4148_LLDS2
2
1 2
+3VLP
PR28 100K_0402_5%
1
2 P2
BATT PR19 0.015_2512_1% 1 2
PD5 EC31QS04
1
1
PC17 4.7U_0805_6.3V6K
1 2 1
2 1
1 2
PR26 1 2 1M_0402_5%
ADP_PRES
4
LX_CHG 1 2 PL3 16UH_SIL104R-160PF_3.6A_30%
1
RHU002N06_SOT323-3
PQ32 RHU002N06_SOT323-3
PQ9 FDS4435BZ_SO8
2
S
DH_CHG SE_CHG+ SE_CHG-
PR25 150_0402_1%
74LVC1G86GW_SOT353-5
PQ45
VS VHSP GND BATSET BATDEP GND NC4 NC3
18 20 29 6 1 17 23 14
S
1
PC20 150P_0402_50V8J
PD18
4
2
3 Y
4
COMP NC1 NC2
25 22 21 16 15 12 24
2
B
PU18
ENABLE ACSEL ALARM SRSET ACSET ACPRES IBAT VREF
ACDRV# VCC PWM# SRP SRN BATP BATDRV#
D
D
0.1U_0402_16V7K
1 2
1
A
ACN ACP ACDET
PR153 100K_0402_5% 2 1 2 G
ADP_PRES2 G PQ31 S RHU002N06_SOT323-3
BQ24703_QFN28
2
2
<30>
SN74LVC1G14DCKR_SC70-5
PC13 1U_0603_10V6K
5
1 NC
P D
2 G
1K_0402_5%
SN74LVC1G14DCKR_SC70-5
5
PR251 1K_0402_5% 1 2
3
1 2
BATCON
G 4
P
1
PU17
Y
G
P A
NC
5
+3VL
3 1000P_0402_50V7K
1
3
2
Y
4
1
1
PR248
PU19
2
PC157
2 1 PR249 470K_0402_5%
CHGCTRL
A
+3VL
G
1 2 PR250 470K_0402_5%
PC158 2 1
0.047U_0402_16V7K
2
5 28 19 2 3 27 13 4 7 10 11
PR24 32.4K_0402_1% 2
+3VL +3VL
PR20 137K_0402_1% PC19 1U_0603_6.3V6M 2 1
2 191K_0402_1%
PR21 100K_0402_1%
PR17
1
PR13 0_0402_5% 2 1
PU1
PC21 4.7U_0805_10V6K
2
2 PR18 1 +3VLP 100K_0402_5% BQ24703VREF
+3VLP
1
PR31 0_0402_5%
CHGCTRL
1 2
PD3 RLZ16B_LL34 SE_ConPWR- 8 SE_ConPWR+ 9 26
PR16 PQ10 @0_0402_5% RHU002N06_SOT323-3ADP_PRES2 1
2
3
2
PC11 1U_0603_6.3V6M
1
S
2 G
2 1
1 1
D
3
PR15 ADP_PRES 1 2 3K_0402_5%
PR12 100_0402_1%
PC10 4.7U_1206_25V6K
1 2
PR14 150K_0402_5%
3
S PQ8 RHU002N06_SOT323-3
PR11 100_0402_1%
PC9 10U_1206_25V6M
CHG_B+
3
2 G
1
PL2 FBM-L11-322513-151LMAT_1210 1 2
1 PQ6 DTC115EUA_SC70-3
VIN
4
PR9 0.015_2512_1% 1 2
DTA144EUA_SC70-3
D
PR6 1 2 47K_0402_5%
1 PR7 200K_0402_5%
1
PC8 1
2 PQ5
8 7 6 5
2
4
0.22U_0603_16V7K
1
2
2 1
3 2 1
2
PR10 47K_0402_1% 1 2
3 2 1
3
PC7 47P_0402_50V8J 1 2
PR5 47K_0402_5% 2 1
8 7 6 5
PQ4 FDS4435BZ_SO8
8 7 6 5
1
2
3 2 1
P4 PQ3 FDS4435BZ_SO8
BATT
PQ2 FDS4435BZ_SO8
PR256 @0.015_2512_1% 1 2
PC12 1U_0805_25V4Z
A
2
60.4K_0402_1% PU3
4
REF
CATHODE NC
5
ANODE
NC
1.24VREF
3
4
2 1
LMV431ACM5X_SOT23-5
Compal Secret Data
Security Classification Issued Date
Deciphered Date
Title
Compal Electronics, Inc. Charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
www.vinafix.vn
Monday, April 02, 2007 D
Sheet
Rev 36
of
47
B
BST_5V_B
VL
PC41 0.047U_0603_16V7K
1 2
PC32 4.7U_1206_25V6K
1 2
PC31 2200P_0402_50V7K
2 1
2
PR46 0_0402_5%
1
2
1 2 1 PR48 @499K_0402_1%
1
2
1 2 1 2
PL6 10U_LF919AS-100M-P3_4.5A_20%
BST_3.3V DH_3.3V DL_3.3V LX_3.3V
2
1
PC34 1U_0805_16V7K
17
20
PR47 @499K_0402_1%
2
7 2 2
MAX8734AEEI+_QSOP28
+3VLP 1
10
PRO#
+3VALWP
1
PR57 0_0402_5%
2
PR55 @3.57K_0402_1%
1
DH_3.3V_B
0_0402_5% PR45
1 + 2
1
2 1
1
VL
PC38 220U_6.3VM_R15
3
1
2
3
PR244 300K_0402_5% 2
PR56 2 1 499K_0603_1%
28 26 24 27 22
SP8K10S-FD5_SO8
2
REF
11
FB3 PGOOD
SKIP#
8
ILIM5 BST3 DH3 DL3 LX3 OUT3
8 7 6 5
2
12
MAINPWON <41>
V+
SHDN# ON5 ON3
PC39 0.22U_0603_10V7K
MAINPWON
5
ILIM3
D2 G2 D2 D1/S2/K G1 D1/S2/K S1/A D1/S2/K
PR58 0_0402_5%
6 4 3
PR51 1 2 @0_0402_5% 1 2 PR53 @10K_0402_5%
PR43 0_0402_5%
1 2 3 4
1
2 0_0402_5%
PR44 0_0402_5%
1 LX5 DL5 OUT5 FB5 N.C.
2VREF_1999 VL
2
15 19 21 9 1
VCC
DH5
LX_5V DL_5V
TON
16
PR50
18
BST5
DH_5V
PC40 4.7U_0805_10V4Z
1
PU4
PC30 0.1U_0603_16V7K
2VREF_1999
2
23
PR52 47K_0402_5% 2 1
2VREF_1999
2VREF_1999
2 1 PC37 0.1U_0603_25V7K
PR49 @10.2K_0402_1%
1 2 1
150U_D2_6.3VM
2
PR54 0_0402_5%
2
+5VALWP
1
GND
BST_5V 14
2
VL
LD05
PC35 4.7U_0805_10V4Z
1 2
PL5 10U_LF919AS-100M-P3_4.5A_20%
+
2 PC33 2 1 0.1U_0603_50V4Z
1
<42> LX_5V
1
2 PR42 0_0402_5%
PC36 1
PR41 47_0402_5%
B++
SP8K10S-FD5_SO8
B++
B++ PQ12
13
D2 G2 D2 D1/S2/K G1 D1/S2/K S1/A D1/S2/K
LDO3
1 2 3 4
1
PD7 CHP202UPT_SOT323-3
PR40 0_0402_5% 8DH_5V_B 1 2 7 6 5
25
PQ11
E
PC27 0.1U_0603_50V4Z 1 2
BST_3.3V_B 3
2 1 PC29 10U_1206_25V6M
FBM-L11-322513-151LMAT_1210 2 1
2 1 PC28 2200P_0402_50V7K
B+
PC26 0.1U_0603_50V4Z 1 2
B++
D
1
PL4
1
C
2
A
PR59 100K_0402_5%
PQ13 2
1
D
2 ADP_PRES <30,36,42> 2 G G PQ14 PQ15 S RHU002N06_SOT323-3 RHU002N06_SOT323-3
KBC_PWR_ON <30>
3
3
S
1
D
1
3
2 G S RHU002N06_SOT323-3 D
4
4
Compal Secret Data
Security Classification 2006/10/26
Issued Date
Deciphered Date
2006/07/26
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
www.vinafix.vn
D
Compal Electronics, Inc. 3.3VALWP / 5VALWP
Document Number
Monday, April 02, 2007
Sheet E
37
Rev of
47
5
4
3
2
1
PL15 FBMA-L11-322513-151LMA50T_1210 1.8V_B+ 2 1
2
2
1 2
PC46 0.1U_0402_16V7K
1
PL7 3.3UH_PCMC063T-3R3MN_6A_20% 1 2
2
4
PR252 @4.7_1206_5%
1
9
PC159 @680P_0603_50V7K
PC122 1U_0603_10V6K
2
SC411MLTRT_MLPQ16_4X4
3 2 1
DL
1
VDDP
10
PQ17 FDS6690AS_NL_SO8
LX_1.8V PR162 1 2 18.2K_0402_1%
2
11
1
5 6 7 8 12
LX
8
PGND
VSSA
7
17
DH
ILIM
PGD
3 2 1
BOOT_1.8V 1
13
15
14 NC
16
FB
TP
4
6
3
1
PC119 0.1U_0402_16V7K
2
VCCA
BOOT1_1.8V
2 0_0402_5%
BST
VOUT
2
EN/PSV
1
NC
1 PC121 1U_0603_10V6K
1
TON
PU11
2
2
PR247 @0_0402_5%
2
1
<20> SLP_S4#
PR245 100K_0402_5%
5
1 PC120 @2200P_0402_25V7K
UG_1.8V
PR161
1
2
PR246 0_0402_5%
2
1
<20,33> SLP_S5#
1SS355_SOD323-2
2
2
PC118 1000P_0402_50V7K
D
4
PD14
1
1 PR159 470K_0402_5%
2
5 6 7 8 1 PR158 1M_0402_5%
2
D
PR157 10_0402_5%
1
+
2
PQ16 FDS8884_SO8
PC45 0.1U_0402_16V7K
1
PC42 220U_V_4VM_R25M
2 1 PC44 10U_1206_25V6M
2
PC116 680P_0402_50V7K
+1.8VP
+5VALW
PC43 2200P_0402_50V7K 2 1
1
B+
C
C
LG_1.8V
PR163 1 2 27K_0603_0.1%
(500mA,40mils ,Via NO.= 1)
PU6 APL5508-25DC-TRL_SOT89-3
2
2
+2.5VSP
3
GND 1
1
OUT
1
1
PR164 10K_0603_0.1%
IN
PR260 @150_1206_5%
2
2
2
1
+3VS
PC51 4.7U_0805_6.3V6K
2 PC123 33P_0402_50V8J
PC50 1U_0603_10V6K
1
B
B
+1.8V
PU7
1
2
+1.8V
(7A,280mils ,Via NO.= 14)
1
2
+3VL
(100mA,20mils ,Via NO.= 1)
+VCCP
(6A,240mils ,Via NO.=12)
+1.5VS
(4A,160mils ,Via NO.=8)
+0.9V
(2A,80mils ,Via NO.= 4)
1
P5
7
NC
1
NC
VOUT
8 2
1
1
VREF
+5VALW
9
PC57 1U_0603_16V6K
G2992F1U_SO8
2
PR255 @0_0402_5%
PQ18 RHU002N06_SOT323-3
<33> SLP_S3 2
1
3
TP
1
1
PJP9 B+
PJP5 +1.05V_VCCP
2
PAD-OPEN 2x2m
PAD-OPEN 4x4m
A
<29,33> SLP_S5
PJP8 +3VLP
PAD-OPEN 4x4m PJP4 +1.8VP
(500mA,40mils ,Via NO.= 1)
5
1 PR75 0_0402_5%
PAD-OPEN 4x4m
2
D
S
PR74 1K_0402_1%
2 G
+0.9VP
PC59 10U_1206_6.3V7K
PC60 @0.1U_0402_16V7K
2
+3VALWP
2
+2.5VS
PAD-OPEN 3x3m
PAD-OPEN 4x4m PJP3
1
2
6
NC
1
1
2
+3VALW
(3A,120mils ,Via NO.= 6)
+2.5VSP
VCNTL
GND
4
2 1 PC58 0.1U_0402_16V7K
(4.5A,180mils ,Via NO.= 9)
VIN
2
2
+5VALW
2
2
PR73 1K_0402_1%
1
1
1
+5VALWP
PJP2
3
PJP1
2
2
PC55 10U_0805_10V4Z
PC56 @10U_0805_10V4Z
1
1
A
PAD-OPEN 4x4m PJP6 +1.5VSP
1
2 PAD-OPEN 4x4m PJP7
+0.9VP
1
2
Compal Secret Data
Security Classification Issued Date
PAD-OPEN 3x3m
2006/10/26
Deciphered Date
2006/07/26
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
www.vinafix.vn
2
Compal Electronics, Inc. 1.8VP/0.9VSP/2.5VSP
Document Number
Rev 1.0
LA-3491P Monday, April 02, 2007
Sheet 1
38
of
47
5
4
3
2
1
D
D
B+++
PR165 73.2K_0402_1% 1 2
PR167 75K_0402_1%
PR166 75K_0402_1% 1 2
1
PR168 29.4K_0402_1%
2
1
2
2
2
1
PC64 4.7U_1206_25V6K
5 6 7 8
PR169 0_0402_5%
1
PQ20 FDS8884_SO8
PC61 @2200P_0402_50V7K 2 1 PC62 10U_1206_25V6M
2
1
PL8 FBMA-L11-322513-151LMA50T_1210 1 2 PC63 @2200P_0402_50V7K 2 1
B+
DR VL1
PGND2
DR VL2
17
16
15
14
13
PR176 16.5K_0402_1% 1 2
PR178 10K_0402_5% 2 1
UG_1.05V
2
1
+1.05V_VCCP
2
0.1U_0603_25V7K
20 19
1
LX_1.05V
1 1
21
LL1
PL9 2.2UH_PCMC063T-2R2MN_8A_20%
PC125
LG_1.05V PC72 4.7U_0805_6.3V6K 4
TPS51124RGER_QFN24_4x4
+ 2
PC71 220U_6.3VM_R15
2
DR VH1
LL2
3 2 1
1
1
2
DR VH2
11
PC74 4.7U_0805_6.3V6K
PQ35 FDS6690AS_NL_SO8
PR177 18.2K_0402_1%
B
1
2
<20,30,33> SLP_S3#
VO1
VFB1
4
3 GND
5
10
PR175 0_0402_5% 1 2
BST_1.05V
1
2
TONSEL
22
2
+
VO2
VBST1
1
1
220U_6.3VM_R15 PC73 B
VBST2
12
LG_1.5V
3.3UH_SIQB74-3R3RF_4.8A_30%
9
2
LX_1.5V
1
EN1
PR173 0_0402_5% 1 2UG1_1.05V
23
5 6 7 8
2
UG_1.5V
0.1U_0603_25V7K
EN2
12/29
24
3 2 1
PL10
PGOOD1
PGND1
SP8K10S FD5 2N SOP8
+1.5VSP
BST_1.5V
PGOOD2
8
TRIP1
PR174 PC124 0_0402_5% 2 1 1 2
C
PC163 @0.022U_0603_25V7K
18
UG1_1.5V
8 7 6 5
P PAD
7
V5IN
D2 G2 D2 D1/S2/K G1 D1/S2/K S1/A D1/S2/K
1 2 0_0402_5%
V5FILT
1 2 3 4
PR171
TRIP2
PQ19
25
PR170 0_0402_5% 1 2
VFB2
PU12
6
VCCP_POK <34>4
C
PR179 3.3_0402_5%
VCCP_ON <34>
2
PC127 1U_0603_10V6K
2
1
2
1
PC126 0.1U_0402_16V7K
PC128 4.7U_0805_10V6K
1 1
2
1
+5VALWP 2
SLP_S3#
@0_0402_5% PR180
12/29
2
PC129 @1000P_0402_50V7K
A
A
Compal Secret Data
Security Classification 2006/10/26
Issued Date
Title
Deciphered Date
1.05VSP/1.5VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
www.vinafix.vn
2
Monday, April 02, 2007
Rev 1.0 Sheet 1
39
of
47
4
3
2
+5VS
1
CPU_B+
11
REF
CCI
10
CC1_CPU
21
DH2_CPU
BST2
20
BST2_CPU
LX2
22
LX2_CPU
2
PWRGD
DL2
24
DL2_CPU
38
4
DPRSTP
CLKEN
PGND2
SHDN
CSP2
VRHOT
CSN2
POUT
GNDS
2
15
CSN2_CPU
13
2
1
MAX8770GTL+_TQFN40
2
PR212 @10K_0402_5%
PR213 100_0402_5%
<5>
VSSSENSE
2
1
PC134 2200P_0402_50V7K 2 1
PC133 10U_1206_25V6M 2 1
5 6 7 8 D D D D G S S S 4 3 2 1 NTC PR206 @3K_0603_1% 2
2
PR207 @3K_0603_1% 1
PR209 20K_0402_1%
PR253 4.7_1206_5%
2 1
PC142
VCCSENSE
1
2 @0.022U_0402_16V7K
1 PR203
PQ39 SI4684DY-T1-E3_SO8
PR216 1
2.2_0402_5% 2
VCCSENSE <5>
2 100_0402_5%
4700P_0402_25V7K
2 CPU_B+
PC143 470P_0402_50V8J
VSSSENSE
PC149 0.1U_0402_16V7K
C
2
B
PL18
0.36UH_PCMC104T-R36MN1R17_30A_20% 2
2
1
PR217 2.1K_0603_1% 1
2 10K_0402_5%
2
2
PC140 0.22U_0603_16V7K
PR254 4.7_1206_5%
2 @0_0402_5%
1 PR215
2 3.65K_0402_1%
1
10KB_0603_5%_ERTJ1VR103J
1
1 PC141
2
1 PR214
1 PR202
PQ40 FDS6676AS_SO8 4 G D 5 3 S D 6 2 S D 7 1 S D 8
1
2
POUT
2 @3K_0603_1%
1 2 PR195 3.48K_0402_1%
PC161 680P_0603_50V7K
<4> H_PROCHOT#
1
1 PR200
PQ41 FDS6676AS_SO8 1 2 1
B
1
12/29
CSP2_CPU
1
<30,33,34,42> PWR_GD
1 2 PR208 0_0402_5% 1 2 PR210 0_0402_5% 1 2 PR211 0_0402_5%
2
<15> CLK_ENABLE#
14
1
1
<7,20> VGATE_INTEL
23
TP
2
1
5 PR204 2K_0402_1%
DH2
PSI
1
PR205 1.91K_0402_1%
DPRSLPVR
3
40
NTC PH3
PC148 2200P_0402_50V7K 2 1
FB1_CPU
PC160 680P_0603_50V7K
12
+VCC_CORE
2
PR191 2.1K_0603_1%
PC146 10U_1206_25V6M 2 1
16
FB
PQ38 FDS6676AS_SO8 2 1
CSN1
CCV
1
TIME
9
2
7
CSN1_CPU
1
CSP1_CPU
2
17
5 6 7 8
CSP1
D D D D
D6
G S S S
37
4 3 2 1
18
5 6 7 8
+3VS
GND
D D D D
H_PSI#
PGND1
D5
39
1
27
D4
36
+VCC_CORE
0.36UH_PCMC104T-R36MN1R17_30A_20%
G S S S
<5>
DL1_CPU
D
PL17
PR187 2.2_0402_5% 1 2
4 3 2 1
<4,19> H_DPRSTP#
26
1 0_0402_5%
5 6 7 8
<7,20> DPRSLPVR
DL1
2 PR185
D D D D
C
LX1
D3
28
DH11_CPU LX1_CPU
G S S S
CPU_VID6
D2
BST1_CPU
29
1
PQ36 SI4684DY-T1-E3_SO8
4 3 2 1
<5>
35
30
DH1
DL1_CPU
CPU_VID5
34
BST1
D1
DL2_CPU
CPU_VID4
<5>
33
D0
PQ37 FDS6676AS_SO8 4 G D 5 3 S D 6 2 S D 7 1 S D 8
<5>
32
8
2 0_0402_5%
CPU_VID3
31
TON
1 PR201
CPU_VID2
<5>
1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 2 1 PR194 71.5K_0402_1% 1 2 PC138 470P_0402_50V8J 1 2 PC139 0.22U_0603_16V7K 1 2 PR196 499_0402_1% 1 2 PR197 0_0402_5% 1 2 PR198 0_0402_5%
VDD
THRM
BSTM2 CPU
<5>
2 PR184 2 PR186 2 PR188 2 PR189 2 PR190 2 PR192 2 PR193
25
Vcc
1 2 PC145 0.22U_0603_16V7K
CPU_VID1
6
PC144 1000P_0402_50V7K
CPU_VID0
<5>
19
41
<5>
VCC
PC137 1 2
PU13 @470KB_0402_5%_ERTJ0EV474J PH2 2 1
0.22U_0603_16V7K
BSTM1 CPU
PC132 10U_1206_25V6M 2 1
+ 2
PC130 47U 25V M 6.3X6 ESR0.44 CE-LX
1
PC147 10U_1206_25V6M 2 1
2 1 2
PR182 200K_0402_5%
2
PR183 13K_0402_5%
2
1 2.2U_0603_6.3V6K
1 2 PC136 1U_0603_16V6K
1
D
1
2
PC135
PC131 0.01U_0402_25V7K
1
2
PR181 10_0402_5%
B+
PL16 FBM-L11-322513-151LMAT_1210
PC162 1000P_0402_50V7K
5
NTC PH4 1
2
1
PR218 3.48K_0402_1%
PC150
A
2
10KB_0603_5%_ERTJ1VR103J
1
2 0.22U_0603_16V7K
A
Compal Electronics, Inc. Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, April 02, 2007
5
4
www.vinafix.vn 3
2
Rev 1.0 Sheet 1
40
of
47
A
B
VMB PCN2 BATT+
6
SMD SMC RES TS
5 4 3 2
GND
1
D
BATT
PL14
HCB4532KF-800T90_1812 1 2 1
<36> PR136
2
PR137 210K_0402_1% 1 2
1 1
1 PR139 100_0402_5%
2
PD10 @SM05_SOT23 1
3
TYCO_C-1746706_6P
2
3
1
2 1 @1K_0402_5%
+3VL
1
Batt_Det
PC105 1000P_0402_50V7K
2
EC_SMD EC_SMC
1
1
C
PC106 0.01U_0402_50V4Z
PD11 @SM24.TC_SOT23-3
PR138 1K_0402_5%
THM_MAIN# <30>
2
2
2
PR140 100_0402_5% SMB_EC_DA1
SMB_EC_DA1 <30>
SMB_EC_CK1
SMB_EC_CK1 <30>
2
2
PH1 under CPU botten side : CPU thermal protection at 90 +-3 degree C Recovery at 47 +-3 degree C PR141 47K_0402_1% 1 2
+5VS
+5VS 3
PR146 10K_0402_5%
PH1 10K_TH11-3H103FT_0603_1% 1
2
2
CPU
1
3
2
PR145 150K_0402_1%
1
D
S
P
7
PQ29 RHU002N06_SOT323-3
2 G
LM393DG_SO8
1
1
PR144 2.55K_0603_1%
-
PU2B O
4
PR143 150K_0402_1%
+
G
2
3
6
8 5
1
MAINPWON <37>
PC109 1000P_0402_50V7K
2
2
PC108 0.22U_0603_10V7K
2
1
1
+5VS
PR142 15K_0603_1% 1 2
4
4
Compal Secret Data
Security Classification Issued Date
2006/10/26
Deciphered Date
2006/07/26
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BATTERY CONN
Rev
LA-3491P
Date:
A
B
C
www.vinafix.vn
Monday, April 02, 2007
Sheet D
41
of
47
5
4
3
2
1
+5VS
+5VS +3VS
PD15 1
+5VS
1
@LMV431ACM5X_SOT23-5
4 @0.027U_0402_16V7K
PC154 2 1
1 2 1
PC151 @1U_0805_16V7K
1
1
O
2
D
PR229 @10_0402_5%
@LM393DG_SO8 2
P G
8
2 1
@80.6K_0402_1%
PR234 2 1
2
PC156 @3900P_0402_50V7K
1 2
@3.9K_0402_5% PR241
3
E PR242 @124K_0402_1% 1 2
PR259 @1M_0402_5% 2 1
3
1 <30,36,37> ADP_PRES
PQ44 @MMBT3904W_SOT323-3
-
1
2 PR233 @604K_0603_1%
LX_5V
<37>
PR238 1
<30,33,34,40>
2 @0_0402_5%
OCP#
<4,20,30> C
1
2
C
2 B
2
G
2
1
PWR_GD
2 G S
+
2
1
PD17 @CH751H-40PT_SOD323-2 1 2
D PQ46 @RHU002N06_SOT323-3
3
PR224 @10K_0402_5%
PU15A 2
1
1 NC
PR236 @3.9K_0402_5%
2 @100K_0402_5%
@LM393DG_SO8
1
ANODE
2
PR258 @1M_0402_5% 2 1
2
PR240 @0_0402_5%
B+
2
NC
1
3
7
PR231 1 2 @0_0402_5%
@MMBT3906_SOT23-3
PR237
5
CATHODE
O
D
3
PR235
1
PQ42
2
@2.2U_0603_6.3V6K
PC155 2 1 1
C
REF
-
1 2 PR239 @470K_0402_5%
2
PC152 @0.22U_0603_16V7K
4
+
6
4
@LM358ADR_SO8
PU16
5
P
8 1
7
PU15B
1
-
0
PR232 @2K_0402_5% 2 1
6
PU14B
1
2
@CH751H-40PT_SOD323-2 @CH751H-40PT_SOD323-2
PR221 PR220 @133K_0402_1%
PR222 @10K_0402_5%
3
2 PR228 @100K_0603_0.5%
+
P
PR227 @10K_0402_1%
5
@110_0603_1% @7.32K_0402_1% 2 1 PR257 @6.98K_0402_1%
1 PR230 2
@0_0402_5%
2 @6.81K_0402_1% 2 1
G
1
8
PR226
@LM358ADR_SO8
4
8 P G 4
1 2 PR225 @0_0402_5% 1
-
P5
2
1
PC153 @1U_0805_50V4Z
2
PR223 @330K_0402_5% 2 1
B
0
PU14A 3
+
C
1
E
D
PD16
S
PQ43 @RHU002N06_SOT323-3
2 G
1
D PQ47 @RHU002N06_SOT323-3
2 G
4C#_6C8C <30>
3
S
B
B
A
A
Compal Secret Data
Security Classification 2006/10/26
Issued Date
Deciphered Date
2006/07/26
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
www.vinafix.vn
2
ADP_OCP
Monday, April 02, 2007
Sheet 1
Rev 42
of
47
5
4
3
Version change list (P.I.R. List) Item D
1 2
3
2
HW section
Reason for change
PG#
Modify List
Page 10
Add R2221 R2222 R2223 TV-out power plane
R2211
Page 9
Change R2211
Page 9
Change CPU and NB BCLK follow heavenly2.0
Page 15
5
Change Mini card CLK From SRC3 to SRC7
Page 15
6
CRT connector PCB footprint error
Page 16
C
A
TVDAC_B(R2173) TVIRTNA
TVIRTNB
Phase
01/02
DB2
01/02
DB2
01/02
DB2
01/02
DB2
01/02
DB2
01/02
DB2
D
--->CPUCLKT1/C1
Change to SRC7 Change JP6 PCB Footprint form SUYIN_070912FR015S207CR_15P to ALLTO_C10510-115A5-L_15P
+ENAVDD add a 100k Pull low follow datasheet
Page 17
Add R2247 to GND
8
LCDVDD enable timing
Page 17
Change R159 to 47k
9
Change AND gate that one gate one chip
Page 18
Change U28(4 in 1) to U30
Reserve EE PROM power plane +3VS
Page 19
11
Add R2213 and verify need or not
Page 19
12
Change PCIE from port 1 to port 2 follow caymus
13
Reserve LAN_RST# that can fine tune from EC
14
Change R to RP , keep original design
Page 20
15
Reserve +3VS power plane for don't support wake up LAN
Page 21
16
Reserve +3VALW power plane to verify HDA codec
Page 21
17
Reserve +3VALW power plane support wake up LAN
Page 23
18
Reserve +3VALW power plane support wake up LAN
Page 24
19
Reserve 0 ohm resistor for SMSC1070
Page 30
Page 20 Page 25 Page 20 Page 30
TVDAC_C(R2174) TVIRTNC(R2251)
CPU --->CPUCLKT0/C0
7
10
R2225 for Disable
R2212 to 10K_0402_5%
TVDAC_A(R2172)
NB
B
R2224
Date
Add resistor to +1.5VS power Disable TV-out follow datasheet
TV_IREF(R57) 4
Page 1 of 3
Reserve Disable TV-out power plane resistor
R2212 Change to 10k follow datasheet
1
C
01/02
DB2
01/02
DB2
01/02
DB2
01/02
DB2
Add R2213
01/02
DB2
Change MINI Card PCIE from Port 1to Port2
01/02
DB2
Reserve R2233 for fine tune LAN_RST# timing
01/02
DB2
Change to RP33
01/02
DB2
01/02
DB2
01/02
DB2
01/02
DB2
01/02
DB2
01/02
DB2
C213 to 0.1u U31
Reserve R2230
for don't support wake up LAN
Reserve R2231
for
support wake up LAN
RP34
If R2237 --->support wake up LAN If R2236 --->Don't support wake up LAN If R2234 --->AC97 codec If R2235 --->HD Codec If L11 --->Don't support wake up LAN If L20 --->Support wake up LAN If L12
L13 --->Don't support wake up LAN
If L21
L22 --->Support wake up LAN
Reserve R2238
R2239
R2240
B
A
Compal Electronics, Inc. Title
HW PIR (1)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
Date:
2
Monday, April 02, 2007
Rev 1.0 Sheet 1
43
of
47
5
4
3
Version change list (P.I.R. List) Item D
C
2
HW section
Reason for change
PG#
Page 2 of 3
Modify List
20
Wireless LED design issue
Page 31
Delete Q20
21
Change POK circuit form PGOOD to VCCP_ON
Page 34
Add R2244
22
LID_SW# add 10k pull high
Page 30
23
Change use EAPD# to control Amp Shutdown
24
1
Date
Phase
01/02
DB2
01/02
DB2
Add R2253 for LID_SW# pull high
01/16
SI
Page 28
Reserve R2198 and add R2252 pull high
01/16
SI
Change Battery LED power from +3VALW to +3VL
Page 31
Change Battery LED power from +3VALW to +3VL
02/06
PV
25
XMIT_OFF# control error
Page 31
Delete Q46
02/06
PV
26
Delete KSI PU, 1070 had internal PU
Page 30
Delete RP29
02/07
PV
27
Reserve SMSC 1070 VCC0 to +3VL,Add R2267 to GND
Page 30
Reserve R2266 to +3VL,Add R2267 to GND
02/07
PV
28
Change Codec Mix Resistor from 20k to 1k
Page 28
Change R2264
02/07
PV
29
Change LAN82562GT RBIAS resistor to 649 ohm
Page 23
Change R274 to 649 ohm
02/07
PV
30
Reserve RESET IC for VCC1_PWRGD
Page 34
Reserve RESET IC U32 for VCC1_PWRGD
02/07
PV
31
THM_MAIN# Double pull high
Page 30
Delete R356
02/07
PV
32
Fine tune PC Beep
Page 26
BOM delete R310
02/09
PV
33
Change Hp series resistor to 60 ohm 0603
Page 28
Change R341
02/14
PV
34
Reserve OCP# to EC GPIO29(pin 98)
Page 30
Reserve R2268 to EC GPIO29(pin98)
02/14
PV
35
HP
Page 28
HP
MIC ESD Diode change to AGND
02/14
PV
Page 28
Add inverter to prevent HP pop noise
02/26
PV
Page 06
Change CPU core decoupling capacitor height limit 1.9mm for short term solution(SGA19331D00)
02/26
PV
Page 25
02/26 Add R2270 for WL_LED_EC# PU
Page 30
02/26 Add R2271 for use EC detect WLAN active
02/26
PV
Page 31
02/26 Add R2272 for EC output and driver WLAN LED
Q42, and reserve R2243
RP30
R2265 to 1K
D
C
B
B
36
MIC ESD Diode change to AGND
HP de pop when boot
37
C43
C44
C45 impact ME parts
38
WLAN LED use XMIT_OFF# have error beheive
A
R343 to 60 ohm 0603
A
Compal Electronics, Inc. Title
HW PIR (2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
Date:
2
Monday, April 02, 2007
Rev 1.0 Sheet 1
44
of
47
5
4
3
Version change list (P.I.R. List) Item D
C
2
HW section
Reason for change
PG#
Page 3 of 3
Modify List
39
SMSC leakage current issue
Page 30
Reserve R2273
40
Reserve KSO PU resistor prevent SMSC chip issue
Page 30
Reserve RP35
41
BOM change (Delete CBS de-pop circuit)
Page 26
BOM delete C1479
42
BOM add Keyboard matrix error issue
Page 30
BOM Add Keyboard scan input PU resistor RP29
43
BOM delete (SMSC leakage issue fail)
Page 30
BOM Delete R2273
44
Reserve +RTCVCC for SMSC VCC0
Page 30
Reserve R2277
45
Add CBS SPK depop circuit , change Q43 from FET to BJT
Page 26
BOM add C1479
46
Add R324
Page 20
BOM add R324
R334 can pass ESD test
R2274
RP36
1
R2275
RP37
R2256
Date
R2276 EC dummy pin
RP38 for SMSC KSO
Q43
RP30
R2274
R2256
Q43
R334
Phase
02/27
PV
02/27
PV
03/10
MV
03/10
MV
03/10
MV
03/19
MV
03/19
MV
03/21
MV
D
C
B
B
A
A
Compal Electronics, Inc. Title
HW PIR (3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
Date:
2
Monday, April 02, 2007
Rev 1.0 Sheet 1
45
of
47
5
4
3
Version change list (P.I.R. List) Item D
Power section
Reason for change
PG#
Page 1 of 1
Modify List
Date
Phase
The PR172 changes to HW side
39
Remove PR172
2006/12/29
DB2
2
Change the +1.05V_VCCP power sequence
39
Remove PR180
2006/12/29
DB2
3
The +1.05V_VCCP dynamic range is over spec.
39
Change PL9 from 3.3UH to 2.2UH
2007/01/03
DB2
4
Adjust +1.5VSP voltage range
39
Change PR165 from 75K_ohm to 73.2K_ohm
2007/01/03
DB2
5
Change the PD18 diode
36
Change PD18 from 1SS355 to RLS4148
2007/01/16
SI
Change PC38 from 150U_D2_6.3VM to 220U_6.3V_R15
2007/01/16
SI
Change PC59 from 22U to 10U
2007/01/16
SI
Change PC71 from 220U_V_4VM_R25M to 220U_6.3V_R15
2007/01/16
SI
Change PC73 from 220U_6.3VM_R15 to 220U_6.3V_R15
2007/01/16
SI
Change the +3VALWP output capacitor.
37
7
Change the +0.9VP output capacitor.
38
Change the +1.05V_VCCP output capacitor.
39
Change the +1.5VSP output capacitor.
39
10
Change the +1.5VSP choke size.
39
Change PL11 from 3.3UH_PCMC063T-3R3MN_6A_20% to 3.3UH_SIQB74-3R3RF_4.8A_30%
2007/01/16
SI
11
Change PD14 diode
38
Change PD14 from CH751H-40PT to 1SS355
2007/02/05
PV
12
Adjust PU3 operation current
36
Change PR38 from 75K_ohm to 60.4K_ohm
2007/02/05
PV
Change PC25 capacitor.
36
Change PC25 form .022U to 22P
2007/02/05
PV
Change the +1.5VSP power sequence
39
1. Change PR178 form 0_ohm to 10K_ohm 2. Add PC126 0.1U
2007/02/05
PV
9
13
14
D
C
6
8
A
1
1
C
B
2
B
A
Compal Electronics, Inc. Title
PWR PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
Date:
2
Monday, April 02, 2007
Rev 1.0 Sheet 1
46
of
47
5
4
3
Version change list (P.I.R. List) Item D
2
Power section
Reason for change
PG#
1
Page 1 of 1
Modify List
Date
Phase
15
Add CPU CORE snubber circuit
40
1. add PR253, PR254 4.7_ohm 2. add PC160, PC161 680P
2007/02/05
PV
16
Change PC155 capacitor.
42
Change PC155 form 0.1U to 2.2U
2007/02/05
PV
17
for EMI
40
Change PR187, PR216 form 0_ohm to 2.2_ohm
2007/02/08
PV
18
Remove PR187 and PR219.
40
Remove PR187 and PR219.
2007/02/09
PV
19
Add PR60
36
Add PR60 47_ohm
2007/03/13
MV
D
C
C
20
Change PC8 capacitor.
36
Change PC8 form 0.1U to 0.22U
2007/03/28
MV
20
Change PC8 capacitor.
38
Change PR162 form 16.4K_ohm to 18.2K_ohm
2007/03/28
MV
21
Change PR176, PR177
39
1. Change PR176 from 15K to 16.5K_ohm 2. Change PR177 from 18K to 18.2K_ohm
2007/03/28
MV
B
B
A
A
Compal Electronics, Inc. Title
PWR PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
Date:
2
Monday, April 02, 2007
Rev 1.0 Sheet 1
47
of
47
