IJRIT International Journal of Research in Information Technology, Volume 2, Issue 3, March 2014, Pg: 349-354

International Journal of Research in Information Technology (IJRIT) www.ijrit.com

ISSN 2001-5569

High Speed Wavelet Based FIR Filter Architecture on FPGA Platform 1

2

3

Leji C Koshy1, Olga John2, A Sanjeevi Gandhi3 PG Scholar, Department of Electronics & Instrumentation, Karunya University Coimbatore, Tamilnadu, India [email protected]

PG Scholar, Department of Electronics & Communication, Karunya University Coimbatore, Tamilnadu, India [email protected]

Assistant Professor, Department of Electronics & Instrumentation, Karunya University Coimbatore, Tamilnadu, India [email protected]

Abstract This paper presents a new architecture for high speed implementation of wavelet based FIR filter on FPGA. The proposed architecture presents the advantage to ensure increase in the filter operating frequency thereby reducing the processing time. Different filter architectures are implemented on FPGA using Xilinx System Generator for DSP and Virtex-5 FPGA development board. The proposed architecture is compared with conventional FIR filter architecture in terms of computation frequency, resource utilization, output latency and filtering performance.

Keywords: Pipelining, FPGA, Latency, Critical Path.

1. Introduction In the last decades, the wavelet based FIR filters has been successfully used in numerous applications across several disciplines which include signal and image de-noising [1, 2] and compression [3], signal detection, feature extraction, pattern recognition, etc. The extensive use of wavelet filters can be explained by its capability to provide indefinite number of basis functions [4, 5]. This pin points the importance of developing a fast and efficient architecture for wavelet FIR filtering. Due to recent advances in technology and decreasing costs, implementation of wavelet filters on field programmable gate array (FPGA) has been widely developed. The existing conventional architectures for wavelet FIR filters operate at comparatively low frequencies with respect to the proposed architecture thereby restricting its use in high frequency applications. Hence the new pipelined architecture for wavelet FIR filter is developed which considerably increases the operating frequency but at the cost of the number of FPGA resources utilized and output filter latency. The architectures have been implemented on FPGA using Xilinx System Generator for DSP and Virtex-5 FPGA development board. The rest of the paper is organized as follows. Section 2 presents the advantages of FPGA based implementation. Section 3 describes the methodology adopted. FPGA implementation is detailed in Sect. 4. Experimental results are discussed in Sect. 5. Finally, conclusion is given in Sect. 6.

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IJRIT International Journal of Research in Information Technology, Volume 2, Issue 3, March 2014, Pg: 349-354

2. Benefits of FPGA based implementation Several traditional computer hardware platforms can be considered for processing of signals which includes Microprocessor, Digital Signal Processor or an Application Specific Integrated Circuit (ASIC). Microprocessors and digital signal processors has the advantage of being easily programmed to perform verity of tasks, inexpensive and off-the-shelf devices but with low processing speed. On the other hand, an ASIC offers an advantage in terms of processing speed [6], but expensive to design and fabricate and inflexible once the design is complete. FPGA represent a new middle ground between microprocessors and ASICs in terms of cost and computational performance. Like microprocessors, FPGAs are off-the-shelf devices, inexpensive and easily reprogrammed for any new applications [6]. Like ASICs, FPGA offer high degree of control over the underlying computer hardware, allowing the system designer to specify hardware architecture developed for any application at hand, thus providing additional processing speed. The recent advances in FPGA technology have made FPGA preferable for implementation of all types of computational systems.

3. Method This section describes the conventional FIR filter architecture and it’s comparison with the proposed pipelined FIR filter architecture. There are two well-known canonical forms of implementation of FIR filters called the direct form and transposed form [7, 8]. Conventional and the proposed pipelined architecture implementation using either form are detailed below.

3.1 Conventional FIR filter architecture Figure 1 presents the conventional canonical implementation of a five tap FIR filter in direct and transposed forms which are functionally equivalent. Both forms suffer from important drawbacks in real world applications. It can be seen from the figure that direct form is limited by the critical path corresponding to the longest computation time among all zero delayed paths which is an increasing function of the number of taps. The critical path is illustrated by the dashed line in Fig. 1. It is necessary that the critical path should be less than a clock period. For direct form FIR filter, critical path      1  , where  and  are the time required for one multiplication and one addition respectively and N is the number of taps.

Fig. 1 Conventional canonical implementation of a five-tap FIR filter Leji C Koshy,

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IJRIT International Journal of Research in Information Technology, Volume 2, Issue 3, March 2014, Pg: 349-354

For transposed for FIR filter the critical path is reduced in to a single multiply-accumulate operation      by retiming delays in to the adder chain but at the cost of suffering from significant fan-in to apply the input signal simultaneously to all taps of the filter [7, 8].

3.2 Pipelined FIR filter architecture The proposed pipelined architecture reduces the critical path by inserting delays between the multipliers and adders of the circuit. However, this process increases the number of latches and the output latency in the system. Figure 2 presents the pipelined canonical realization of a five tap FIR filter in direct and transposed forms. Here we can see that in both forms the critical path is reduced to a single multiplication operation    . The inserted delays due to pipelining are presented by the shaded boxes. For pipelined direct form FIR filter the latency at the output of the FIR filter is an increasing function of the number of taps(latency=N) where as for pipelined transposed form FIR filter the latency is negligible and a constant(latency=2) irrespective of the number of taps of filter.

Fig. 2 Pipelined canonical implementation of a five-tap FIR filter

4. FPGA Implementation Both the conventional and pipelined architectures were implemented on FPGA using Xilinx System Generator (XSG) and Virtex-5 FPGA development board.XSG is a high level software development tool that allows the use of MATLAB/Simulink environment to create and verify hardware designs for Xilinx FPGA’s easily. It provides a library of Simulink blocks for accurate modeling of arithmetic and logic functions, DSP functions and memories.XSG includes a code generator that automatically generates HDL code of the developed model which can be synthesized and implemented on Xilinx FPGAs. The XSG blocks are similar to Simulink blocks but they can only operate in discrete time and fixed-point format [3]. Figure 3 presents the implementation of Daubechies2 decomposition low pass wavelet filter using conventional and proposed pipelined architectures on Xilinx System Generator in both direct and transposed forms. Daubechies2 filter is a 3rd order wavelet filter with four taps and four coefficient values. The coefficient values for Db2 decomposition wavelet filter is mentioned in Table 1. Table 1 Daubechies2 wavelet decomposition filter coefficient values Leji C Koshy,

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IJRIT International Journal of Research in Information Technology, Volume 2, Issue 3, March 2014, Pg: 349-354

Coefficients    

Conventional architecture of direct form Db2 filter

Values -0.1294095226 0.2241438680 0.8365163037 0.4829629131

Conventional architecture of transposed form Db2 filter

Pipelined architecture for direct form Db2 filter

Leji C Koshy,

IJRIT

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IJRIT International Journal of Research in Information Technology, Volume 2, Issue 3, March 2014, Pg: 349-354

Pipelined architecture for transposed form Db2 filter

Fig. 3 Implementation of conventional and pipelined architectures of Daubechies2 wavelet filter

5. Results & Discussion Timing and power analysis tool of Xilinx System Generator is used to calculate the resource utilization summary and the maximum operating frequency of the developed architectures. A noisy artificial signal from the workspace is used to evaluate the architectures as shown in Fig. 4. A fixed point data format of FIX18.14 (2’s complement signed 18- bit number having 14 fractional bits) is used for the evaluation. Resource utilization, maximum operating frequency and output filter latency for conventional and pipelined filter architectures is presented in Table 2.

Fig. 4 Evaluation of the filter architectures using Xilinx System Generator

Table 2 Resource utilization, maximum operating frequency and output latency for conventional and pipelined architectures of Db2 wavelet filter. Resource availability of Xilinx Virtex-5 XC5VLX50t FPGA are given in brackets. Architecture Conventional architectures Pipelined architectures Direct form

Transposed form

Direct form

Transposed form

Resource utilization Slice registers(28,800)

54

54

180

144

Slice LUTs(28,800)

1229

1229

1229

1229

Occupied Slices(7200)

343

330

355

355

LUT FF pairs(3741)

1239

1229

1247

1247

Bonded IOBs(480)

37

37

37

37

BUFGs(32)

1

1

1

1

104.232

232.654

340.326

342.466

0

0

4

2

Max. Ope. Freq(MHz) Latency

Leji C Koshy,

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IJRIT International Journal of Research in Information Technology, Volume 2, Issue 3, March 2014, Pg: 349-354

For pipelined architectures it can be seen that more resources are utilized compared to the conventional architectures but there is a considerable increase in the operating frequency. Also the output filter latency is increased for the proposed pipelined architectures which is minimum (latency=2) for transposed form filter over the direct form whose latency is an increasing function of the number of filter taps. The maximum operating frequency is approximately constant for pipelined architectures because the critical path is reduced to a single multiplication operation. Analyzing the above results, the pipelined transposed form FIR filter architecture which gives the highest operating frequency and minimal latency is considered as the best architecture for implementing an FIR filter on FPGA.

6. Conclusion A new architecture for high speed implementation of wavelet based FIR filter on FPGA was proposed and implemented. It was shown that the proposed pipelined architecture increases the operating frequency at the cost of number of resources utilized and the output latency. A fixed point data of only 18 bits is used which considerably decrease the FPGA resource utilization without affecting the filtering efficiency. Pipelined transposed form FIR filter architecture which gives the highest operating frequency and minimal latency is considered as the best architecture for implementing an FIR filter on FPGA.

References [1] S. Poornachandra, Wavelet based de-noise using subband dependent threshold for ECG signals, Elsevier J. Digit. Signal Process. 8 (2008) 49–55. [2] Y. Hel-Or, D. Shaked, A discriminative approach for wavelet denoising, IEEE Trans. Image Process. 17 (2008) 443–457. [3] Y. Ying, W. Yaseen, New threshold and shrinkage function for ECG signal denoising based on wavelet transform, in: Proceedings of the Bioinformatics and Biomedical Engineering (ICBBE) IEEE International Conference, 2009, pp. 1–4. [4] N. Ouarti, G. Peyré, Best basis denoising with non-stationary wavelet packets, in: Proceedings of Image Processing (ICIP) IEEE International Conference, 2009. [5] S.V. Vaseghi, Advance Digital Signal Processing and Noise Reduction, fourth ed., Wiley, United Kingdom, 2008. [6] J. Carletta, G. Giakos N. Patnekar, L. Fraiwan and F. Krach, Design of a field programmable gate array- based platform for real-time denoising of optical imaging signals using wavelet transforms , Elsevier, vol.36, 2004 289-296. [7] K. Azadet, C.J. Nicole, Low-power equalizer architectures for high-speed modems. IEEE Commun. Mag. 36(10), 118–126 (1998). [8] M. Bahoura, H. Ezzaidi, FPGA—implementation of parallel and sequential architectures for adaptive noise cancelation. Circ. Syst. Signal Process. 1–28. doi:10.1007/s00034-011-9310-0

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