Etch Proximity Correction through Machine-Learning-Driven Etch Bias Model Seongbo Shim†‡ and Youngsoo Shin† †

School of Electrical Engineering, KAIST, Daejeon 34101, Korea ‡ Samsung Electronics, Hwasung 18448, Korea

ABSTRACT Accurate prediction of etch bias has become more important as technology node shrinks. A simulation is not feasible solution in full chip level due to excessive runtime, so etch proximity correction (EPC) often relies on empirically obtained rules or models. However, simple rules alone cannot accurately correct various pattern shapes, and a few empirical parameters in model-based EPC is still not enough to achieve satisfactory OCV. We propose a new approach of etch bias modeling through machine learning (ML) technique. A segment of interest with its surroundings are characterized by some geometric and optical parameters, which are then submitted to an artificial neural network (ANN) that outputs predicted value of etch bias. The new etch bias model and EPC are implemented in commercial OPC tool and demonstrated using 20nm technology DRAM gate layer.

1. INTRODUCTION Etch process on a resist image may yield over-etched substrate due to lateral erosion of photo resist (Figure 1(a)) or under-etched substrate due to deposition (Figure 1(b)).1 This phenomenon is called etch proximity effect and the extent of over- or under-etch is called etch bias. As illustrated in Figure 2, a design layout should be modified through etch proximity correction (EPC) to compensate for etch bias before it is submitted to OPC and subsequent optical lithography. Etch bias is affected by the amount of etching particles (e.g. ions or radicals), which collide with substrate surface, and their incidence angle and direction.2 Accurate prediction of etch bias in full chip Ion and radical

Resist

Ion and radical

Resist

Etch Substrate

Etch Substrate

Positive etch bias

Negative etch bias (b)

(a)

Figure 1. Resist image with (a) a small space and etch result with negative etch bias and (b) a large space and etch result with positive etch bias. Advanced Etch Technology for Nanopatterning V, edited by Qinghuang Lin and Sebastian U. Engelmann, Proc. of SPIE Vol. 9782, 97820O · © 2016 SPIE · CCC code: 0277-786X/16/$18 · doi: 10.1117/12.2219057

Proc. of SPIE Vol. 9782 97820O-1 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/15/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

Design layout

Litho pattern layout

EPC

Mask image

OPC

Litho (resist) pattern

Lithography

Final etch pattern Design layout

Etch

Figure 2. Lithography process with EPC. Litho pattern layout

Interaction range (r1)

Point of interest

Interaction range (r2)

Point of interest

Point of interest Interaction range (r3)

(a)

(b)

(c)

Figure 3. Kernels for conventional empirical etch modeling: (a) density kernel, (b) visible kernel, and (c) blocked kernel.

level is computationally very expensive, so EPC often relies on empirically obtained rules or models. A rule-based EPC has been adapted for a few technology nodes, but simple rules alone cannot accurately correct various pattern shapes; it is expected that, in 10-nm technology, on-chip variation (OCV) is still 28% beyond the tolerance even though rule-based EPC is applied.3 In model-based EPC, etch bias is modeled as a function of a few empirical parameters: Etch bias = C0 + C1 Den + C2 Vis + C3 Blo + C4 Den2 + C5 Vis2 + ...,

(1)

where Den is a signal value of a density kernel (Figure. 3(a)), Vis is a signal value of a visible kernel (Figure. 3(b)), and Blo is a signal value of a blocked kernel (Figure. 3(c)); coefficients Ci s are determined through linear regression. In 20nm DRAM devices, it is expected that OCV is still 15% of gate size even though model-based EPC is applied.4 Our approach of new EPC is illustrated in Figure 4. A set of edge segments is identified from a litho pattern layout. For each segment, a number of geometric and optical parameters are extracted by examining nearby segments. These parameters become inputs of artificial neural network (ANN), which outputs predicted etch bias of the segment. ANN is trained for all segment involving its nearby segments so that their etch biases can be predicted as correctly as possible, and the resulting network is used as our etch bias model. The accuracy of our etch bias model is determined by the parameters that we choose and a set of test segments that are used for training. The parameters that we suggest are local pattern densities and

Proc. of SPIE Vol. 9782 97820O-2 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/15/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

Edge segment

Artificial neural network (ANN)

Litho pattern layout Parameter 1

Parameter 2

p1

p2

Predicted etch bias

Parameter 3

pn Segment of interest

Figure 4. The proposed EPC: each segment in a layout is parameterized, and ANN is established to predict etch bias from input parameters.

optical signal; the density represents the amount of etching particles, and the location where the density is measured is associated with incident angle and direction of the particles; optical signal is associated with a side wall angle of the photo resist, which also affects etch bias.1 To prepare comprehensive test segments, we extract segments from real test layouts; each segment is parameterized and identified as a point in n-dimensional parameter space; some close points are grouped as a cluster and a few representative points from each cluster are used as test segments. In this way, we maintain a small number of test segments, while they still represent a variety of segments in the space. The remainder of this paper is organized as follows. Details of new EPC are presented in Section 2, which include a systematic method of test segment preparation, description of the proposed parameters, ANN construction, and actual EPC. In Section 3, we demonstrate our EPC using a few test layouts of DRAM gate layer in 20nm technology. In Section 4, we summarize this paper.

2. A NEW ML-DRIVEN EPC 2.1 Test Segment Preparation Two types of patterns are considered to prepare test segments: traditional synthetic patterns and complex actual patterns. The traditional synthetic patterns include parametric patterns, e.g. the dense line and space (DLS), isolated line (Iso-line), and line-end to line-end (E2E) as shown in Figure 5(a). These patterns are easy to customize and good to see the trend of etch bias with respect to a specific geometry change, e.g. etch bias change with increasing space of DLS. We also consider complex patterns in real test layouts as shown in Figure 5(b). The test layouts may be prepared by shrinking some actual layouts produced with earlier technologies or synthesizing designs from a preliminary version of the new technology library. Each segment in the test layouts is represented by n such parameters such as local pattern densities and optical signals, and mapped to corresponding point in n-dimensional parameter space. Some close points are then grouped as a

Proc. of SPIE Vol. 9782 97820O-3 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/15/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

...

CD measurement position

Segment of interest

Test layouts p1

DLS

DLS

Representative segment

Iso-line

Segment cluster

...

p2 pn E2E

E2E (b)

(a)

Figure 5. Test segment preparation: (a) test segments in traditional synthetic patterns and (b) representative segments after classifying segments extracted from test layouts.

cluster through K-mean method.5 A few representative points from each cluster are picked, and their corresponding segments will be used as test segments for constructing our etch bias model.

2.2 Parameter Extraction Two parameter types are chosen for characterizing a test segment and its surroundings. The first parameter is a local pattern density, which is measured at some position around a segment of interest. As shown in Figure 6(a), we place a few concentric circles, whose centers coincide with the center of the segment, and draw a few lines passing the center of the segment. At each point where the circles and lines intersect (measurement point), we measure pattern density within some circular region (region of density measurement). The number of parameters is determined by the numbers of concentric circles and lines that we use. A local density value and its measurement position are associated with the amount of etching particles and their incident angle and direction. To take account of side wall angle of resist, we choose optical kernel signal as the second parameter tyepe, which is given by X φi = L(x, y)Ψi (x, y), (2) ∀(x,y)

where L is a pixelated layout image, in which pixel value is 1 if the pixel is within a layout polygon, and 0 otherwise; Ψi is the i-th optical kernel function, whose center and the center of an interesting segment coincide as shown Figure 6(b). We obtain a few optical kernel signals using different optical kernel functions, some of which are shown in Figure 7; a set of basis functions of polar Fourier transform6 or a set of eigen functions in the sum of coherent systems (SOCS)7 can be used as optical kernel functions. The signals reflect constructive or destructive interference of lights at the center of the segment, and thus are associated with the vertical shape of the resist, which affects etch bias,1

Proc. of SPIE Vol. 9782 97820O-4 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/15/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

Region of densify measurement

Optical kernel function

Measurement point Litho pattern layout d1

d12 d24

d2

d13

Segment of interest

d14

Segment of interest

(a)

(b)

Figure 6. Parameterization of a pattern: (a) local pattern densities and (b) radial distances.

... 1

2

3

4

5

n

Figure 7. Basis functions of polar Fourier transform as optical kernels.

2.3 ANN Construction We employ an artificial neural network (ANN) as our etch bias model. ANN is a model inspired by biological neural network, which consists of neurons and synapses. Accordingly, ANN consists of nodes and edges, which respectively correspond to neurons and synapses, as shown in Figure 8. N input nodes receive N parameters from an interesting segment. An input node propagates its input signal to every hidden node in the first hidden layer via edges; each edge has weight value, which is multiplied with a propagated signal. Multiple (weighted) signals that are received by each hidden node are summed, and if the sum is larger than some threshold, the hidden node outputs 1 and 0 otherwise. The thresholding is often realized by using a sigmoid function, which outputs a floating value in between 0 and 1. A node in the first hidden layer then propagates the output value to every node in the next layer in the same manner, and this process is repeated until an output node is reached. The output node then returns a predicted etch bias of the input segment. We evaluate ANN for all test segments, and optimize the individual edge weight and threshold values so that the difference between the predicted etch bias and actual etch bias can be minimized. The resulting ANN is used as our etch bias model. Prediction accuracy is affected by ANN complexity. If ANN is too simple and consists of small numbers of nodes and layers, it cannot be successfully trained. On the other hand, too complex ANN may be trained to be overly specific for test segments, which causes over-fitting; in other words, ANN now cannot successfully handle new segments not considered during ANN training. We adjust the

Proc. of SPIE Vol. 9782 97820O-5 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/15/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

Parameter 1

Parameter 2 Predicted etch bias

Parameter N

N input parameters

Hidden layers and nodes

1 output node

Figure 8. ANN network.

numbers of nodes and layers through 5-fold cross-validation. The set of test segments is randomly divided into 5 subsets of equal size; 4 of these sets are used to construct an ANN while the remaining set is used to assess the proportion of correctly predicted etch biases. The accuracy is averaged over 5 iterations. Once an ANN is constructed for test segments, it is used for EPC of a litho pattern layout. A set of parameters is extracted from each segment in the layout, and submitted to the ANN, which then outputs predicted etch bias of the segment. After repeating this for all segments, each segment moves inward or outward following the amount of its predicted etch bias, which yields a predicted etch pattern.

2.4 EPC Algorithm EPC is to find a litho pattern layout that is expected to produce the desired etch pattern, as shown Figure 2. EPC cannot be performed in analytical fashion since no analytical function exist to model etch proximity effect, so we have to rely on trial-and-errors. Our EPC algorithm is shown in Figure 9. It receives a design layout (Din ), which is used as an initial litho pattern layout L (L1), and output is an ideal litho pattern layout (Lout ) that is expected to produce desired etch pattern. Our goal is to modify L so that its expected etch pattern (D) is similar to the desired etch pattern Din as much as possible; this is achieved through iteration (L2-L7). Each segment of the litho pattern layout is parameterized and inputted to ANN, which returns a set of expected etch biases for all the segments (L3). We move each edge of L following the expected etch bias, which yields expected etch pattern D (L4), as shown in Figure 10(b). The expected etch pattern is then compared with a design layout; the difference between them is modeled by edge placement error (EPE), which is a distance between edges of Din and D as shown in Figure 10(c). We measure EPE at center of every segment of Din (L5). New L is constructed by adjusting position of each segment of the current L in the opposite direction of EPE with size of k · EP E, where k is user-defined coefficient

Proc. of SPIE Vol. 9782 97820O-6 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/15/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

Input: A design layout Din Output: An ideal litho pattern layout Lout L1: L ← Din L2: repeat for max iterations L3: A set of biases ← AN N (a set of segments from L) L4: D ← ET CH(L, a set of biases) L5: A set of EPEs ← M easure EP E(Din , D) L6: if EP Emax ≤  then Exit loop L7: L ← CORRECT (L, −k · a set of EPEs) L8: return Lout ← L Figure 9. EPC algorithm.

Litho pattern layout ( L )

Etch bias

Expected etch pattern (D )

Design layout (D in )

EPE

D

L

(a)

(b)

(c)

Figure 10. (a) Current litho pattern layout (L), (b) expected etch pattern (D), and (c) EPE measured between the expected etch pattern (D) with a design layout (Din ).

for better convergence (L7). If the largest EPE does not exceed a certain threshold (EP Emax ≤ ), iteration stops; otherwise iteration continues until user defined maximum iteration counts are reached.

3. EXPERIMENTS Our EPC was implemented using Proteus9 for parameter extraction and Python for constructing ANN. We extracted 1000 segments from synthetic- as well as actual-layouts and used them for ANN training; another 600 segments were also extracted from layouts and used for actual EPC. A segment is represented by 34 parameters: 24 local densities and 10 optical kernel signals. Our ANN consists of 34 input nodes, three hidden layers ( each of which contains 10 hidden nodes), and one output node. For assessment of our EPC, we implemented rule-based (RB) and model-based (MB) EPCs. Rules were composed of 28 steps of pattern space and 20 steps of pattern width, which together yield 560 combinations, each of which is associated with one etch bias value. Two versions of MB-EPC were implemented: MB-2nd is constructed using up to 2nd order terms (e.g. Vis2 in (1)); MB-3rd, in addition, includes 3rd order term (e.g. Vis3 ). The size of each kernel and coefficients are determined

Proc. of SPIE Vol. 9782 97820O-7 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/15/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

6.5

6.9

Training segment Test segment

RMSE of etch bias [nm]

9.8

RB

3.5 1.9

2.2 1.1

MB-2nd

MB-3rd

1.5 1.7

New

Figure 11. RMSE of etch bias for training (white) and test (shaded) patterns.

through linear regression using Progen.8 Rule and empirical model are also constructed for the same 1000 training segments.

3.1 Accuracy of New Etch Bias Model Root mean square errors (RMSE) for the 1000 training segments were compared (white bars in Figure 11). RB method shows very large RMSE, indicating that using a few simple rules are not enough to represent complex pattern shapes. In MB method, RMSE decreases as more higher order terms are used. Our new model shows 1.5nm RMSE, which places in between MB-2nd (1.9nm) and MB-3rd (1.1nm). RMSE for other 600 test segments that are not used in model training is also compared (shaded bars). RMSE of RB significantly increases because of its bad coverage of complex patterns. In MB-2nd, RMSE only slightly increases, but MB-3rd shows almost 3 times larger RMSE because the empirical kernels cannot physically reflect etching phenomena, which may cause overfitting if too many unnecessary terms are involved in model training. Our new model still shows very small RMSE in spite of large number of parameters, since each of our parameters is associated with physical phenomenon of each bias, e.g. amount of etching particles, incident direction and angles, and optical property.

3.2 Assessment of New EPC over MB-EPC We compared our new EPC and MB-2nd in variation of critical dimension (CD); MB-2nd is used for etch bias prediction in L3 of Figure 9. MB-EPC was applied to 2X-DRAM gate layer, and gate CD was measured in core and peripheral region. Distribution of CD errors is shown as shaded boxes in Figure 12, in which 3-sigma is 8.7% of target CD value. The same experiment was performed using new EPC, and corresponding CD error distribution is shown as dark circles; 3-sigma of the distribution is reduced by 2.4%. Narrower CD distribution implies larger sensing margin due to more uniform VTH of sense amplifier transistors, which reduces power consumption and improves device speed. New EPC requires about 8 times more runtime because we extract many local densities around every interesting segment. We expect that runtime can significantly be improved if commercial tools are optimized in measuring local densities. Note that our method is currently implemented on top of Proteus using a few user-assessable functions, so is inherently very slow.

Proc. of SPIE Vol. 9782 97820O-8 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/15/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

MB-EPC (3σ = 8.7%)

35

New EPC (3σ = 6.3%)

Percentage [%]

30 25 20 15 10 5 0

-10

-5

0

5

10

CD error [%]

Figure 12. Histogram of CD errors on a wafer after MB-EPC and new-EPC.

4. SUMMARY Machine-learning technique has been applied to etch bias model for the first time. Two key components of our method are parameterization of a segment and preparation of test segments. Local density distribution and optical kernel signals have been proposed as parameters due to their physical implications on etch bias. Test segments have been systematically prepared to keep the number of segments small while ensuring enough covering of pattern shapes. Artificial neural network (ANN) has been employed for constructing etch bias model, in which cross validation has been performed to avoid overfitting issue. We have demonstrated our EPC using 20-nm DRAM gate layer. Experiments have shown that our method yields smaller RMSE of predicted etch bias and smaller OCV of gate CD compared to conventional RB- and MB-EPCs.

ACKNOWLEDGMENTS The authors would like to thank Mr. Junghoe Choi and Mr. Munhoe Do from Synopsys Korea for technical support. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2015R1A2A2A01008037).

REFERENCES 1. C. Wu, W. Yang, L. Luan, and H. Song, “Photoresist 3D profile related etch process simulation and its application to full chip etch compact modeling,” in Proc. SPIE Advanced Lithography, Mar. 2015, pp. 1–8. 2. Y. Granik, “Correction for etch proximity: new models and applications,” in Proc. SPIE Advanced Lithography, Mar. 2001, pp. 98–112. 3. M. Salama and A. Hamouda, “Efficient etch bias compensation techniques for accurate on-wafer patterning,” in Proc. SPIE Advanced Lithography, Mar. 2015, pp. 1–7. 4. J. Park, S. Kim, S. Shim, S. Suh, and H. Oh, “The effective etch process proximity correction methodology for improving on chip cd variation on 20 nm node DRAM gate,” in Proc. SPIE Advanced Lithography, Mar. 2011, pp. 1–10. 5. J. B. MacQueen, “Some methods for classification and analysis of multivariate observations,” in Proc. Fifth Berkeley Symp. on Mathematical Statistics and Probability, vol. 1, Dec. 1967, pp. 281–297.

Proc. of SPIE Vol. 9782 97820O-9 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/15/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

6. D. Frejlichowski, “A three-dimensional shape description algorithm based on polar-fourier transform for 3D model retrieval,” in Image Analysis. Springer, 2011, pp. 457–466. 7. N. Cobb, “Fast optical and process proximity correction algorithms for integrated circuit manufacturing,” Ph.D. dissertation, Univ. California at Berkeley, Oct. 1998. 8. Synopsys, “Progen,” Dec. 2013. 9. ——, “Proteus,” Dec. 2013.

Proc. of SPIE Vol. 9782 97820O-10 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/15/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx