IV Semester M.Sc. Degree Examination, July 2013 Electronic Science EL 402 : EMBEDDED SYSTEM DESIGN Time : 3 Hours
Max. Marks : 80
Instructions : 1) Answer all questions from Section A. 2) Answer any four full questions from Section B. SECTION – A 1. What is ASIP ? Explain any one ASIP.
(5×4=20)
2. Briefly discuss any one application of PWM. 3. Briefly explain subtraction instructions of PIC microcontroller. 4. Write a note on stack register and stack memory of PIC16F877A. 5. Briefly explain function queue scheduling architecture. Mention its advantageous over other architectures. SECTION – B 6. a) Define power, performance, unit cost and flexibility design metrics. b) Distinguish between general purpose processor, single purpose processor and ASIP. 7. a) With suitable example, explain optimization of FSMD and datapath. b) Briefly explain Instruction Set simulator (ISS) and Emulator.
6 9 8 7
8. a) Explain : i) Interrupt driven I/O data transfer ii) Multilevel bus architecture. b) With relevant block diagram and SFR explain TIMER1 of PIC 16F877.
(5+3) 7
P.T.O.
*PG520*
PG – 520 9. a) Explain the following pins of PIC16F877A
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i) RB7/PGD ii) RC6/Tx/CK iii) RA1/AN1 iv) MCLR. b) Explain the function of scheduler in RTOS.
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c) Define critical section of the program.
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10. a) Discuss various problems w.r.t. improper usage of semaphores.
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b) Briefly explain : i) Mailboxes ii) Interrupt latency iii) Advantageous of using more number of tasks in RTOS based embedded system. (3+3+4) 11. Write a note on any three of the following : a) RT-level sequential components. b) Synchronous and asynchronous events. c) TRIS registers of PIC microcontroller. d) Selection of software architecture.
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Sign in. Page. 1. /. 2. Loading⦠Page 1 of 2. ARM MICROCONTROLLER & EMBEDDED SYSTEM. B.E., VI Semester, Telecommunication Engineering [CBCS scheme]. Subject Code 15EC62 IA Marks 20. Number of Lecture 04 Exam Marks 80. Hours/Week. Total Number of 50
b) Briefly explain Concept phase, Design phase and Programming phase of. software life cycle. 7. 11. Write a note on any three of the following : (5Ã3=15).
In Electronic design automation EDA HLS denotes the systematic ... abstraction levels Each new abstraction layer aims at hiding design complexity which .... computation models, controls systems, chip technologies, and modern design tools.
and software. Choice of system components depends upon optimality of. - Implementation of function. - Analysis of alternatives in both hardware and software domains. Specification of flexible hardware- ... These systems are integration of subsystems
