EE241 Midterm Report Offset Compensation Techniques for Sense Amplifiers in Digital Circuits Yida Duan, George Shaw Abstract - Increased process and supply voltage variations in deep submicron technologies have great impact on sense amplifier speed by increasing its worst-case offset. Offset compensation techniques have emerged to become the most promising solution to deal with the offset problem. In this paper, several published offset-compensation techniques as well as some conventional sense-amplifier structures are investigated and compared. New offset compensated sense amplifier structures are proposed.

1. Introduction The function of a sense amplifier is to compare its input signal to a reference threshold voltage and supply an output voltage of zero or VDD based on the comparison. The difference between the input signal and reference is usually very small. These circuits are classified into two types: Highgain open-loop amplifiers, and latch-based (regenerative) amplifiers. The latch-based sense amplifier is usually chosen in digital circuits due to its speed advantage, and for this paper, we focus on the latch-based sense amplifier class only. Ideal sense amplifiers always return correct comparison results no matter how close the input signal is to the threshold, but, in reality, sense amplifiers have an uncertain offset- voltage or current due to device mismatches. If the difference between the input signal and reference is within this uncertain offset range, then the output of the sense amplifier may be incorrect. This offset can be reduced by increasing device size, but it costs more in both power and area.

The conventional method to avoid offset error in digital circuits is to delay the triggering of the sense amplifier until its input signal level has grown larger than the worst case offset. This approach suffers from a speed loss through the introduced timing delay, especially in the case that the input of the sense amplifier is a slowly changing signal (e.g. SRAM). An alternative solution is to cancel this uncertain offset through clever circuit design. There are three common offsetcompensation techniques in integrated circuits: varying load resistance, varying load capacitance, and storing the offset on capacitors (auto zero approach).The first two approaches require large circuit overhead for tuning the resistance or capacitance and therefore are unattractive in digital circuits. In contrast, the auto-zero approach requires at most two additional capacitors and has the ability to cancel the offset on every evaluation cycle. The auto -zero approach is therefore the solution of choice in digital circuits. In following sections, we present the advantages and drawbacks of the conventional voltage-mode sense amplifier (CVS), clamped bitline current-mode sense amplifier (CBLSA) [1], offset-compensated non-strobe regenerative sense-amplifier (NSR-SA) [2], as well as the offset compensated differential comparator (OCDC) [3]. At the end, we propose two new sense amplifier structures, the offset-compensated voltage-mode sense amplifier (OCVSA) and offset-compensated current-mode sense amplifier (OCCSA).

2. Analysis (1) Conventional voltage-mode sense amplifier (CSA)

M7 and M8 during the regeneration phase. Large bit-line capacitors directly load the regeneration devices, M1 and M2, which slow the regeneration speed. Also, one of the bit-lines is always completely discharged at the end of read cycle, which wastes energy unnecessarily in the case of successive read operations. (2) Clamped bit-line current-mode sense amplifier (CBLSA)

The conventional voltage-mode sense amplifier (CSA), shown in Figure 1, operates in two phases. In reset phase, “Pch” is low, “Ysel” is high, and “SAEN” is low. The sense amplifier is disconnected from the bit-lines through M7 and M8, the regeneration loop is shut down by disconnecting it from supply through M10, and the crossed-coupled inverter is forced to its metastable point by pre-charging Q and Qbar to VDD. In the sensing phase, “Pch” is high, disconnecting regeneration nodes Q and Qbar from VDD; “Ysel” is low, connecting the sense amplifier input to the bit-lines; and “SAEN” is high, establishing a power supply connection to the sense amp. The advantage of the CSA is low-transistor count and no static power consumption during the reset phase. However, there are two main disadvantages of the CSA that make it unattractive in deep sub-micron technologies. First, any mismatch between M1 and M2 (device dimensions or Vt variations) give rise to an offset voltage. To avoid this, triggering of the CVS has to be delayed until differential input voltage exceeds this offset voltage. This is represented by a delay of “SAEN”, ∆t, in the timing diagram. Second, the input and output nodes of the sense amplifier are shorted by

The clamped bit-line current mode sense amplifier (CBLSA) is an improved version of the CSA and operates similar to the CSA. In reset phase, “Ysel” is high, disconnecting the sense amp input from the bit-lines; and “SAEN” is low, setting the cross-coupled inverter to its meta-stable point by forcing output voltages equal. At the beginning of sensing phase, “Ysel” is low while “SAEN” is still low, connecting the sense amp inputs to the bit-lines. Since M7 initially shorts the two input nodes, an input -differential current ∆I = Ip − In , flows through M7. “SAEN” rises and the connection through M7 opens when ∆I is greater than input offset current and enables regeneration. The initial differential current that flows in M7 splits between M3 and M4, causing outputs to regenerate to the correct values. The CBLSA has several advantages over the CSA. First, the CBLs are connected to a lowimpedance node, the sources of M3 and M4, which do not load the cross-coupled inverter. The

regeneration speed is only determined by load capacitance at Out and Out . Second, M5 and M6 clamp the bit-line to a relatively high voltage at the end of the read operation. The bit-lines are only slightly discharged at the end of read operation, which saves energy in the case of successive read operations. There are, however, several drawbacks for the CBLSA. First, static current is drawn from the supply during the reset phase. Second, the circuit area is larger than the CSA due to increased circuit complexity, and third, the offset problem due to mismatch is not improved and is likely worse than the CSA as there are now six devices, M1 to M6, that contribute to offset rather than the two devices in the CSA. Triggering of the CBLSA thus has to be delayed longer than that required for the CSA. (3) Non-strobed regenerative sense amplifier (NSRSA)

The operation of the non-strobed regenerative sense amplifier (NSR-SA) is quite different from the previous two sense amplifiers. It is a single-ended amplifier that responds only to a falling input signal. In reset phase, “reset” is high and the input and output of the two inverters are shorted together. The voltages at X and Y are defined by the beta ratios of the inverters. Any voltage difference between X and Y caused by

mismatch between M1/M3, M2/M4 are stored on C1/C2. This ensures VX and VY are set to the metastable point at the end of reset phase. During sensing phase, the input voltage is coupled into the sense amplifier through C1. The two capacitors serve as floating voltage sources with the charge voltage stored equal to the offsets. If the input equals VDD, the sense amplifier stays at its metastable point and nothing will change. If the input starts to fall from VDD, VX will rise above the metastable point, causing VY to fall below the metastable point. When VX − VY = Vt then M5 is turned on and the regeneration loop is enabled. The nominal input referred offset can be approximated from the small signal model as: VOS = Vt /[( gm, n + gm, p )ro, n || ro , p ] 2 , where gm, ro refer to the transconductance and output resistance of M1 to M4. In deep submicron technology, the value of the denominator is roughly 3 2 ≈ 10 . If the threshold voltage is 230mV, then VOS ≈ 23mV . To avoid false regeneration caused by charge injection from switch S1 or S2, PMOS is used for S1, and NMOS is used for S2 [3]. However, this raises the voltage at the gate of the first inverter at the beginning of sensing phase, therefore, effectively increasing the offset voltage. It is worth mentioning that although the offset voltage slows down the speed of the sense amplifier, it decreases probability of false regeneration. There are several advantages of the NSR-SA. First, explicit compensation reduces worst-case offset compared to the CSA, and, therefore, increases the access speed. Second, NSR-SA has a simple timing scheme. It is triggered at the same time that WL rises; no delay needs to be inserted. The speed penalty caused by delay uncertainty associated with the SAEN delay is thus eliminated. The drawbacks for NSR-SA are several, however. The bit-line capacitance at the input loads the output node Y, which decreases regeneration speed. Second, the reduced offset that occurs from compensation is counteracted by the threshold variation of M5 and charge injection of S1 and S2 (> 30mV). The regeneration is inactive before the input passes the offset voltage. Lastly, the singleended sensing scheme worsens noise immunity of the NSR-SA. Any digital noise at the bit-line may

cause a false regeneration, whereas with the CSA, most noise coupled to the bit-line appears to be common mode and is rejected by the differential CSA. Since a larger offset increases the noise margin, the authors shows a very steep trade-off between noise rejection and delay [2] (large noise rejection can be achievable with very little speed penalty). However, the sense amp offset is set by Vt, channel charge of S1 and S2, and loop gain. Thus, transistor dimensions have to be changed to vary offset in reality, which greatly affects speed, area, and power. (4) Offset compensated differential comparator (OCDC)

stops flowing when Vgs1 = Vt1 , Vgs 2 = Vt 2 , and the difference of the two threshold voltages, Vt 2 − Vt1 is stored on C1 and C2. During voltage capture phase, both M5 and M6 are off, which disables the regeneration loop. The bit-lines connections are closed and input differential signals are sampled at the drains of M1 and M2. During comparison phase, M5 and M6 are on, enabling the regeneration loop; and the bit-lines are disconnected from the sense amp to avoid loading by bit-line capacitance. The advantage of OCDC is its extremely small offset. An offset as low as 1mV is reported in [3]. The drawback of this approach is that only the threshold voltage variations of M1 and M2 are cancelled, while the variations in dimensions are not. Thus, aggressive sizing is require to achieve low offset, with areas of 30mm2 used in [3]. In addition, two clock phases are required to cancel the offset before every read operation. Therefore, due to its large area and extra phase for offset compensation, this approach is attractive only in applications where few sense amplifiers are require and a large number of consecutive read operations occur at once (e.g. flash memory). (5) Offset compensated voltage-mode sense amplifier (OCVSA)

The offset compensated differential comparator (OCDC) is a multi-phase sense amplifier. Prior to read operations, a two-phase offset cancellation must be performed. During pre-charge phase, M6 is on; M5 is off; the bit-lines are disconnected from the inputs of sense amp; and M1 and M2 are diode connected. The drain of M6 is charge up to VDD, while drains of M1 and M2 are charge up to roughly VDD − | Vt , p | . During the offsetnulling phase, M6 is off; M5 is on; and M1 and M2 are still diode connected. Charges stored on the gate of C1 and C2 and gates of M1 to M4 start to flow through M1 and M2 to ground. The current

The offset-compensated voltage-mode sense amplifier (OCVSA) is modified version of the CSA. Offsets caused by M1 to M4 are stored on C1 and C2 during reset phase. Additional transistors, M5 and M6, are inserted to disconnect the bit-lines

from the inputs during reset phase of M1 to M4. Ysel is pulsed, and a small differential input voltage is sampled on small capacitors Cs1 and Cs2. Bit-line capacitors are cut off from regeneration node during sensing phase. One potential problem with this approach is the difficulty to generate a short pulse for Ysel. A longer than needed pulse width will slow down the speed. The falling edge of the reset signal has to be delayed until enough (albeit small) input differential voltage is built up. (6) Offset-compensated current mode sense amplifier (OCCSA)

through device dimensions and capacitor size. The results will be compared and studied.

4. Conclusion Several offset compensated sense amplifiers as well as some conventional sense amplifiers are investigated. According to the preliminary examination, CSA is likely to be the slowest of all sense amps; CBLCSA appears to be faster than CSA, with slightly more power and area; NSR-SA is faster than CSA with minimal power and area penalty, however, whether it is faster than CBLCSA is not clear without more rigorous analysis and simulation; OCDC has the smallest offset voltage but is not suitable for random access memory and low swing logic application. The proposed sense amplifier, OCVSA and OCCSA seems to be the most promising solutions so far. Each one of the two has its own advantage over the other. However, more rigorous analysis and simulation are needed to reveal its benefits and limitations.

References [1] Travis N. Blalock, Richard C. Jaeger, “A high-speed clamped bit-line current-mode sense amplifier”, IEEE Journal of Solid-State Circuits, Vol.26, No. 4, April 1991 [2] Naveen Verma, Anantha P. Chandrakasan, “A highdensity 45nm SRAM using small-signal non-strobed regenerative sensing”, ISSCC 2008 [3] Jonny Javanifard, etl. “A 45nm self-aligned process 1Gb NOR flash with 5MB/s program speed”, ISSCC 2008

The offset-compensated current-mode sense amplifier (OCCSA) works exactly the same as CBLCSA, except the offsets for M1 to M4 are cancelled by compensation. The timing diagrams are exactly the same as CBLCSA except the delay of the SAEN signal, ∆t, now is much shorter. Note that the offset caused by a mismatch between M5 and M6 is not cancelled. The advantage of this approach comparing to OCVSA is relatively simple timing. No short pulse needs to be generated.

3. Future Work Sense amplifiers presented in this paper as well as proposed solution will be implemented using ASU 45nm LK PTM. Offset, speed, and power of each sense amplifier will be extracted from simulation. The total area will be estimated