USO0RE41959E
(19) United States (12) Reissued Patent
(10) Patent Number: US RE41,959 E (45) Date of Reissued Patent: *Nov. 23, 2010
Suzuki et a]. (54)
(56)
VARIABLE ADDRESS LENGTH COMPILER
References Cited
AND PROCESSOR IMPROVED IN ADDRESS MANAGEMENT
U.S. PATENT DOCUMENTS 4,296,469 A 4,301,514 A
(75) Inventors: Masato Suzuki, Osaka (JP); Hiroshi
Kamiyama, Kyoto (JP); Shinya Miyaji,
10/1981 Gunter et al. 11/1981 Eifuku et al.
(Continued)
Nara (JP)
FOREIGN PATENT DOCUMENTS
(73) Assignee: Panasonic Corporation, Osaka (JP) Notice:
.
.
.
.
EP
7/1985 10/1985
148478 A 0180077
.
This patent 1s 511131601 to a termmal d1s
(Continued)
claimer.
OTHER PUBLICATIONS
Panasonic; Microcomputer Family AM Series; Original
(21) Appl. No.: 09/662,484 Sep. 14, 2000 (22) Filed:
Microcomputer With C Language Oriented Architecture; pp. 1421; 2000. *
European Search Report issued in European Patent Applica tion No. EP 02 076 02524224, dated Sep. 22, 2009.
Related US. Patent Documents
(Continued)
Reissue of:
(64)
Patent No.:
Appl. No.:
5,809,306 Sep. 15, 1998 08/587,338
Filed:
Jan. 16, 1996
Issued:
Primary ExamineriKenneth R Coulter (74) Attorney, Agent, or FirmiMcDermott Will & Emery LLP
(57)
US. Applications: (63)
The present invention discloses a program converting unit
Continuation of application No. 08/249,157, ?led on May
for generating a machine language instruction from a source program for a processor that manages an N-bit address While
26, 1994, now abandoned.
(30)
May 27’ 1993 Oct. 1, 1993
(51)
(52)
processor that runs the converted program. The program
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(JP)
Converting
5426212
’
a
parameter
for
user; the data Width representing the number of bits of data
712/210_ 717/143_ 717/154_ ' """"""""""" "
Comprising:
used in the source program While the pointer Width repre senting the number of bits of an address; and a generating unit for generating an instruction to manage the data Width When a variable operated by the instruction represents the
(200601)
U 5 Cl
unit
holding a data Width and a pointer Width designated by a
(JP) ........................................... .. 5-247154
Int_ CL G06F 9/45
' '
(58)
processing M-bit data, N being greater than M, and such a
Foreign Application Priority Data
May 31,
ABSTRACT
’ 717/140’
data, and for generating an instruction to manage the pointer
_ _ _ Field of Classi?cation Search ................ .. 712/210;
Width When a variable operated by the instruction represents the address_
717/140,143,154 See application ?le for complete search history.
9 Claims, 26 Drawing Sheets
TO REGISTER UNIT 137
/138 EXECUTING UNIT
24)
24)
141 FM
DECODING
UNIT 140
ALU
TO DECODING UNIT
psw
T /143
’ I
142
FM
DECODING{ UNIT 14o
BRANCH
144
JUDGING
8
UNIT
AEIggNDER 2,“ '6
' SECOND /,/145 j EXTENDER f
glécoomo
UNIT 140
US RE41,959 E Page 2
4,314,332 4,347,566 4,361,868 4,447,879 4,453,212
US. PATENT DOCUMENTS
JP JP
A A A A A
JP JP JP WO
2/1982 8/1982 11/1982 5/1984 6/1984
Shiraogawaet a1. Kodaet 31. Kaplinsky F9118 Gaitheretal.
4,602,330 A
7/1986 Ikeya
4,679,140
7/1987
A
4,739,471 A 4,763,255 A 5,072,418 A 5,077,659 A
3-74725 3248240
3/ 1991 11/1991
04_014144 04_172533 05_046383 WO9215943
H1992 6/1992 2/1993 9/1992
OTHER PUBLICATIONS
Gotouetal.
_
4/1988 Baumetal‘ 8/1933 Hopkins et 31,
_
_
_
Aho, A.V. et al., “Compile Pr1nc1p1es, Techn1ques and Tools”, Nikkei Science Inc., Nov. 10, 1990, pp. 399-400,
* 12/1991 Boutaud et a1. ........... .. 708/207 12/1991 Nagata
With English Translation. Hennessy et al., Computer Architecture . . . , 1990 pp.
5,307,492 A
4/1994 Benson
9(H13 and1392161~
5,420,992 A
5/1995 Kllhan et _a1'
Sebesta, Concepts of Programming Languages, 1989 pp.
5,488,710 A
5,568,630 A
RE40,498 E
* *
1/1996
Matsuzak1eta1. Sato et a1. ................. .. 711/125 . .
10/1996 Kllllan et a1.
712/200
* 9/2008 Suzuki etal.
717/143
2008/0320454 A1 * 12/2008
Suzuki et a1. ............. .. 717/143
FOREIGN PATENT DOCUMENTS 0 170 284 0503514 0 528 695 B1 55-43680 55-72255 55-118153 57-161943 57-105038 61-084735 62-259140 01-169537 64-91236
5/1986 3/1992 2/1993 3/1980 5/1980 9/1980 5/1982 6/1982 4/1986 11/1987 7/1989 10/1989
’ and ’ i Harman et al., The Motorola MC.68000 . . . , 1985 pp.
3931’ 52753’ 84789’ 1347137’ 1427159’ 1747177 & 2007203
“Address SiZe Independence in a 16-Bit Minicomputer”, by Philip E. Stanley, the 5th Annual Symposium on Computer
Architecture, Apr. 1978. “High-Performance Simgle-Chip Microcontroller H8/300 Series, by Nobuo Shibasaki et a1., Hitachi Review, V01. 40 (1991), No. 1. XP4)02114028, IBM Technical Disclosure Bulletin, V01. 16, No. 3, Aug. 1973.
High-Performance Single-Chip Microcontroller H8/300 Series Hitachi Review, V01. 40, pp. 23-28, (1991). XP4)02141401, Address SiZe Independence in a 16-bit
minicomputer, Phillip E. Stanley pp. 152-157, Apr. 1978. * cited by examiner
US. Patent
Nov. 23, 2010
Sheet 1 0f 26
FIG. 1 12
J
US RE41,959 E
PRIOR ART
16
J 11
INSTRUCTION DECODING
REGISTER UNIT
UNIT
v ,
14
EXTERNAL-ACCESS
EXECUTING UNIT
EXTERNAL STORAGE UNIT
FIG_ 2
OP
PRIOR ART
SIZE" SRC MOVE 32bit
vDEST A1 @ A2
13
US. Patent
Nov. 23, 2010
Sheet 2 0f 26
FIG. 3
US RE41,959 E
PRIOR ART
INSTRUCTION
/34 INSTRUCTION DECODING UNIT
IMMEDIATE DATA
/31 ‘
V
DATA REGISTERS DO~D7 |——>
[/32 ADDRESS REGISTERS AO~A7 |->
, SIGN I EXTENDER
33
r’
V
V S’
CALCULATOR
US. Patent
Nov. 23, 2010
Sheet 3 0f 26
FIG. 4A A
PRIOR ART
32-BIT
V
FIG_ 4B A
US RE41,959 E
PRIOR ART
32-BIT
V
16-BIT
O
lU --- ~llll
lm
O
O
I
V
I
I
*
11414 |
|
US. Patent
Nov. 23, 2010
Sheet 4 0f 26
US RE41,959 E
@ 3 E . 8 Q 5 6 L 0 I % 5 i 5 d o s < l $ | i H>O TIMovN
HI'l
@I 3|! @vl
Icnow©vdlgO
< 1 E m § mi8.3 $35082mg E0d3<© 8.5Ea<‘ 35.285 3g.8m5% ><0qm2
>4m0m2g:
US. Patent
Nov. 23, 2010
Sheet 5 0f 26
US RE41,959 E
FIG. 6 PRIOR ART
DO—DO "* DO
(1)
I IMMEDIATE DATA H8000 —» A0 ‘A’ (2)
IDATA IN ADDRESS DESIGNATED BY A0 —» D1 F6)
I
Dl+D0 —» D1
|'\/(4)
I IMMEDIATE H0010 + A0 —» A0 F45) COMPARE AO WITH IMMEDIATE DATA H8100
A0 < H8100
W N‘’ I STORE D0 AT ADDRESS H1000OOOO r48)
(6)
US. Patent
Nov. 23, 2010
Sheet 6 0f 26
FIG. 7
US RE41,959 E
PRIOR ART
HOOOOOOOO
| 16~BIT
noooosooorg
ADDRESS
HOO0O8100—
SPACE
HOOOOFFFF——-
-
-
-
-
'
‘L
32-BIT
ADDRESS SPACE
HFFFF8000
HFFFFFFFF
US. Patent
Nov. 23, 2010
Sheet 7 0f 26
US RE41,959 E
FIG. 8 PRIOR ART
SUB 00,130 —-(1) MOVI #H8000,AO --—(2-1) ANDI #HOOOOFFFF,A0 ——(2-2) LABELA
MOV ADD ADDI MOVI ANDI CMP BLT
@AO,D1 ——-(3) mp0 —-—(4) #HO010,A0 ———(5) #H8100,AO —---(6- 1) #HO00OFFFF,A1——~—-(6n2) A1,AO —-——(6-3) LABELA -——-(7)
LABELB
MOV D0,@H 10000000 #(8)
US. Patent
Nov. 23, 2010
Sheet 8 0f 26
US RE41,959 E
FIG. 9 PRIOR ART
INSTRUCTION
i
91
INSTRUCTION DECODING UNIT CALCULATION CONDITIONAL BRANCH DESIGNATION DESIGNATION {,92
-
l6-BIT CALCULATOR
lg-Bl'r
BRANCH IUDGING UNIT
BRANCH TAKEN OR NOT TAKEN
US. Patent
Nov. 23, 2010
Sheet 9 0f 26
US RE41,959 E
FIG. 10 PRIOR ART INSTRUCTION
l
101
INSTRUCTION DECODING UNIT CALCULATION CONDITIONAL BRANCH DESIGNATION
r DESIGNATION
BIT-WIDTH DESIGNATION / 102
16-BIT CALCULATOR
1I6-BIT
8-BIT
l‘___‘
104"
4-BIT
I
N r
v 1/103
V N Z
103-1
103-3
BRANCH JUDGING UNIT
BRANCH TAKEN OR NOT TAKEN
US. Patent
Nov. 23, 2010
zoE?
_ — @ TEMEQLEGL
2ZmovO\uCQrwDEMzUnm< E05mé:
Sheet 10 0f 26
E9$zo5F<26Q:mo Eiv
M.Hm:0-U5
im2z9uo5E3é.
US RE41,959 E
mzouEa< \ \
mZwOuEQzéMnUmO Z$OF<5Q-m8
Emé
US. Patent
Nov. 23, 2010
Sheet 11 0f 26
US RE41,959 E
FIG. 12A PRIOR ART
9
H0O Lllllll
H88 llllLll
H0O
HF8
l lllll l
lllllll
FIG. 12B PRIOR ART
H88 Illllll
llllll
lllllll
US. Patent
Nov. 23, 2010
Sheet 15 0f 26
US RE41,959 E
— _ TEMGQLMEMEQV _
<26E
Zzo1m?2ua0g5éh8 O@U~PD
a
E5:
@mEwMQ2593a0g8xmE. 250683
zowMk9PdEq5m2Qo8 E3
US. Patent
Nov. 23, 2010
Sheet 16 0f 26
US RE41,959 E
FIG. 17
DECODING UNIT 6 2 lQIl
_R _I M lI|lI1T FIR II‘. _
6
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."E w E u n D N a_
7C12I_
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su w .U
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2., “.13u A
||_s|1uv|1ilI|
,w 1h f_ u 41L31 36_
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B 4_05
1"1U..
BUS CONTROL‘UNIT _
_
_
_
_
_
_
_
_
_
_
_
~
_
MEMO RY
1,130
US. Patent
Nov. 23, 2010
Sheet 17 0f 26
FIG. 18A
FIG. 18B
US RE41,959 E
US. Patent
Nov. 23, 2010
Sheet 18 0f 26
US RE41,959 E
FIG. 19
@ SYNTAX ANALYSIS STEP 20 GENERATE INTERMEDIARY FILE AND STEP 21 SYMBOL TABLE
__
I
T1
ANY STEP 22 UN-PROCESSED INTERMEDIARY INSTRUCTION 7
END YES
STEP 23
READOUT ONE INTERMEDIARY INSTRUCTION I SELECT ONE OR MORE MACHINE LANGUAGE INSTRUCTION
STEP 24
l DEsIGNATE INDIVIDUAL INSTRUCTION I STEP 25 I
GENERATE OPERATION CODE
STEP 26
ARITHMETIC OPERATION INSTRUCTION "
STEP 28
FOLLOWING _ INSTRUCTION ‘7
YES