Crosstalk Investigation of an All-Optical Serial-toParallel Converter Based on the SMZ M. F. Chiang, Z. Ghassemlooy, Senior Member, IEEE, Wai Pang Ng, Member, IEEE, H. Le Minh, and V. Nwanafio Optical Communications Research Group, NCRLab, School of Computing, Engineering and Information Sciences Northumbria University, Newcastle upon Tyne, NE1 8ST, UK Email: {ming-feng.chiang, fary.ghassemlooy, wai-pang.ng, h.le-minh, vincent.nwanafio}@unn.ac.uk Abstract— In this paper an all-optical serial-to-parallel converter (SPC) based on the symmetric Mach-Zehnder (SMZ) interferometers operating at 80 Gb/s is presented. The proposed SPC is simulated and in particular its crosstalk (CXT) characteristics is investigated for a range of different system parameters such as signal and control pulse powers, delay time between the control pulses, and the main physical parameters of semiconductor optical amplifiers (SOAs). It is shown that CXT highly depends on the gain of the SMZ switching window and the difference in the gain profiles of SOAs in the gain recovery region. We show that there is a trade-off between the amount of CXT and the power level of the output signal. CXT of -20 dB is achieved at relatively low control power of ~20 mW.

(SW) [7]. Crosstalk associated with a switch and its impact on the system performance has been studied in [8], [9], but not in the context of this particular application. Here we investigate crosstalk characteristics of a SMZ switch employed as the main building block for the SPC. The paper is organised as follows: after introduction, the operation principles of the SMZ and the SPC, together with the crosstalk characteristics are shown in section II. Section III presents the simulation results and discussions. Finally, section IV will conclude the paper.

Index Terms—Symmetric Mach-Zehnder, semiconductor optical amplifier, serial-to-parallel, control pulse, inter-channel crosstalk.

A. Symmetric Mach-Zehnder (SMZ) Figure 1 shows the structure of SMZ switch comprises SOAs, and a number of 3-dB couplers. By means of injecting two high power control pulses (CP1 and CP2) into SOA1 and SOA2, respectively at different time, the induced phase difference between two arms enables the SMZ either to be switched on or switched off, thus creating a SW. For example, with no CPs, the upper and lower arms of the SMZ are in the balance state and the input signal emerges from the output2. Applying the CP1 changes the gain characteristics of SOA1, and as a result the SMZ becomes un-balanced (i.e the SW is switched on) and the input signal emerges from outport1. By applying CP2, delayed by Tsw with respect to CP1, to the SOA2 the SMZ once again becomes balanced (i.e. the SW is off) and therefore the input signal emerges from output2. In order to distinguish between the control and data pulses at the output ports, the CPs are launched at orthogonal polarization with respect to the data pulses. At the output ports, polarization beam splitters (PBS) are to separate CPs from data pulses. The gain profiles of SOA1 and SOA2 are given by [9]:

I.

A

INTRODUCTION

s the demand for network capacity is growing rapidly, the need to fully utilize an all-optical networks is increasing. Full exploitation of all-optical network is realizable provided all routing and switching of information are carried out in the optical domain. However, in a number of cases the switching process is still performed in the electrical domain which requires optical/electrical/optical (O/E/O) conversion [1]. O/E/O conversion not only requires extra power, but it also imposes speed bottleneck due to the data processing speed of conventional electronic components currently is limited to 40 Gbit/s [2]. The next generation optical networks are aimed to avoid O/E/O conversions and carry out all processing in the optical domain [3]. All-optical networks based on packet-switching [4], [5] are more flexible than circuit-switched networks and are more suitable to deal with bursty traffic offering higher throughput and switching speed. In packet switched networks, all-optical serial-toparallel conversion (SPC) is essential for address recognition. A number of techniques for implementing SPC using surfacereflection all-optical switches have been proposed [6], but it requires a number of micro lens and mirrors. In this paper, we propose SPC based on the SMZ switch configuration. SMZ is chosen due to its compact size, thermal stability, low-power operation, short and almost square switching window profiles

II. OPERATION PRICIPLE

G

G

1

2

⎡ (t ) = e x p ⎢ ⎢⎣ ⎡ (t ) = ex p ⎢ ⎢⎣

L

∫ 0

L

∫ 0

⎛ z Γ .g ⎜ z , t + ⎜ V g ⎝

⎛ z Γ . g ⎜ z , t + T sw + ⎜ Vg ⎝

⎤ ⎞ ⎟⎟ d z ⎥ ⎥⎦ ⎠

(1)

⎤ ⎞ ⎟⎟ d z ⎥ ⎥⎦ ⎠

(2)

Tsw

Tsw

CP1

PC1 SOA1

Input signals Coupler2

PBS Output1

Coupler1

Coupler4

CP2 Output2 PC2

Coupler3

SOA2

Figure 1: SMZ structure

Figure 2: SPC system block diagram

where L is the length of the active region of the SOA, Γ is the confinement factor, g is the differential gain, Tsw is the time delay between CP1 and CP2, and Vg is the group velocity of the control pulses. The relationship between gain saturation and non-linear phase is given by [10]: −2 Δφ ( p )

Gs ( p ) = G0 × e

α LEF

(3)

where Gs(p) is the gain in the saturated regime for a given input power P, G0 is the gain in the unsaturated regime, ΔΦ(p) is the induced phase shift for a given P, and αLEF is the linewidth enhancement factor. The SOA gain G is approximately given by [11]:

G = eΓ ( gm −α ) L = e

Γ[ g0 ( N − N 0 ) −α ] L

=e

η Iτ ⎡ ⎤ Γ ⎢ g0 ( i s − N 0 ) −α ⎥ L eLwd ⎣ ⎦

(4)

where gm is the material gain, α is the optical loss, g0 is the gain coefficient, I is the inject current, N is the carrier density at the operating current I, N0 is the carrier density at transparency, ηi is the current injection efficiency, τs is the spontaneous recombination lifetime of the carriers, e is the electronic charge, and w, d are the width, and thickness of the active region of the SOA. The power at output1 and output2 of SMZ are given as [12]:

1 Pout ,1(t) = Pin (t) ⋅ ⎡⎣G1(t) +⋅ G2 (t) − 2 ⋅ cos(Δφ) G1(t) ⋅G2 (t) ⎤⎦ (5) 8 1 Pout ,2 (t) = Pin (t) ⋅ ⎡⎣G1(t) +⋅ G2 (t) + 2 ⋅ cos(Δφ) G1(t) ⋅G2 (t) ⎤⎦ (6) 8 where Pin(t) is the power of the input signal and ΔΦ is the phase difference of the input signals between the upper and lower arms of the SMZ given by [12]:

TABLE I SOA SIMULATION PARAMETER

TABLE II SIGNAL AND CONTROL PULSES DEFAULT PARAMETERS

(a)

(b)

Figure 3: (a) The gain profiles of SOA1 and SOA2, and (b) the SW profile of SMZ output1

Δ φ = − 0 . 5 α LEF ln (G 1 / G 2 )

(7)

where αLEF is the linewidth enhancement factor. The width of the SW profile is given by [12]:

1 W(t) = . ⎡⎣G1(t) +⋅ G2 (t) − 2 ⋅ cos(Δφ) ⋅ G1(t) ⋅G2 (t) ⎤⎦ 4

(8)

B. Serial-to-Parallel Module Figure 2 shows the block diagram of the proposed SPM, which is composed of a number of SMZ modules, fibre delay lines (FDL), 1×4 splitter and a number of PBSs. The incoming data signal is split into four bits using a 1×4 splitter, which are then applied to the inputs of the parallel SMZ modules. The first 3 outputs are delayed by 3Tb, 2Tb and Tb, respectively for selecting the 1st (bit ‘0’), 2nd (bit ‘1’), 3rd (bit2) and the 4th (bit3) bits of the input signals. Introducing correct delay is essential in order to ensure that the data signal sits in the centre of the SMZ SW. Identical CP1 is applied to all SMZs prior to the target data signals in order to saturate the SOAs in the upper arms, thus turning on the switch. After Tsw delay time, CP2 are applied to the SMZs to saturate the SOAs in the lower arms, thus turning off the switch). Polarization controller (PC) is used to distinguish between CP1 and CP2 and the data pulses. PBS at the output ports of the SPC are used to separate the data signals and CPs. The numbers of SMZs is equal to the numbers of serial bits converted.

C.

Inter-Channel Crosstalk With a high power CP applied to the SMZ, the SOA gain saturation is abruptly dropped (i.e. ΔG). However, once the CP has exited the SOA, the gain recovery is rather slow orders of magnitude higher than the saturation time, see Fig. 3(a). Note the slight difference in the gain profiles for SOA1 and SOA2 in the recovery region (i.e. Δg), which results in an uncompleted cut-off edge of the SW profile, see Fig. 3(b). As a consequence, the undesired signals are also switched at the output1 of SMZ, which are main source of CXT defined as [8]:

CXT = 10 log10 ( Pnt / Pt )

(9)

where Pnt is the sum of the output signal power of all nontarget channels and Pt is the output signal power of the target channel. III.

SIMULATION RESULTS AND DISCUSSIONS

The proposed SPC is simulated using the Virtual Photonics Inc. simulation software and its CXT is investigated in detail against a number of system parameters. All the main parameters used are shown in Tables I and II [5]. Figure 4(a) shows CXT against the CP power for different values of input signal power (SP). The lowest CXT is achieved when both SP and CP are at low values. E.g., for CP of 20 mW and SP of 0.5 mW the CXT is ~–20 dB. However for CP > 120 mW, the

-18.4

-15

-18.6

-16

-18.8

CXT Ratio (dB)

CXT Ratio (dB)

-14

-17

-18

SP=0.5mW -19

-19 -19.2 -19.4

SP=1mW -19.6

SP=2mW

-20

SP=4mW

-19.8 0

-21 0

20

40

60

80

100

120

140

160

180

200

220

0.5

1

1.5

2

2.5

3

3.5

FWHM of CP&SP (ps)

Control Power (mW) (a)

(b) Figure 4: Crosstalk vs. (a) control power,and (b) FWHM of CP and SP

best CXT is achieved for SP of 4 mW. Note that the minimum level of CXT not only increases with the SP power but is also achieved at higher values of CP power. This is because higher power CPs contribute to increased gain saturation of the SOA, and consequently resulting in a higher gain difference in the recovery region, thus leading to a higher CXT. CXT changes very little (about 1 dB) with the duration of the CP and SP, provided they have the same FWHM, see Fig. 4(b). This is because CXT mostly depends on the pulse power rather than pulse width. The small increase in the CXT is due to the higher average power of the non-target pulses residing within the SW window. As shown in Fig. 5(a), CXT increases with the size of the SW width, due to the greater difference between G1 and G2 profiles. Although small Tsw leads to a lower CXT, but it results in reduced level of the output signal, due to lower gain of the SW. In Fig. 5(b), CXT increases rapidly with αLEF. This can be explained from (5) and (7). Higher values of αLEF will result in increased gain difference between G1 and G2 at the off (low) state of the SW, therefore leading to higher

output power Pout,1 of the non-target pulses and consequently a higher CXT. Next we investigated CXT characteristics against the inject current and the confinement factor, showing a linear behaviour as illustrated in Fig. 6(a). This can be explained by (4), where higher values of I and Γ will result in a higher G. Note that higher I and Γ also contributes to a faster gain recovery time (i.e. increased Δg) and increased ΔG (see Fig. 3), respectively. Finally Fig. 6(b) shows the decrease in CXT with the SOA length, since longer SOA results in a higher gain for both the SW and non-target pulses, see (4). The lowest level of CXT is achieved for the following system parameters: CP and SP with FWHM of 1 ps, Tsw of 3 ps, L of 1000 μm, I of 0.15 A, Γ of 0.15, αLEF of 0.5, SP power of 0.5 mW, and CP power of 20 mW. Simulation result showed that, for data rates of 80, 160, and 320 Gb/s, the lowest level of CXT observed are at –33.27, –28.20, and – 22.78 dB, respectively, but at the cost of reduced output power levels of 2.80, 1.40, and 0.47 mW, respectively.

-16

-17

-16.5 CXT Ratio (dB)

CXT Ratio (dB)

-15.5 -15

-19 -21 -23 -25

-17 -17.5 -18 -18.5 -19

-27

-19.5

-29 0

2

4

6

8

Tsw (ps) (a)

10

12

14

16

-20 0

2 4 6 8 Linewidth Enhancement Factor (b)

Figure 5: Crosstalk vs. (a) CP1 and CP2 delay times, and (b) linewidth confinement factor

10

-2 -16

-4

-17

-8 -10 -12

Inject Current

-14 -16

CXT Ratio (dB)

CXT Ratio (dB)

-6

Confinement Factor

-18 -20

-18

-19

-20

-21

-22 0

0.1

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0.3

0.4

0.5

0

0.6

200

400

600

800

1000

1200

SOA Length (um)

Inject Current (mA); Confinement Factor (a)

(b)

Figure 6: Crosstalk vs. (a) inject current and confinement factor, and (b) SOA length

However, higher values of output power (i.e. higher signalto-noise ratio) could be achieved either by increasing Tsw , I, Γ,or αLEF , but at the cost of increased CXT level. Thus there exists a trade-off between the output power and the CXT. IV.

CONCLUSIONS

The paper has investigated the crosstalk performance of a serial-to-parallel converter by employing different SOA parameters, and different control and signal pulses powers. The gain of the SMZ SW and the difference in the gain profiles of SOA1 and SOA2 in the gain recovery region dominate the CXT performance. There is a trade-off between the amount of CXT and the power level of the output signal. From our simulation results we found that the proposed SPC is capable of operating at relatively low control power (~20 mW) to achieve the minimum CXT level of -20 dB. Furthermore, by carefully selecting the SOA parameters the CXT level of the SPC could be further controlled to ensure the optimum performance. REFERENCES [1] [2]

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