Changes in the lsi-v2013.01.01 Branch U-Boot 126.96.36.199 Changes • Revert “Changes for ARM errata 833469 and 834769 (CCN-504)”. • Update the default peripheral memory access settings. • Backport a patch to avoid infinite loops when attempting to read corrupted ext4 file systems. • Revert the commit included in 188.8.131.52 that eliminated the watchdog reset call in udelay(). This was originally included to handle the corrupt ext4 file system problem now solved by the backport mentioned above.
U-Boot 184.108.40.206 Changes • Changes for ARM errata 833469 and 834769 (CCN-504). When flushing the L3 cache, switcth the state to OFF and then to FULL instead of to SFONLY and then to FULL.
U-Boot 220.127.116.11 Changes • When using EIOA to boot, ‘macspeed=auto’ now works for GMAC ports. • Allow builds with either gcc 4 or gcc 5. • Outer cache functions are now written in assembler so they don’t use the stack.
U-Boot 18.104.22.168 Changes • Add a define to select which method of redundancy gets used when updating the parameters.
U-Boot 22.214.171.124 Changes • Update the unused parameters to avoid corrupting the parameters in use. • Indicate write errors, if they occur, when updating the parameters.
U-Boot 126.96.36.199 Changes • Only update the DDR settings in the parameters once, not every boot.
U-Boot 188.8.131.52 Changes • Add a watchdog update while running the MBIST.
U-Boot 184.108.40.206 Changes • Enabled Dynamic ODT in the DDR Retention Case. • Allow Flush Cache with End Address of 0xffffffff. • Revert the fixes to allow building with gcc 5.x, those changes break building with 4.x.
U-Boot 220.127.116.11 Changes • Fixes to allow building with gcc 5.x.
U-Boot 18.104.22.168 Changes • Revert the previous change to run LSM uncached. Instead, clear the HN-I errors before jumping to Linux. • Update the ssp driver transfer function to avoid a failure that is still under investigation.
U-Boot 22.214.171.124 Changes • SPL Linker map updates. – The page table was overlapping the BSS. – Available LSM was wrong based on the stack pointer.
U-Boot 126.96.36.199 Changes • In the MMU, make LSM uncached in the SPL. • Clean up printf() formatting in system memory initialization.
U-Boot 188.8.131.52 Changes • Update SMEM initialization to set the SRT bit in the DRAM MR2 register when ‘highTemperature’ is set in the parameters.
U-Boot 184.108.40.206 Changes • Don’t set ccn_qos_rni6_s0 in simulation.
U-Boot 220.127.116.11 Changes • Add the option, on by default, to leave the L3 cache in SFONLY mode. This is a work-around for occasionaly problems noticed when booting Linux. Make sure to get a version of Linux that re-enables the L3. • Don’t call the watchdog reset function in udelay(). • If ccn_qos_rni6_s0 is not set in the U-Boot environment, use a default value of 0x00cc000c. The default is defined in include/configs/axxia-arm.h. • Fix compile errors when DEBUG is defined. Only errors in Axxia specific code are fixed.
U-Boot 18.104.22.168 Changes • Removed SBB lockup test code that got checked in by mistake.
U-Boot 22.214.171.124 Changes • Corrected the sbb command return codes.
U-Boot 126.96.36.199 Changes • QoS support for AXI priority. If ccn_qos_rni6_s0 is set in the U-Boot environment, so_qos_control will be set to that value. • Updated the sbb command messages and error handling. In the previous version, an unsigned, and optionally unencrypted, image would boot with secure boot enabled. • PCIe speed change and enumeration now only applies when in root complex mode.
U-Boot 188.8.131.52 Changes • Make ‘sbb verify’ pass for all images when secure boot is disabled.
U-Boot 184.108.40.206 Changes • Work-around when using the SBB to validated images. To avoid lockups, the ‘aux_ctl’ register needs to be set to 0x9 while the SBB is validating images. • Now reads the CNTPCT value correctly In the work-around for ARM 811981. • Added support for SRIO 16 bit transport ID. Controlled by the parameter file.
U-Boot 220.127.116.11 Changes • Updated defines related to memory usage, and added comments. See include/configs/axxia-arm.h. • Calculate the size of secure images before reading them from flash. • New API for axxia_hybrid_mbist(). • Power down unused serdes channels. NOTE: To Power Down Unused Serdes Channels HSS5 & HSS6 lanes can be powered down via the following new PCIe/SRIO SPL parameter fields. Note that these new SPL parameter fields are not supported by the ASE hardware configuration editor yet. Support for these new fields will be provided in a forthcoming (newer than 18.104.22.168) ASE release. Monitor the ASE README for notification of feature availability. Prior to ASE support, HSS lane power-down can be enabled by hand-editing the ASE generated SPL parameter file. The current ASE hard-codes these PCIe/SRIO fields to 0. Therefore, legacy behavior is maintained when using a new U-Boot SPL with an SPL parameter file generated by current ASE software. PCIe/SRIO -
Bit Bit Bit Bit Bit Bit Bit Bit
19 18 17 16 15 14 13 12
: : : : : : : :
Powerdown Powerdown Powerdown Powerdown Powerdown Powerdown Powerdown Powerdown
HSS6 HSS6 HSS6 HSS6 HSS5 HSS5 HSS5 HSS5
ch3 ch2 ch1 ch0 ch3 ch2 ch1 ch0
U-Boot 22.214.171.124 Changes • Set tref_enable during DDR controller initialization.
U-Boot 126.96.36.199 Changes • Fixed USB ULPI reads. • Align the reset cpu fabric sequence so it fits in one cache line and keep the compiler from optimizing out the read back of the reset control register
U-Boot 188.8.131.52 Changes • • • • •
Work arounds for ARM Errata. 8111981 ? (see BZ 49133 or commit ab815bdb40b13461214d7f5f38b6e2e9ffa657ea) Support for Spansion S25FL164K. Hybrid mbist support.
U-Boot 184.108.40.206 Changes • EIOA Updates – Fix slot for gmac1/gmac7 – Fix tagGenMSB for gmac19/gmac20. – Support for copper PHYs and AN • Update the watchdog during spl_mtest.
U-Boot 220.127.116.11 Changes • EIOA updates for gmacs 1, 17, 19, and 20.
U-Boot 18.104.22.168 Changes • Power down HSS0-4 lanes after EIOA downloads. • Fix single SMEM operation with DDR retention enabled.
U-Boot 22.214.171.124 Changes • Redundant/Secure Boot Updates – Don’t boot unsigned/unencrypted images if secure boot is enabled. – Require U-Boot image files as input for secure boot.
U-Boot 126.96.36.199 Changes • Updated sysmem init to set the correct values for tinit and cke_inactive.
U-Boot 188.8.131.52 Changes • Handle signed/encrypted images when redundant boot is enabled. • Allow more flexible ranges in spl_mtest.
U-Boot 184.108.40.206 Changes • • • • • • •
Remove 64 bit divisions, use lldiv() or do_div() as needed. Enable exceptions. Return the current frequency in get_tbclk(). Leave memory from the end of U-Boot up to 1G available. Corrected page table entries used by spl mtest. Support for partial goods. In simulation, change bootargs to have Linux use virtio (axxia-55xx-simvirtio) or mmc (axxia-55xx-sim-mmc) as desired.
U-Boot 220.127.116.11 Changes • Reduce the number of watchdog updates while testing memory. • Fixed compiler warnings, and add -Werror (turn warnings into errors) to the C flags. • Add a warning when failing on voltage out of range. • Enable the watchdog timer earlier in U-Boot. • Fixes for thumb builds and register usage in assembler called by C. • Turn off debug output during system memory initialization. • Errata 812169 from ARM applies to our hardware. U-Boot now sets bit 7 in the L2ACTLR as recommended by ARM. • Updated PCIe code so that the Gen2 speed change work-around is only used on v1.0 hardware.
U-Boot 18.104.22.168 Changes • Update the global SPL image structure after loading the second U-Boot image. • Start the watchdog timer before initialization. Without this, errors caused by a parameter file update will be fatal. • Support booting on v1.0 hardware with v1.1 parameters. This means that the FAB and SYS PLLs will be set to default values on v1.0, ignoring the parameters. • Display the parameter description field when reading parameters. • Added option to leave the watchdog timer running when leaving U-Boot. To do this, define LEAVE_WATCHDOG_ON. • Fixed boot failure when using copy B of the parameters.
• SPL memory test ranges are now passed correctly.
U-Boot 22.214.171.124 Changes • Redundant boot support for U-Boot images. • Suppress erroneous error messages about Parameter magic numbers during boot. • Only map LSM (256K) instead of the first 1G for SPL. • Remove chip reset after pin reset added in 126.96.36.199. The original issues was an inadvertent write to the lor register.
U-Boot 188.8.131.52 Changes • Fix compile error when CONFIG_SPL_MTEST is defined. • Add support for single SMEM.
U-Boot 184.108.40.206 Changes • Remove debug code for watchdog timer reset test. • Add a chip reset after a pin reset on v1.1 silicon. This is a work-around for the stall after “Starting kernel. . . ”.
U-Boot 220.127.116.11 Changes • System Memory range testing now uses a software test instead of the hardware bist. When all of system memory is used, the hardware test is still used. • Updated parameter file handling to match the latest version 9 paramters.
U-Boot 18.104.22.168 Changes • Switch to version 9 paramters. • Redundant parameter file support.
U-Boot 22.214.171.124 Changes • Don’t enable secondary cores when in normal mode, as this is handled by Linux. • Run U-Boot in normal mode to allow access to USB.
U-Boot 126.96.36.199 Changes • Support for v1.0 (in secure mode) and v1.1 (in normal mode).
U-Boot 188.8.131.52 Changes • Secure Mode for v1.0 and v1.1.
U-Boot 184.108.40.206 Changes • Preliminary (untested) support for the v1.1 5500. • Power down HSS6 when PEI1 is not used.
U-Boot 220.127.116.11 Changes • Corrected problems in the code that disables WFE when running on v1.0 silicon. • Added support, disabled by default, for the watchdog timer. • The U-Boot environment is now available in the SPL.
U-Boot 18.104.22.168 Changes • Allow user level access to the performance counters. • SPL mtest updates. – No longer uses an invalid pointer for data line test. – New arguments allow the number of iterations and the type of test, data, address, mtest, or all, to be specified. • EIOA network driver now allows multiple loads without reset. • L1/L2 ECC and Parity checking is now enabled. • MDIO clock offset and parity are now configurable using compile time constants in include/configs/axxia.h and the U-Boot environment variables mdio_clk_offset and mdio_clk_period. • For all memory regions that won’t contain executable code, the XN bit is now set in the page tables. • Only renegotiate the PHY link if necessary.
U-Boot 22.214.171.124 Changes • Initial support for AVS. The volatage offset table is not yet supported. To change the voltage, add a function, int set_vrm_to_vrun() to set the voltage. See board/lsi/axxia-arm/voltage.c.
• Update PCIe driver to only enumerate if PCIe has been configured. • Added a new memory test function, mtest, based on mtest86. • Updated Makefiles to work with the latest Yocto tools.
U-Boot 126.96.36.199 Changes • Updated the generation of version numbers to work when building out of a git clone. The LSI version will be UNKNOWN in that case. • Use the correct offset for the SBB status register during secure boots.
U-Boot 188.8.131.52 Changes • Suport for secure boot. • I2C: Adjust tLOW and tHIGH to match fast-mode requirements.
U-Boot 184.108.40.206 Changes • Cleaned up compiler warnings. • Implemented work around for cross-cluster event problems in v1.0 silicon. • Replaced invalid copyright headers.
U-Boot 220.127.116.11 Changes • Add “mem=1024M” to bootargs in simulation. • Specify that debug information use dwarf v3 and not dwarf v4. ARM’s DS-5 debugger doesn’t support dwarf v4 until version 5.16.
U-Boot 18.104.22.168 Changes • Update PCIe/SRIO device tree entries based on the SerDes configuration. • Check for ECC errors after running mtest. • Allow building with the Yocto generated SDK.
U-Boot 22.214.171.124 Changes • Add simulation as a target, axxia-55xx-sim. Support for simulation is not complete. • Support for the Gen2 speed change workaround for PEI0 x1/x1 and PEI1 x4/x2/x1.
• Added support to enable PEI0/PEI1 in the device tree based on PCIe SerDes configuration. • Now checks the validity of saved parameters before using them for DDR recovery.
U-Boot 126.96.36.199 Changes • Enable SRIO0/SRIO1 DTS entries based on the SRIO PHY SerDes settings. • Handle memory sizes larger than 4G.
U-Boot 188.8.131.52 Changes • • • •
I2C: Use only manual mode transfers. System Memory Initialization: Update ODT configuration. Added SerDes configuration support for all PCIe/SRIO modes. Fixed a defect in the SPI flash driver that allowed the divisor to be 0 or 1. The divisor must be 2. . . 254 and even. • Updated BIST to set the size correctly.
U-Boot 184.108.40.206 Changes • Added support for booting the latest Linux on the emulation platform.
U-Boot 220.127.116.11 Changes • Works on the emulation platform. • Enable ODT on system memory.
U-Boot 18.104.22.168 Changes • Added support for a redundant parameter table.
U-Boot 22.214.171.124 Changes • Updated defines for DDR retention. DDR retention was broken without this change. • Enable sev/wfe event signalling across clusters. • Implemented ehci_hcd_stop(). • SerDes PHY updates for SRIO host and agent modes.
U-Boot 126.96.36.199 Changes • Now uses the version 7 parameter file.
U-Boot 188.8.131.52 Changes • Fixed problems with memory testing based on the parameter flags. Bits 31:30 now work as described in the parameter file comments. • PCIe Gen1/Gen2 speed change and serdes setup updates.
U-Boot 184.108.40.206 Changes • Resolution of BZ 46214. Leaving the L1/L2 caches enabled while calling the functions to flush L3 doesn’t work because updates to L1/L2 get lost. Instead, disable caching before flushing. • Added work around for ARM errata 784420. Disable branch prediction when disabling the MMU. • Fixed tracing of config ring accesses during memory initialization. • System Memory Initialization Updates * Improved coarse write leveling. * Enable Auto-ZQ calibration (fixed interval for now).
U-Boot 220.127.116.11 Changes • Don’t invalidate the data cache after it has been disabled! This caused memory corruption in some cases. • Remove the old SSP driver. The SSP should be access using the U-Boot driver; serial flash access is available using the mtd driver. • Enable software access to cp14 registers and power on ETB ram modules. • Update the ncr command to allow access to the virtual nodes supported by the ncr access code. • Replace the auto-refresh work around with corrected coarse write leveling. • Fix up the VAT addressing when switching the memory map from reset to mission. • Updated PCIe Gen2 work around.
U-Boot 18.104.22.168 Changes • Disable auto refresh until after DDR PHY training is complete. • Disable USB driver work arounds when not required.
U-Boot 22.214.171.124 Changes • Updated the parameters API to handle writes correctly. • Updated the network driver to avoid indicating the PHY link as up incorrectly. • Added work around for BZ 45907. The bootROM leaves SPI device 0 selected. The SF layer expects no devices to be selected. For now, U-Boot will deselect all devices before using the SF layer. • Added support for DDR retention. • PCIe updates – Gen2 software work around. – PEI1 SERDES config now matches the parameter file setting.
U-Boot 126.96.36.199 Changes • Added a function, int __weak usb_phy_init(void), that can be overridden as needed for board-specific USB PHY initialization. • I2C Updates – Fixed lockup in i2c driver. – Properly calculate the prescaler divider for the WAIT_TIMER making sure the timeout value doesn’t overflow the 15-bits. – Change to i2c_probe function to read one byte instead of zero. The automatic transfer mode of the controller doesn’t handle zero-length transfers. – Make the read/write functions wait for state machine to go idle before returing.
U-Boot 188.8.131.52 Changes Added PCIe enumeration support. See comments in U-Boot SPL parameters file for board specific PCIe/SRIO SerDes lane configuration. Note that this is an early access engineering drop of this feature. Only minimal unit testing has been performed at the time of this release.
U-Boot 184.108.40.206 Changes • Update U-Boot SPL with simplified and improved DDR coarse write leveling algorithm. • Modify U-Boot SPL to use simple read-only SSP/SPI driver for reading the U-Boot SPL parameter data prior to system memory initialization and having heap and stack support. Subsequent to system memory initialization the full function SSP/SPI driver is enabled and used. • Resolve issue with U-Boot SPL not detecting certain SPI FLASH devices.
U-Boot 220.127.116.11 Changes Note that U-Boot 18.104.22.168 has only been tested with LSI Linux 22.214.171.124, based on Linux 3.4.43. • Add EIOA driver support (ability to use EIOA ports for tftp and bootp services) to U-Boot. See “Using EIOA (55xx)” section of Readme_lsi v2010.03 on lsigithub lsi_axxia_uboot_public wiki page. • Add I2C support both U-Boot SPL and U-Boot. • Add initial support for configuring the PCIe SerDes in x4 Gen-1 mode (Full PCIe root complex support is ongoing) to U-Boot SPL. • Add support for “reset” command to U-Boot. • Add full/standard U-Boot SPI driver support to U-Boot SPL. • Fix ncr_read for SYSMEM addresses >= 4 GB.
U-Boot 126.96.36.199 Changes • Increased PHY RX FIFO size to address RX FEMAC CRC/Alignment errors
U-Boot 188.8.131.52 Changes • Added U-Boot command support for ULPI PHY read/write
U-Boot 184.108.40.206 Changes • • • • • •
SMEM DDR configuration updates Fix to course write leveling programming sequence Fix for ECC byte lane read leveling Fix for PHY configuration of WL_RANK value FEMAC driver fix Added ARM barrier instruction in transmit path between writing packet data and updating the DMA head pointer register. • Added USB support