Building A Cognitive Radio Network Testbed Zhe Chen, Nan Guo, and Robert C. Qiu Department of Electrical and Computer Engineering Center for Manufacturing Research Tennessee Technological University Cookeville, TN 38505, USA Email: [email protected], {nguo, rqiu}@tntech.edu Abstract—Cognitive radio has been put forward to make efficient use of scarce radio frequency spectrum. A testbed for cognitive radio can not only verify concepts, algorithms, and protocols, but also dig out more practical problems for future research. However, to our best knowledge, an authentic real-time cognitive radio system has never been demonstrated. In order to build a cognitive radio network testbed, four popular commercial off-the-shelf hardware platforms are investigated. Unfortunately, none of them meets our needs. Thus, an architecture of the motherboard and a functional architecture for nodes of cognitive radio network testbeds, as well as an architecture for cognitive radio network testbeds, are proposed. With the proposed architectures, a cognitive radio network testbed is being built at Tennessee Technological University.

I. I NTRODUCTION Cognitive radio (CR) has been put forward to make efficient use of scarce radio frequency spectrum. It introduces “adaptiveness” and “intelligence” to traditional radios. The term “cognitive radio” was initially coined by Joseph Mitola over a decade ago [1]. Later, Simon Haykin defined cognitive radio as an intelligent wireless communication system in [2]. Cognitive radio network (CRN), generally speaking, is a network composed of CR nodes, with “intelligent” networking functions. The general concept toward cognitive networking was introduced a few years ago in [3], [4], [5], [6]. Although there have been many research works on CR and CRN, to our best knowledge, an authentic real-time CR system has never been demonstrated. So far, we have developed algorithms for CR on spectrum sensing [7], [8], cooperative spectrum sensing [9], channel state prediction [10], [11], and spectrum allocation [12]. These algorithms provide basic functions for CR systems. By implementing these algorithms as well as traditional communications algorithms on a cognitive radio network testbed (CRN testbed) in real-time, a CR system can be demonstrated. We are building a CRN testbed at Tennessee Technological University. There are three reasons for us to develop the CRN testbed. First, a CRN testbed enables a real-time demonstration of the concept of CR and CRN. Second, algorithms and protocols for CR and CRN can be further tested in real-time on a CRN testbed. Thirdly, by developing a CRN testbed, unexpected or practical problems will be dig out for future research. There have been some wireless network testbeds, such as the open access research testbed for next-generation wireless networks (ORBIT) [13] and the wireless testbed developed

by University of California, Riverside [14]. Some common features of those wireless network testbeds are summarized as follows. First, the nodes in the networks are developed based on computer central processing units (CPUs). Second, the nodes use network interface cards like 802.11 Wi-Fi for wireless communications. These network testbeds may work well for evaluating algorithms, protocols, and network performances for Wi-Fi networks. But they are not suitable for CRNs, due to their inherent lack of wide-band frequency agility. Lately, Virginia Tech has developed a testbed for CRNs with 48 nodes [15], which is an exciting advance in this area. Each node consists of three parts: an Intel Xeon processorbased high-performance server, a universal software radio peripheral 2 (USRP2), and a custom developed radio frequency (RF) daughterboard that covers a continuous frequency range from 100 MHz to 4 GHz with variable instantaneous bandwidths from 10 kHz to 20 MHz. The node is well capable of frequency agility. However, as the authors mention, the drawbacks of the nodes are twofold. First, it is not a low-power processing platform. Second, it is not capable of mobility. In our understanding, two important features for nodes of CRN testbeds are computing power and response time delay. We have investigated existing commercial off-the-shelf hardware platforms that may be used for nodes of CRN testbeds. Unfortunately, none of the hardware platforms is suitable for building our desired CRN testbed. To overcome the shortcomings of the existing hardware platforms, such as lack of frequency agility, lack of mobility, not enough computing power, and large response time delay, we propose an architecture of the motherboard and a functional architecture for nodes of CRN testbeds in this paper. Based on the proposed nodes, a CRN testbed can be further built. The rest of this paper is organized as follows. Section II introduces four popular commercial off-the-shelf hardware platforms and reports our investigation results. Section III describes our proposed CRN testbed. Finally, Section IV concludes this paper. II. O FF - THE -S HELF H ARDWARE P LATFORMS FOR C OGNITIVE R ADIO N ETWORKS A CRN testbed is composed of multiple nodes. There are several popular commercial off-the-shelf hardware platforms designed for software defined radio (SDR) that may be used for building the nodes of CRN testbeds.

Fig. 1.

USRP2 with WBX RF daughterboard.

A. Universal Software Radio Peripheral 2 Universal software radio peripheral (USRP) and USRP2 provided by Ettus Research are widely used hardware platforms in the areas of SDR and CR. USRP2 is the second generation of USRP and it became available in 2009 [16]. USRP2 consists of a motherboard and one or more selectable RF daughterboards, as shown in Fig. 1. The major computation power on the motherboard comes from a Xilinx Spartan-3 XC3S2000 field programmable gate array (FPGA). The motherboard is also equipped with a 100 MS/s 14-bit dual channel analog-to-digital converter (ADC), a 400 MS/s 16-bit dual channel digital-to-analog converter (DAC), and a Gigabit Ethernet port that can be connected to a host computer. There are some RF daughterboards available for USRP2. Among them, a newly developed RF daughterboard called WBX covers a wide frequency band of 50 MHz to 2.2 GHz, with a nominal noise figure of 5-7 dB. Signals are received and down-converted by USRP2 and its RF daughterboard, then they are sent to a host computer for further processing through the Gigabit Ethernet. Most of the processing work is conducted by the host computer. Data to be transmitted are sent from the host computer to USRP2 through the same Gigabit Ethernet, before they are up-converted and transmitted by USRP2 and its RF daughterboard. A major advantage of USRP2 is that it works with GNU Radio [17], a open source software with plenty of resources for SDR and a lot of users, which simplifies and eases the usage of USRP2. On the other hand, USRP2 is not perfect. First, the Gigabit Ethernet connecting USRP2 and its host computer introduces random time delays. The operating system on the host computer may also introduce random time delays. According to our measurement, the minimum response delay of USRP2 is in the range of several milliseconds to tens of milliseconds [11]. Such random response delay may be okey for half-duplex communications. However, in CRNs, full-duplex communications are desired and random response delays may deteriorate the performance of CRNs. Second, USRP2 is usually used together with GNU Radio that runs on a host computer. When the instantaneous bandwidth of USRP2

Fig. 2.

SFF SDR DP with low-band tunable RF module.

increases, the CPU on the host computer gets much busier. Thus a multi-core CPU is desired, as what Virginia Tech has done in their network testbed. When the instantaneous bandwidth of USPR2 becomes wider and the processing tasks on GNU Radio becomes much more complex, a common CPU may not be competent enough for real-time processing. B. Small Form Factor Software Defined Radio Development Platform The small form factor (SFF) software defined radio (SDR) development platform (DP) provided by Lyrtech in collaboration with Texas Instruments (TI) and Xilinx is a self-contained platform consisting of three separate boards: digital processing module, data conversion module and RF module, as shown in Fig. 2 [18], [19], [20]. The digital processing module is designed based on TMS320DM6446 system-on-chip (SoC) from TI and Virtex4 SX35 FPGA from Xilinx. The TMS320DM6446 SoC has a C64x+ digital signal processor (DSP) core running at 594 MHz together with an advanced RISC machine (ARM9) core running at 297 MHz. The digital processing module also comes with a 10/100 Mb/s Ethernet port. The data conversion module is equipped with a 125 MS/s 14-bit dual channel ADC and a 500 MS/s 16-bit dual channel DAC. It also has a Xilinx Virtex-4 LX25 FPGA. The low-band tunable RF module can be configured to have either 5 MHz or 20 MHz bandwidth with working frequencies of 200-1050 MHz for the transmitter and 200-1000 MHz for the receiver. The nominal noise figure of this RF module is 5 dB. Other frequency bands may be covered by several other RF modules. There are two favorable features of SFF SDR DP for CRN testbeds. One is that SFF SDR DP is in small form factor and can be moved easily. The other is that it is capable to support full-duplex communications. But there are also two technical drawbacks to use it to build nodes of CRN testbeds. One drawback is that its computing capacity is fixed and it is not easy to upgrade to meet the needs of CRN testbeds. The other drawback is the response time delay. According to our measurement, the minimum response delay of SFF

Fig. 3.

WARP FPGA board with two radio boards.

SDR DP is about tens of milliseconds and the delay is almost constant [11]. Such a nontrivial delay is undesirable for CRN testbeds, since it may deteriorate the performance in the end. SFF SDR DP can be viewed as an example of standalone hardware platforms, whereas USRP2 is an example of computer-aided hardware platforms. A comparison between the above two hardware platforms has been reported in [21]. C. Wireless Open-Access Research Platform The wireless open-access research platform (WARP) developed by Rice University consists of an FPGA board and one to four radio boards [22], as shown in Fig. 3. The second generation of the FPGA board has a Xilinx Virtex-4 FX100 FPGA and a Gigabit Ethernet port [23], [24]. The FPGA can be used to implement the physical layer of wireless communications. There are PowerPC processors embedded in the FX100 FPGA. The radio board incorporates a dual-channel 65 MS/s 14-bit ADC and a dual-channel 125 MS/s 16-bit DAC, covering two frequency ranges of 2400-2500 MHz and 4900-5875 MHz, with a bandwidth up to 40 MHz. WARP platform is also a stand-alone hardware platform, which is its first advantage for building nodes of CRN testbeds. The second advantage of WARP is that both physical layer and MAC layer can be implemented on one FPGA, which may simplify the board design compared to an “FPGA + DSP/ARM” architecture and hence reduce time delays introduced by the interface between FPGA and DSP/ARM. However, according to [24], the Virtex-4 FPGA on WARP is not powerful enough to accommodate both transmitter and receiver functions at the same time. Thus, full-duplex communications desired by CRN testbeds can not be implemented using just one WAPR. D. Microsoft Research Software Radio Microsoft research has developed a software radio (Sora) platform [25]. Sora is composed of a radio control board (RCB) and a selectable RF board, and it works with a multicore host computer. The RCB is shown in Fig. 4.

Fig. 4.

Sora radio control board.

The RCB contains a Xilinx Virtex-5 FPGA, and it interfaces with a host computer through a peripheral component interconnect express (PCIe) interface at a rate of up to 16.7 Gb/s. Actually, RCB is an interface board for transferring digital signals between the RF board and computer memory. The RF board can be WARP radio board. Processing work including physical layer and MAC layer is conducted on the host computer. Sora is a computer-aided platform. It is an advantage for Sora to fulfill a high-throughput interface between an RF board and a host computer. However, since processing work burdens the host computer, the host computer has to be very powerful to support all the functions running in real-time. At the other hand, multi-core programming and debugging with speedup tricks is not a piece of cake. Moreover, implementing fullduplex communications on one host computer is challenging. Obviously, a host computer (or server) installed with Sora lacks mobility. III. P ROPOSED C OGNITIVE R ADIO N ETWORK T ESTBED All of the above four hardware platforms are originally designed for SDR. Two of them connect to a host computer where major processing work is performed. The other two are stand-alone hardware platforms. From the aspect of mobility, stand-alone platforms are preferable for building nodes of CRN testbeds, whereas from the aspect of software development, computer-aided hardware platforms look better, since software development and debugging on a host computer is generally easier. In [26], a compromise of the above two kinds of hardware platforms is suggested. The authors recommend to move time-critical tasks to FPGA and split MAC design with host and FPGA implementations. The solution sounds reasonable. However, to the best of our understanding, major concerns on hardware platforms for CRN testbeds are computing power and response time delay. CR introduces “intelligence” beyond SDR, like detection and learning algorithms, which means CR requires much more computing powers than SDR. A hardware platform with ample and upgradable computing power is

Radio board (RF + ADC) Rx 2

Radio board (RF + ADC) Rx 1

Memory (RAM 1) Virtex-6 FPGA (Rx) Flash memory (Flash 1)

Radio board (RF + DAC) Tx 1

Virtex-5 FPGA with PowerPC (Tx)

Radio board (RF + DAC) Tx 2

Applications

Memory (RAM 2)

Data manager

Flash memory (Flash 2)

Security manager

Routing manager

Extension port

Fig. 5.

Gigabit Ethernet

Architecture of the proposed motherboard for nodes.

Knowledge/ policy/data base Geolocation

Spectrum and channel manager

desired for building CR testbeds. On the other hand, the desired hardware platform should have least response time delay. If the response time delay is large, the throughput of CRN testbeds will seriously degrade. Moreover, the ability of full-duplex communications for the desired hardware platform is preferable. Unfortunately, none of the existing off-the-shelf hardware platforms can meet all of the above requirements. They are originally designed for SDR, instead of CR and CRN. It is time to design a new hardware platform for building the nodes of CRN testbeds.

Other learning algorithms

Decision making

Spectrum detection and prediction

Hardware abstraction layer (HAL)

Hardware platform

A. Proposed Motherboard for Nodes We propose an architecture of the motherboard for nodes of CRN testbeds. Fig. 5 shows the proposed architecture of the first generation motherboard and its major components. Two powerful FPGAs, i.e., a Xilinx Virtex-6 LX FPGA and a Xilinx Virtex-5 FX FPGA, are employed as core components on the motherboard. All the functions for physical layer and MAC layer are implemented on the two FPGAs. No external host computer is required. The proposed hardware platform is stand-alone, thus it has good mobility. The Virtex-5 FX FPGA has PowerPC cores that can be used for implementing MAC and networking functions. Physical layer functions including spectrum sensing are implemented on the two FPGAs. The Virtex-5 FPGA is employed for the transmitting data path, and it is connected to one or two RF boards as well as a Gigabit Ethernet port. The Virtex-6 FPGA is dedicated for the receiving data path, with connections to one or two RF boards and an extension port. The extension port can be used to connect with external boards to gain access to additional computing resources. The two FPGAs are connected together directly via low-latency connections. Both of the FPGAs have the access to their own external memories. The use of two FPGAs is a trade-off between performance and cost. The proposed motherboard can provide enough and upgradable computing resources for nodes of CRN testbeds. And the time delay between the two FPGAs is trivial. Moreover, full-duplex communications are supported with one proposed motherboard and two or more RF boards. Existing RF boards from WARP or USRP2 can be reused to interface with the proposed motherboard. Moreover, customized RF boards are

Fig. 6.

Proposed functional architecture for nodes.

supported. A node for CRN testbeds can be built using one proposed motherboard equipped with two or more RF boards. B. Proposed Functional Architecture for Nodes of CRN Testbeds From the aspect of functionality of CR, nodes of CRN testbeds can be implemented using the following proposed functional architecture plus traditional communications functions, as shown in Fig. 6. The hardware abstraction layer (HAL) is a packaged interface for upper-level functions that screens hardware-specific details. It provides data interfaces to both receiving data path and transmitting data path, as well as an access interface to other hardware-specific resources on the hardware platform. The spectrum and channel manager manages all the spectrum and channel related resources, including links, frequencies, and modulation methods. There are several functional modules interfacing with the spectrum and channel manager. The spectrum detection and prediction module provides the information regarding the availability of some frequency bands. The decision making module utilizes decision algorithms to make decisions like which channel will be used and when it will be used. More learning algorithms can be implemented as independent modules to learn and reason from the inputs. The geolocation module outputs information like the latitude

R EFERENCES … ... Node 1

Node 2

Node 3

Node N

Gigabit Ethernet

Gigabit Ethernet switch Console

Fig. 7.

Proposed cognitive radio network testbed.

and longitude of the node. The spectrum and channel manager can use such geolocation information to load prior information about current location from the knowledge/policy/data base. The routing manager employs routing algorithms to select the best route for sending and relaying data packages. While the data manager organizes all the data from upperlevel applications and the data to be relayed. The security manager provides encryption and decryption to data manager, routing manager, and spectrum and channel manager. The knowledge/policy/data base stores prior knowledge, policies, data, and experiences. After the nodes are built, a CRN testbed is ready to be established. C. Proposed Cognitive Radio Network Testbed Multiple nodes constitute a CRN testbed. Fig. 7 shows the proposed architecture for CRN testbeds. All the nodes are connected using Gigabit Ethernet to one or more console computers through one or more Ethernet switches. The console computer controls and coordinates all the nodes in the CRN testbed. This CRN testbed can be used not only for cognitive radio, but also for other applications, such as smart grid [21] and wireless tomography [27]. IV. C ONCLUSION To build a cognitive radio network testbed, popular commercial off-the-shelf hardware platforms designed for software defined radio have been introduced and investigated. In order to overcome the shortcomings of the off-the-shelf hardware platforms, an architecture of the motherboard and a functional architecture for nodes of cognitive radio network testbeds, as well as an architecture for cognitive radio network testbeds, have been proposed. The proposed cognitive radio network testbed is being built at Tennessee Technological University. ACKNOWLEDGMENT This work is funded by National Science Foundation through two grants (ECCS-0901420 and ECCS-0821658), and Office of Naval Research through two grants (N00010-10-10810 and N00014-11-1-0006).

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