Backlog Aware Scheduling for Large Buffered Crossbar Switches Aditya Dua† , Benjamin Yolken∗, Nicholas Bambos∗, Wladek Olesinski‡ , Hans Eberle‡ , and Nils Gura‡ † Qualcomm

Inc. , Campbell, CA 95008; [email protected] Stanford University, Stanford, CA 94305; {yolken,bambos}@stanford.edu ‡ Sun Microsystems Laboratories, Menlo Park, CA 94025; {wladek.olesinski,hans.eberle,nils.gura}@sun.com ∗

Abstract—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with input groups), distributes the switch fabric across multiple chips, which communicate via high speed interconnects enabled by proximity communication (PC) a recent circuit technology [2]. An OBIG switch aggregates multiple input flows inside the switch fabric, thereby significantly reducing the amount of memory required for internal buffers, vis-`a-vis a conventional buffered crossbar, which has buffers at every crosspoint. Thus, the OBIG architecture is promising for realizing terabit switches with hundreds of ports. In this paper, we study packet scheduling algorithms which help realize the potential of OBIG-like switch architectures. Our emphasis here is on designing backlog aware scheduling algorithms, while ensuring desirable traits such as low computational complexity and scalability. We demonstrate the efficacy of our proposed scheduling algorithms with respect to performance metrics such as backlog and load balancing via simulations under a variety of scenarios.

I. I NTRODUCTION Routing and packet switching are integral to the functioning of any data communication network. As the Internet grows in size and user demands for high speed data soar, packet switches in core routers will need to have hundreds of ports and handle data rates of the order of several terabits per second. Switches of this magnitude require a scalable architecture. The crossbar (input queued) architecture has been a popular choice for packet switches [3] over the years. However, crossbars do not scale well with the size of the switch. Further, the performance of a crossbar is heavily dependent on the scheduling/arbitration algorithm used to match input ports to output ports. The computation of a schedule can get quite cumbersome as the switch size increase, in spite of the various low complexity algorithms which have appeared in the literature (e.g., see [4]–[9] and references therein). The buffered crossbar switch architecture was proposed as an alternative to decouple the scheduling process into two stages and hence reduce overall complexity [10]–[12]. However, a buffered architecture entails a packet buffer at each crosspoint in the fabric. Thus, the memory requirements of this architecture become impractical as the switch grows in size. Other multi-stage architectures have been studied in the past (e.g. Clos networks), which realize a large switch by interconnecting several small switches [13]. Such architectures, however, result in high latency and also require complex

routing between the several stages of the switch. Recently, a single stage, distributed switch architecture, OBIG (output buffers with input groups) was proposed in [1] and leveraged for enabling a switch with 256 ports and an aggregate bandwidth of 2.5 Tbps. An OBIG switch is distributed over multiple chips which communicate via high speed interconnects called proximity communication (PC) links1 . Each chip is equipped with internal buffers at strategically chosen crosspoints, as described in Section II. The overall memory requirements of this architecture are significantly less than that of a conventional buffered crossbar. To fully realize the potential of OBIG switches, we need input and output scheduling/arbitration algorithms which have low computational complexity, are easy to implement in hardware, and scale attractively with switch size. Further, it is important for the schedulers to perform well with respect to metrics such as delay/ backlog, fairness, etc. It was demonstrated in [9] in the context of input queued switches that backlog aware scheduling algorithms significantly outperform algorithms which are oblivious to queue backlogs. With this motivation, we explore backlog aware scheduling algorithms for OBIG-like switches in this paper, with a view toward low complexity implementation and scalability. The remainder of this paper is organized as follows. We begin in Section II by describing in detail the switch model and the associated packet scheduling problem. Section III discusses our proposed scheduling algorithms for both the input as well as output arbitration. In Section IV, we evaluate our algorithms via simulation, showing that they perform well under different types of loading. Finally, we conclude and furnish directions for future work in Section V. II. S WITCH M ODEL AND

THE

S CHEDULING P ROBLEM

In this section, we describe the logical architecture of a multi-chip crossbar switch with internal buffering. The architecture we consider here is very close to that described by Olesinski et al. in [1] for OBIG switches. Consider an N × N switch with N input ports and N output ports, physically distributed across M chips. The chips communicate via high speed interconnect links, such as proximity communication (PC) links [2]. Each chip has K = N/M input ports and 1 Proximity communication relies on capacitative coupling between overlapping chips to provide substantial increase in bandwidth over traditional chip packing technologies such as area ball bonding [2].

IN1

OUT1

IN2

IN3

OUT2

OUT3

IN4

OUT4

Fig. 1. Distributed buffered crossbar switch with N = 4 ports, M = 2 N = 2 inputs and outputs per chip. Each input has N chips, and K = M VOQs (not shown). At each time slot, the input scheduler on each chip maps its KN VOQs to N internal buffers. The output scheduler for each port then arbitrates between M such buffers.

K output ports, as depicted in Fig. 1. There are N virtual output queues (VOQs) at each input port to prevent head-ofline (HOL) blocking. The j th VOQ at the ith input port buffers packets destined from the ith input port to the j th output port. Each chip is equipped with internal buffers at some of its crosspoints. Thus, a packet traverses the switch in two stages — in the first stage, it is transferred from its input VOQ to a designated internal buffer and in the second stage, it is transferred from the internal buffer to its desired output port. We assume fixed size packets/cells in this paper. We consider an architecture with N internal buffers per chip. Thus, the total number of internal buffers in the switch is N M . In contrast, the total number of internal buffers in a conventional buffered crossbar is N 2 . Note that N 2 ≫ N M for a switch with a large number of ports. The internal buffers are logically arranged in “columns”. Each column of internal buffers corresponds to a single output port. In particular, there are M buffers per column, i.e., M buffers per output port. The first buffer in the j th column stores packets destined from input ports 1, . . . , K to the j th output port. More generally, the pth buffer in the j th column stores packets destined from input ports (p − 1)K + 1, . . . , pK to the j th output port. The internal buffers are implemented as FIFO (first-in firstout) queues. Each internal buffer is shared by K different input ports, all from the same chip. Packets arriving from all these input ports are stored in a single queue and served according to a FIFO discipline. The advantage of such an architecture is that it allows for dynamic memory sharing and keeps the overall memory requirements, and hence, the size of the switch fabric small. The disadvantage is that it may lead to HOL blocking effects and unfairness issues at the internal buffers, especially under non-uniform loading conditions. This disadvantage can potentially be overcome by splitting each internal buffer into K virtual queues, albeit at the expense of significantly higher memory requirements. In

fact, the memory requirement of this solution would be equal to that of a conventional buffered crossbar, thereby nullifying the advantages of the OBIG architecture. There is one input scheduler per chip, which arbitrates between K input ports on that chip and all the N output ports, independently of the input schedulers of other chips. We will collectively refer to the K input ports on a chip as an input group, similar to [14]. For example, consider the input scheduler of chip 1, which arbitrates between input ports 1, . . . , K and the N output ports. Suppose the scheduler chooses to forward a packet from the first input port to the j th output port. The HOL packet of the j th VOQ at the first input port is transferred to the first internal buffer in the j th column. This buffer is located on the first chip if j ≤ K, on the second chip if K < j ≤ 2K, and so on. If the buffer is not located on the first chip, the packet is transported across a PC link, which enables communication between different chips. Note that each internal buffer is accessed by only a single input scheduler, thereby eliminating the possibility of contention that may have arisen due to distributed and independent decision making by the input schedulers. Remark: To simplify discussion, in this paper, we assume that the flow control between the internal buffers and input schedulers is fast enough, so that the most recent backlog state of the internal buffers is known to the input schedulers. This prevents the input schedulers from sending a packet to an internal buffer which is full and thereby eliminates the possibility of dropped packets. In practice, as the number of chips in the switch increases, the internal buffer size needs to be increased to compensate for the rise in round-trip times. For instance, in [1] it was shown that in a 256-port OBIG switch with 10 Gbps ports spread over M = 16 chips, the longest input-to-output path would have up to 8 cells in transit (cell size 128 bytes). Finally, each output port is equipped with its own output scheduler, which arbitrates between M internal buffers (FIFO queues). While the input of the switch is akin to a K × N crossbar (one per chip), each output port can be thought of as an independent parallel-queue single-server systems with M competing queues. Both models have received considerable attention in the queuing and scheduling literature in isolation. Their performance, however, has not been examined in conjunction in the past. To summarize, the scheduling process is comprised of two logical phases in every time slot. In the first phase, the input scheduler of each chip “matches” the K input ports on that chip to the N output ports and transfers the HOL packets of the selected input VOQs to the appropriate internal buffers. In the second phase, the output scheduler of each output port transfers the HOL packets of one of the M internal buffers associated with that port to the output of the switch. III. S CHEDULING A LGORITHMS FOR D ISTRIBUTED S WITCHES WITH I NTERNAL B UFFERING In this section, we study input and output scheduling algorithms for the buffered multi-chip switch architecture

described in Section II. As mentioned earlier, our focus here in on scalable, low complexity scheduling algorithms, suitable for large high speed switches envisioned with the above distributed architecture. A. Input Scheduling Recall that each chip is equipped with its own input scheduler, which arbitrates between K input ports and N output ports. Thus, the input of each chip is effectively a K × N crossbar. Several scheduling algorithms have been proposed in the literature for non-blocking crossbar switches. Most notable amongst these is the maximum weight matching (MWM) algorithm [15], often used as a performance benchmark. While the MWM algorithm has several desirable properties like throughput optimality and no dependence on input traffic statistics, it is computationally intensive and hard to implement in large switches. Much work has therefore been undertaken on developing schedulers which achieve the throughput optimality of MWM at lower complexity [7], [8]. On a different strand of research, several authors have proposed practical low complexity (typically sub-optimal) schedulers with a view toward easy implementation in hardware [4]– [6]. While such schedulers perform quite well under uniform loading of the switch, their performance degrades significantly under heavy and non-uniform loading. In this paper, we will focus on the BA-WWFA algorithm, which is a backlog aware version of the basic WWFA algorithm [5]. The Ba-WWFA algorithm was proposed [9]. We now briefly review the WWFA algorithm, followed by BAWWFA. 1) The WWFA algorithm: In the WWFA algorithm [5], each VOQ is assigned a request flag, which is set to ON in the current time slot if the VOQ is non-empty, and set to OFF otherwise. WWFA first examines the VOQs swept by wave 1, as depicted in Fig. 2 for a 4 × 4 crossbar. Note that the VOQs swept by a wave are non-conflicting, i.e., they can all be scheduled simultaneously. A grant is issued to a VOQ swept by wave 1 if it has a request (flag is ON). Next, WWFA examines VOQs swept by wave 2 and issues them grants if they are non-empty, and the requested output is available. The process continues until all waves have been processed. This procedure, called wavefront propagation, is repeated in every time slot. The HOL packets of all VOQs to which grants were issued are then transferred to the appropriate internal buffers. The wave priorities are rotated in round robin fashion in every time slot in the interest of fairness. Remark: While we illustrated wavefront propagation for a symmetric switch (K = N ), the idea naturally extends to a K × N with K < N , which is the scenario of interest to us in this paper. Specifically, there are exactly max(K, N ) waves associated with a K × N crossbar. WWFA is attractive due to its simplicity, which stems from the choice of wave patterns. Under WWFA, each VOQ can make a local grant decision based solely on the status of its own request flag and the outcome of the previous wave processing (communicated to it by neighboring VOQs from

the “left” and the “top”). This local decision making ability vastly simplifies hardware implementation of WWFA. Another key property of WWFA is that it always produces a maximal matching. On the downside, WWFA does not incorporate VOQ backlogs into its scheduling decisions. This results in performance degradation, especially under non-uniform loading of the switch. 2) The BA-WWFA algorithm: The BA-WWFA algorithm [9] is a backlog aware derivative of the basic WWFA algorithm. Instead of rotating wave priorities in a round robin fashion, the leading wave in each wavefront propagation cycle is picked based on VOQ backlogs. In particular, the “weight” of each wave is computed as a sum of the backlogs of the VOQs which are swept by that wave, and the wave with the largest weight is picked as the first wave. Backlog information from the previous time slot can be used to compute the wave weights, with minimal impact on performance. Thus, the scheduler does not have to poll each VOQ for its backlog, thereby retaining the local decision making feature of WWFA. Further, BA-WWFA preserves maximal matching property of WWFA, with the added advantage of backlog awareness, which improves its throughput/average delay performance. Remark: The implementation of WWFA and BA-WWFA can be made even more efficient by exploiting parallelization OEG07. B. Output scheduling Each output port is equipped with its own output scheduler, which arbitrates between the column of M internal buffers assigned to that output port. Note that since each input buffer is a FIFO queue, the output scheduler can only arbitrate between input groups (the k th group comprises of input ports on the k th chip) and not between individual input ports. Each output port is effectively an M parallel-queue singleserver system. Scheduling parallel queues on a single server is a classical queuing problem and has received much attention in the literature. See [16] for several variations of this problem. Parekh et al. [17] studied single server scheduling in the context of integrated services networks and focused on issues like per-flow fairness. We will focus our attention on three simple scheduling algorithms here: 1) Round Robin (RR): The round robin scheduler, as the name suggests, schedules the internal buffers in cyclic fashion. If the current buffer is empty, then no packet is sent to the output and the slot is “wasted”. While RR is very simple to implement, it is oblivious to the backlogs of the internal buffers, which severely degrades performance, especially under non-uniform loading conditions. 2) Work Conserving Round Robin (WCRR): The WCRR scheduler arbitrates between queues in a fashion similar to RR, except that it does not “waste” any time slot. If WCRR finds the designated internal buffer to be scheduled empty, it polls the remaining internal buffer in cyclic fashion, and schedules the HOL packet of the first non-empty queue it finds. Thus, a

W av e

Wavefront propagation

1

1

2

3

4

2 3 4

Fig. 2. The left side shows the wave pattern used by WWFA for a 4 × 4 IQ switch (implemented as a crossbar). The j th crosspoint in the ith row maps to VOQ index N (i − 1) + j. The right side shows the configuration subset SW and also the one-one correspondence between waves and configurations.

packet will be scheduled as long as there is at least one nonempty internal buffer. The WCRR scheduler is backlog aware in a “binary” way, in that it distinguishes between empty and non-empty internal buffers, unlike RR, which simply wastes a slot if it encounters an empty buffer. 3) Longest Queue First (LQF): The LQF policy picks the internal buffer with the largest backlog and transfers its HOL packet to the output port. Intuitively, LQF tries to achieve a load balancing effect between different input groups. We will demonstrate this key property of LQF via experimental results in Section IV. Thus, LQF is the most backlog aware of all three schedulers discussed here. LQF naturally adapts to non-uniform loading conditions by devoting more attention to buffers with larger backlogs. C. Scheduling algorithms Combining the input and output schedulers discussed above, we construct three different scheduling algorithms for distributed crossbar switch fabrics with internal buffers. (a) BA-WWFA-RR: This algorithm uses BA-WWFA to arbitrate between input ports and internal buffers and RR to arbitrate between internal buffers and output ports. The algorithm is oblivious to the backlogs of the internal buffers. (b) BA-WWFA-WCRR: This algorithm used BA-WWFA as the input scheduler and WCRR as the output scheduler. This, it is responsive to the backlogs of the internal buffers in a binary way, in the sense described above. (c) BA-WWFA-LQF: This algorithm combines BA-WWFA with LQF and is therefore responsive to the backlogs of the input VOQs as well as the input buffers. As mentioned before, the superiority of BA-WWFA over WWFA for crossbar switches was established in [9]. IV. P ERFORMANCE E VALUATION In this section, we experimentally evaluate the performance of our three main proposed algorithms: (1) BA-WWFA-RR, (2) BA-WWFA-WCRR, and (3) BA-WWFA-LQF. We do this by employing two metrics, described in more detail below,

under two different loading schemes: one uniform and one highly non-uniform. Our first metric is the long run average delay per packet. This is a commonly used and easily computable benchmark which reflects aggregate performance across the entire system. All else being equal, lower delays generally correspond to more efficient scheduling, smaller backlogs, and higher throughput. The previous value reflects the system as a whole, without considering imbalances between different packet flows. Thus, as a second performance criterion we examine the backlog fairness of each algorithm. To do this, we partition the switch packet flows into M N groups of size K each (recall that the switch has N ports, M chips, and K chips per port), one for each chip-output port combination. Note that these are the flows that are aggregated by each internal buffer; thus, backlogs and delays at this level of resolution reveal qualities about the system potentially hidden by the first metric. In particular, we look at the difference between the largest and smallest average backlogs among these groups. These backlogs are taken system-wide, i.e. they include both the input and internal buffers. In particular, if these groups are indexed as (1, 1), (1, 2), . . . , (M, N ), and the corresponding average occupancies for each group are encoded in the vector b = (b11 , b12 , . . . bMN ) then our backlog fairness metric is defined as: f (b) = max |bij − bkl | i,j,k,l

(1)

i.e., the largest difference in this group. Although many other fairness criteria are possible, we believe that this particular function captures the potential imbalances in our switch model. Moreover, as opposed to delay-based fairness criteria, ours is more directly linked to the packet arrival rates. All results presented here are for a 12 × 12 switch, i.e, N = 12. The simulated switch consists of three chips, i.e. M = 3, and the internal buffers each have a capacity of 20 packets. Each data point reported on the performance curves is based on a simulation length of 10, 000 time slots.

35

3.5 BA−WWFA−RR BA−WWFA−WCRR BA−WWFA−LQF

BA−WWFA−WCRR BA−WWFA−LQF 3

Scheduler backlog fairness

Average delay per packet

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BA−WWFA−WCRR BA−WWFA−LQF 10 Scheduler backlog fairness

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(d) Backlog Fairness Metric Under Non-uniform Load

Fig. 3. Simulation results for 12 × 12 switch. Each plot shows the average delay per packet vs. the average load per switch input port for various algorithms / switch configurations.

Packets are assumed to arrive according to an independent and identically distributed (i.i.d.) Bernoulli process to each input VOQ, possibly with different rates. A. Uniform Loading We first consider the case of uniform loading. In particular, λ packets arrive at a rate N to all VOQs. λ is varied from 0.05 to 0.95 to vary the load per input port, viz. λ. The average delay per packet as a function of λ is depicted in Fig. 3(a). We see that BA-WWFA-WCRR and BA-WWFA-LQF produce nearly identical average delays at all loads; moreover, these are both superior to BA-WWFA-RR. The reason for the bad performance of the latter algorithm is evident — even under uniform loading, there is a high probability that one internal buffer is empty while another on the same output port contains packets. Thus, round robin scheduling leads to “wasted” time slots that could be used to service packets. This effect becomes more significant as load is increased. On the other hand, the first two algorithms always remove packets from these internal buffers, if there are packets to remove. Thus, from a holistic viewpoint, the total occupancy

in each case is nearly the same and hence the average delays are nearly the same. This service is distributed differently in each case, however, as shown by the backlog fairness curves in Fig. 3(b). BAWWFA-RR is not shown on this plot because it is significantly worse than the other two. We see that for low to medium loads (λ ≤ 0.85), the backlogs are more evenly distributed by BaWWFA-WCRR than BA-WWFA-LQF; because of the uniform nature of the loading, using BA-WWFA-LQF does not produce many advantages. Under very high loads (λ > 0.85), however, BA-WWFA-LQF is superior to BA-WWFA-WCRR. In these cases, the system is closer to capacity and hence buffer size differences can become more significant. B. Non-uniform Loading We now switch to the case of highly non-uniform loading, a setup which potentially places more stress on scheduling algorithms. In particular, we assume that packets arrive at a rate λ1 to VOQs which correspond to input port i and output port i, and at a rate λ2 = N0.5 −1 to all other VOQs. The total

TABLE I S UMMARY OF A LGORITHMS AND T HEIR P ERFORMANCE Scheduler Type

Input Backlog Awareness

Output Backlog Awareness

Heavy, Uniform Load Average Delaya

Heavy, Non-uniform Load Average Delayb

BA-WWFA-RR

Yes

No

16.99

1121.97

BA-WWFA-WCRR

Yes

Partial

7.94

6.74

BA-WWFA-LQF

Yes

Yes

7.93

6.73

a Case b Case

Remarks Performs poorly under nonuniform loading Good fairness under uniform loading, moderate load Superior backlog fairness under non-uniform loading

of λ = 0.9 for all input ports. of λ1 = 0.4, implying λ = 0.9 for all input ports.

load per input port, viz. λ = λ1 + 0.5 is varied by varying λ1 from 0.05 to 0.45. The average delay per packet as a function of λ is depicted in Fig. 3(c). In contrast to the uniform case, using BA-WWFARR at the output has a catastrophic impact on the average delay performance. This is clearly a result of asymmetry: certain internal buffers now have significantly greater input flow rates than others, yet BA-WWFA-RR treats all of them identically. As the load on the switch increases, the fraction of “wasted” time slots under BA-WWFA-RR becomes significant, and these “overtaxed” buffers are likely to reach capacity. This backpressure prevents the input scheduler from moving packets into these queues, leading to a significant backlog in the input VOQs. The other two algorithms, however, continue to perform well and at nearly the same level for all loads. As mentioned before, both service packets from the input buffers at the maximum rate. Thus, both produce nearly identical systemwide average delays. The backlog fairness results are shown in Fig. 3(d). As before, we omit BA-WWFA-RR because it is significantly worse than the other two. We can see that in this asymmetric case BA-WWFA-LQF distributes backlogs more evenly. This difference becomes more significant as the load increases. The reasoning for this is straightforward. Under BA-WWFAWCRR, certain internal buffers have much higher occupancies than others. BA-WWFA-LQF, on the other hand, seeks to “even out” the lengths of these. Thus, it provides a more fair result, at least with regards to our backlog-based metric. A comparative summary of our proposed scheduling algorithms and their performance in the previous two sets of simulations is enumerated in Table I. V. C ONCLUSIONS In this paper, we have described a switch architecture which decouples the input and output arbitration mechanisms via internal buffering and distributes the switching fabric across multiple chips. These characteristics allow for more efficient scheduling and better scalability than the commonly used input-queued crossbar or buffered crossbar designs. We proposed and evaluated three different scheduling algorithms with varying degrees of backlog awareness for this switch

architecture. Our simulations show that having the latter on both the input and output sides offers significant performance improvements with respect to backlog fairness, especially under non-uniform loading. Our ongoing research involves evaluating the performance of the proposed algorithms for bigger switches, under a variety of loading patterns and packet arrival processes. We are also investigating the performance of our algorithms as a function of the buffer sizes and the degree of distribution of the switch (i.e., number of chips). We are also in the process of benchmarking performance relative to throughput optimal scheduling algorithms. R EFERENCES [1] W. Olesinski, H. Eberle, and N. Gura, “OBIG: the architecture of an output buffered switch with input groups for large switches,” in Proc. IEEE Globecom’07, Washington, DC, Nov. 2007. [2] R. Drost, R. Hopkins, and I. Sutherland, “Proximity communication,” in Proc. IEEE Custom Integrated Circuits Conf.’03, Sep. 2003, pp. 469– 472. [3] M. Marsan, A. Bianco, E. Filippi, P. Giaconne, E. Leonardi, and F. Neri, “On the behavior of input queueing switch architectures,” European Trans. Telecommun. (ETT), vol. 10, no. 2, pp. 111–124, Mar./Apr. 1999. [4] T. Anderson, S. Owicki, J. Saxe, and C. Thacket, “High speed switch scheduling for local area networks,” ACM Trans. Comput. Syst., vol. 11, no. 4, pp. 319–352, Nov. 1993. [5] Y. Tamir and H. Chi, “Symmetric crossbar arbiters for VLSI communication switches,” IEEE Trans. Parallel Distrib. Syst., vol. 4, no. 1, pp. 13–27, Jan. 1993. [6] R. LaMaire and D. Serpanos, “Two-dimensional round-robin schedulers for packet switches with multiple input queues,” IEEE/ACM Trans. Netw., vol. 2, no. 5, pp. 471–482, Oct. 1994. [7] K. Ross and N. Bambos, “Local search scheduling algorithms for maximum throughput in packet switches,” in Proc. IEEE Infocom’04, Hong Kong, Mar. 2004, pp. 1158–1169. [8] A. Dua and N. Bambos, “Scheduling with soft deadlines for input queued switches,” in Proc. Allerton Conf. on Commun., Comput., and Contr., Allerton, IL, Sep. 2006. [9] A. Dua, N. Bambos, W. Olesinski, H. Eberle, and N. Gura, “Backlog aware low complexity schedulers for input queued packet switches,” in Proc. Hot Interconnects’07, Aug. 2007, pp. 39–46. [10] T. Javidi, R. Magill, and T. Hrabik, “A high throughput algorithm for buffered crossbar switch fabrics,” in Proc. IEEE ICC’01, Jun. 2001, pp. 1581–1591. [11] L. Mhamdi and M. Hamdi, “Cbf: A high performance scheduling algorithm for buffered crossbar switches,” in Proc. IEEE HPSR’03, Jun. 2003, pp. 67–72. [12] S. Chuang, S. Iyer, and N. McKeown, “Practical algorithms for performance guarantess in buffered crossbars,” in Proc. IEEE Infocom’05, Mar. 2005.

[13] J. Walrand and P. Varaiya, High-Performance Communication Networks, 2nd ed. San Mateo, CA: Morgan Kaufmann, 1999. [14] W. Olesinski, H. Eberle, and N. Gura, “PWWFA: The parallel wrapped wavefront arbiter for large switches,” in Proc. IEEE Workshop HPSR’07, New York, NY, May-Jun. 2007. [15] N. McKeown, A. Mekkittikul, V. Anantharam, and J. Walrand, “Achieving 100% throughput in an input-queued switch,” IEEE Trans. Commun., vol. 47, no. 8, pp. 1–10, Jul. 2004. [16] J. Walrand, An Introduction to Queueing Networks. Englewood Cliffs, NJ: Prentice Hall, 1988. [17] A. Parekh and R. Gallager, “A generalized processor sharing approach to flow control in integrated services networks: the single-node case,” IEEE/ACM Trans. Netw., vol. 1, no. 3, pp. 344–357, Jun. 1993.

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Sep 20, 2017 - at the ADC inputs to reduce RF interference that may have been picked up by the twisted pair. The analog inputs have no self-rectification mechanism that would convert. RF interference into a spurious DC level at the input pin, thus ma